irqController.pld

GAL22V10
irqController

; not tested yet
;
; This is a simple interrupt controller 
; * Supports four priority interrupts, with IRQ3 being the highest priority
; * IRQ is signalled when there are any interrupts.
; * D1..D0 is the index of the highest priority pending interrupt.
; * Chip select tristates the D1 and D0 pins and gates write operations.
;   Generally driven by the IO decoding circuitry.
; * BE keeps us from driving the bus when something else is writing to it. 
;   Generally driven by R/W 
; * Data ENable tristate Dn but allows writes. Use this to read priority encoded interrupts.
; * BEHT tristates OUT and T but allows writes. Use this to read one-hot (OUT) or all pending interrupts (T)
; * H3..T0 is a one-hot representation of the pending interrupts, for 
;   selecting child controllers
; * T3..T0 contain all of the latched interrupts.
; * ACK removes the highest pending interrupt

; 1/13  ; 2/14  ; 3/15  ; 4/16  ; 5/17  ; 6/18  ; 7/19  ; 8/20  ; 9/21  ; 10/22 ; 11/23 ; 12/24
Clock   /CS     /BE     BED     BEHT    /RST    /IRQ0   /IRQ1   /IRQ2   /IRQ3   NC      GND
/ACK    D1      D0      H3      H2      H1      T0      T1      T2      T3      /IRQ    VCC

; Signal the interrupt asynchronously
IRQ = IRQ0 + IRQ1 + IRQ2 + IRQ3

; latch IRQ0-3 into T0-3
T0.R = IRQ0 + T0*/CS + T0*/ACK
T1.R = IRQ1 + T1*/CS + T1*/ACK + T1*T0*ACK*CS
T2.R = IRQ2 + T2*/CS + T2*/ACK + T2*T1*ACK*CS + T2*T0*ACK*CS
T3.R = IRQ3 + T3*/CS + T3*/ACK + T3*T2*ACK*CS + T3*T1*ACK*CS + T3*T0*ACK*CS

; T0 and H1 to H3 are a one-hot representation.
H1.R = /T0*IRQ1 + T1*/T0*/CS
H2.R = /T1*/T0*IRQ2 + T2*/T1*/T0*/CS
H3.R = /T2*/T1*/T0*IRQ3 + T3*/T2*/T1*/T0*/CS

; Priority Encoder
/D0.R = T0 + T2 * /T1*/T0
/D1.R = T2 * /T1*/T0 + T3 * /T2*/T1*/T0

D0.E = CS*BED*/BE
D1.E = CS*BED*/BE
T0.E = CS*BEHT*/BE
T1.E = CS*BEHT*/BE
T2.E = CS*BEHT*/BE
T3.E = CS*BEHT*/BE
H1.E = CS*BEHT*/BE
H2.E = CS*BEHT*/BE
H3.E = CS*BEHT*/BE


AR = RST

DESCRIPTION