All the VHDL files

afficheur_deroulant_top

-- Fichier top

library ieee;

use ieee.std_logic_1164.all;

entity circuit1 is
  port (
	clock,rst: in std_logic;
	start,load : in std_logic; -- start is sw0 and sw1 is load
	hex0 : out std_logic_vector(6 downto 0);
	hex1 : out std_logic_vector(6 downto 0);
	hex2 : out std_logic_vector(6 downto 0);
	hex3 : out std_logic_vector(6 downto 0)
  ) ;
end entity ; -- circuit1

architecture struct of circuit1 is

component machine_etat_affichage is
  port (
  	clock,reset: in std_logic;
  	start,load : in std_logic; -- start is sw0 and sw1 is load
	hex0 : out std_logic_vector(6 downto 0);
	hex1 : out std_logic_vector(6 downto 0);
	hex2 : out std_logic_vector(6 downto 0);
	hex3 : out std_logic_vector(6 downto 0)
  ) ;
end component ; -- machine_etat_affichage

component freq_1hz is
  port (
	clock,rst: in std_logic;
	clock_out : out std_logic
);
end component ; -- freq_1hz

signal intermediaire:std_logic; -- lien entre clock_out de freq_1hz et clock de machine_etat


begin
  
freq_1hz_1:freq_1hz port map(clock => clock,rst=>rst,clock_out=>intermediaire);

machine_etat_affichage_1:machine_etat_affichage port map(clock=>intermediaire,reset=>rst,hex0=>hex0,hex1=>hex1,hex2=>hex2,hex3=>hex3,start=>start,load=>load);

end architecture ; -- struct

bloc_aff

-- ------------------------
-- 	fichier bloc_aff
-- 	Exercice 2
-- 	Par Pierre Zemb
-- 	16 octobre 2014
--	Affichage de ISEN sur les 7 segments
-- ------------------------

library ieee;
 
use ieee.std_logic_1164.all;

entity bloc_aff is
  port (
	sw0,sw1 : in std_logic; -- mode in
	hex0 : out std_logic_vector(6 downto 0)
  ) ;
end entity ; -- bloc_aff

architecture arch of bloc_aff is

begin
--	Lettre I
	hex0 <= '1111001' when not sw0 and not sw1
--	Lettre S
	hex0 <= '0010011' when sw0 and not sw1
--	Lettre E
	hex0 <= '0000110' when not sw0 and sw1
--	Lettre N
	hex0 <= '1001000' when sw0 and sw1

end architecture ; -- arch

div_freq1

-- ------------------------
-- 	entity div_freq
-- 	Par Pierre Zemb
-- 	23 octobre 2014
--	https://stackoverflow.com/questions/15053008/vhdl-clock-divider-counter-duty-cycle
-- ------------------------

library ieee;

use ieee.std_logic_1164.all;

entity freq_1hz is
  port (
	clock,rst: in std_logic;
	clock_out : out std_logic
);
end entity ; -- freq_1hz

architecture beh of freq_1hz is

-- clock is 50MHz, we need 1HZ, so we need to count to 50 000 000.

	signal s_cpt : natural range 0 to 50000000;
	signal s_clock_out : std_logic;

begin

-- Definition of processess
some_process : process( clock,rst )

begin
if rst='0' then
	s_cpt <= 0;
	s_clock_out <= '0';

elsif rising_edge(clock) then
	if s_cpt=50 then
		s_cpt<=0;
		s_clock_out <= not s_clock_out;
	else
		s_cpt<=s_cpt+1;
	end if ;
end if ;
	
end process ; -- some_process

clock_out <= s_clock_out;

end architecture ; -- beh

div_freq5

-- ------------------------
-- 	fichier div_freq5
-- 	Par Pierre Zemb
-- 	23 octobre 2014
--	Diviseur de fréquence slide 61
-- ------------------------

library ieee;

use ieee.std_logic_1164.all;

entity div_freq5_pulse is
  port (
	clock,rst: in std_logic;
	pulse_out : out std_logic
);
end entity ; -- div_freq5_pulse

architecture beh of div_freq5_pulse is

	signal s_cpt : natural range 0 to 4;

begin

-- Definition of processess
some_process : process( clock,rst )

begin
if rst='0' then
	pulse_out <='0';
	s_cpt <= 0;

elsif rising_edge(clock) then
	if s_cpt=4 then
		s_cpt<=0;
		pulse_out <= '1';
	else
		s_cpt<=s_cpt+1;
		pulse_out <='0';
	end if ;
	
end if ;
	
end process ; -- some_process

end architecture ; -- beh

entity_affichage

-- ------------------------
-- 	Exercice 3
-- 	Par Pierre Zemb
-- 	23 octobre 2014
--	Affichage déroulant vers la droite
-- ------------------------

library ieee;

use ieee.std_logic_1164.all;

entity machine_etat_affichage is
  port (
  	clock,reset: in std_logic;
  	start,load : in std_logic; -- start is sw0 and sw1 is load
	hex0 : out std_logic_vector(6 downto 0);
	hex1 : out std_logic_vector(6 downto 0);
	hex2 : out std_logic_vector(6 downto 0);
	hex3 : out std_logic_vector(6 downto 0)
  ) ;
end entity ; -- machine_etat_affichage

architecture arch of machine_etat_affichage is

signal s_status : natural range 0 to 4; -- wich status are we on?
type etat is(ISEN,NISE,ENIS,SENI);

signal EP : etat;

begin

P1 : process( clock,reset ) 
begin

if reset='0' then EP <= ISEN;
elsif rising_edge(clock) then
	case( EP ) is
	
		when ISEN =>
			if start='0' then -- on reste sur ISEN si start vaut 0
				EP <= ISEN;
			else -- On marque NISE sinon
				EP <=NISE;				
			end if ;
		when NISE =>
			if load='1' then -- Réinitialisation
				EP <= ISEN;
			elsif start='0' then -- blocage
				EP <= NISE;
			else -- On change la sortie
				EP <= ENIS;				
			end if ;
		when ENIS =>
			if load='1' then -- Réinitialisation
				EP <= ISEN;
			elsif start='0' then -- blocage
				EP <= ENIS;
			else -- On change la sortie
				EP <= SENI;				
			end if ;
		when SENI =>
			if load='1' then -- Réinitialisation
				EP <= ISEN;
			elsif start='0' then -- blocage
				EP <= SENI;
			else -- On change la sortie
				EP <= ISEN;				
			end if ;			
		when others =>
			EP <= ISEN;
	
	end case ;
		
end if ;

end process ; -- P1

P2 : process( EP )
begin
	case( EP ) is
	
		when ISEN =>
			hex3 <= "1111001"; -- Letter I
			hex2 <= "0010011"; -- Lettre S
			hex1 <= "0000110"; -- Lettre E
			hex0 <= "1001000"; -- Lettre N
		when NISE =>
			hex3 <= "0010011"; -- Lettre S
			hex2 <= "0000110"; -- Lettre E
			hex1 <= "1001000"; -- Lettre N
			hex0 <= "1111001"; -- Letter I
		when ENIS =>	
			hex3 <= "0000110"; -- Lettre E
			hex2 <= "1001000"; -- Lettre N
			hex1 <= "1111001"; -- Letter I
			hex0 <= "0010011"; -- Lettre S
		when SENI =>
			hex3 <= "0010011"; -- Lettre S
			hex2 <= "0000110"; -- Lettre E
			hex1 <= "1001000"; -- Lettre N
			hex0 <= "1111001"; -- Letter I
	end case ;
	
end process ; -- P2

end architecture ; -- arch

hello_world

-- ------------------------
-- 	fichier decouverte
-- 	Exercice 1
-- 	Par Pierre Zemb
-- 	9 octobre 2014
-- ------------------------


 library ieee;
 
use ieee.std_logic_1164.all;

entity decouverte is
  port (
	a,b,c : in std_logic; -- mode in
	s : out std_logic); -- mode out
	
end decouverte; -- decouverte

architecture arch_logic of decouverte is

begin

s <= a and b;

end architecture ; -- arch_logic

rapport_cyclique

-- ------------------------
-- 	fichier slides 62
-- 	Par Pierre Zemb
-- 	23 octobre 2014
--	rapport cyclique
-- ------------------------

library ieee;

use ieee.std_logic_1164.all;

entity div_freq5_pulse is
  port (
	clock,rst: in std_logic;
	clock_out : out std_logic
);
end entity ; -- div_freq5_pulse

architecture beh of div_freq5_pulse is

	signal s_cpt : natural range 0 to 4;
	signal s_clock_out : std_logic;

begin

-- Definition of processess
some_process : process( clock,rst )

begin
if rst='0' then
	s_cpt <= 0;
	s_clock_out <= '0';

elsif rising_edge(clock) then
	if s_cpt=4 then
		s_cpt<=0;
		s_clock_out <= not s_clock_out;
	else
		s_cpt<=s_cpt+1;
	end if ;
end if ;
	
end process ; -- some_process

clock_out <= s_clock_out;

end architecture ; -- beh