Beating C with an FPGA

beating-c.v

// completely untested because I don't have an FPGA or
// anything, plus I hardly know any Verilog to begin with,
// so it most likely contains very bad bugs.
module wc(
	input rst,
	input clk,

	input [7:0] char, // input data bus
	input ch_rdy, // ^ ready flag
	input ch_valid, // did we read from a valid address?

	output [N-1:0] ch_addr, // the address we want to read from
	output ch_rden, // enable reading

	output [N-1:0] w_count,
	output wc_rdy
);
	parameter N = 32;

	reg [N-1:0] ctr;
	reg [N-1:0] addr;
	reg was_space;
	reg done;
	reg rden;

	always @(posedge clk, posedge rst) begin
		if (rst) begin
			ctr  <= 0;
			addr <= 0;
			was_space <= 0;
			done <= 0;
		end else begin
			while (ctr != 'b1 /* sign-extended */) begin
				// tell the bus we want to read from this address
				rden    <= 1;

				// wait until the data is ready to be read
				@(posedge clk);
				while (!ch_rdy) @(posedge clk);
				rden <= 0;

				if (ch_valid) begin // if we read from a valid address
					// split on a space
					if (char == 8'h20) begin
						if (!was_space) ctr <= ctr + 1; // increase the counter
						was_space <= 1;
					end else was_space <= 0;
				end

				addr <= addr + 1; // go to the next address
			end

			done <= 1; // went through the entire memory space -> done!

			// wait forever (until another rst comes along)
			while (1) @(posedge clk);
		end
	end

	assign ch_addr = addr;
	assign ch_rden = rden;
	assign w_count = ctr ;
	assign wc_rdy  = done;
endmodule