Basic template for FSM in vhdl

FSM_template.vhd

-- Template para ejercicios de FSM

type state_type is (st1_name, st2_name, ...);
signal current_state, next_state : state_type;
signal output_i : std_logic;

-- Proceso dedicado al reloj
STATE_PROC:process(clk)
begin
    if(clk'event and clk = '1') then
      if(reset = '1') then
        current_state <= idle;
      else
        current_state <= next_state;
      end if;
    end if;
end process;

-- Proceso dedicado a la salida
OUTPUT_PROC:process(current_state)
begin
    if current_state = state1 then
      output_i <= ...;
    elsif
      output_i <= ...;
    else
      output_i <= ...;
    end if;
end process;

-- Proceso que decide el siguiente proceso
NEXT_STATE_PROC:process(current_state, input1, input2)
begin
    case(current_state) is
        when state1 =>
            if input1 = ... then
                next_state <= ...;
            else
                next_state <= ...;
            end if;
        when state2 =>
            if input2 = ... then
                next_state <= ...;
            else
                next_state <= ...;
            end if;
        when ... =>
            next_state <= ...;
        when others =>
            next_state <= ...;
    end case;
end process;