errors.txt

While trying to instantiate a cyclonev_ram_block:
Error (14107): WYSIWYG RAM primitive "memory_ram_inst.cache_1_inst.mem.0.0.0" uses Port A, Address port, which is inconsistent with port_a_logical_ram_depth parameter value File: //wsl$/Ubuntu-18.04/tmp/mistral-
build/out.v Line: 376783
Error (14093): Can't recognize value for port_a_last_address parameter for WYSIWYG RAM primitive "memory_ram_inst.cache_1_inst.mem.0.0.0" File: //wsl$/Ubuntu-18.04/tmp/mistral-build/out.v Line: 376783
Error (14107): WYSIWYG RAM primitive "memory_ram_inst.cache_1_inst.mem.0.0.0" uses Port B, Address port, which is inconsistent with port_b_logical_ram_depth parameter value File: //wsl$/Ubuntu-18.04/tmp/mistral-
build/out.v Line: 376783
Error (14093): Can't recognize value for port_b_last_address parameter for WYSIWYG RAM primitive "memory_ram_inst.cache_1_inst.mem.0.0.0" File: //wsl$/Ubuntu-18.04/tmp/mistral-build/out.v Line: 376783
Error (14107): WYSIWYG RAM primitive "memory_ram_inst.cache_1_inst.mem.0.0.0" uses Port B, Address port, which is inconsistent with port_b_address_width parameter value File: //wsl$/Ubuntu-18.04/tmp/mistral-buil
d/out.v Line: 376783

While trying to instantiate a cyclonev_mlab_cell:
Error (14107): WYSIWYG RAM primitive "memory_tlb_ram_inst.tlb0_inst.mem.0.0.0" uses Port A, Address port, which is inconsistent with logical_ram_depth parameter value File: //wsl$/Ubuntu-18.04/tmp/mistral-build/
out.v Line: 376956
Error (14093): Can't recognize value for last_address parameter for WYSIWYG RAM primitive "memory_tlb_ram_inst.tlb0_inst.mem.0.0.0" File: //wsl$/Ubuntu-18.04/tmp/mistral-build/out.v Line: 376956
Error (14093): Can't recognize value for data_width parameter for WYSIWYG RAM primitive "memory_tlb_ram_inst.tlb0_inst.mem.0.0.0" File: //wsl$/Ubuntu-18.04/tmp/mistral-build/out.v Line: 376956
Error (14097): WYSIWYG RAM primitive "memory_tlb_ram_inst.tlb0_inst.mem.0.0.0" has too many bits File: //wsl$/Ubuntu-18.04/tmp/mistral-build/out.v Line: 376956

source.v

  /* module_not_derived = 1 */
  /* src = "/home/lofty/mistral/flow/lutram_map.v:45" */
  cyclonev_ram_block \memory_ram_inst.cache_1_inst.mem.0.0.0  (
    .clk0(clk),
    .portaaddr(\memory_ram_inst.cache_1_inst.address_b ),
    .portadatain(\memory_ram_inst.cache_1_inst.data_b [19:0]),
    .portawe({ 1'h0, \memory_ram_inst.cache_1_inst.wren_b  }),
    .portbaddr(\memory_ram_inst.cache_1_inst.q_a [19:0]),
    .portbdataout(\memory_ram_inst.cache_1_inst.q_a [19:0]),
    .portbre(2'h1)
  ); // Line 376783
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .logical_ram_name = "bram";
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .operation_mode = "dual_port";
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_a_address_width = 9;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_a_data_width = 20;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_a_first_address = 0;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_a_first_bit_number = 0;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_a_last_address = 511;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_a_logical_ram_depth = 9;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_a_logical_ram_width = 20;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_b_address_clock = "clock0";
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_b_address_width = 9;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_b_data_width = 20;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_b_first_address = 0;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_b_first_bit_number = 0;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_b_last_address = 511;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_b_logical_ram_depth = 9;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_b_logical_ram_width = 20;
  defparam \memory_ram_inst.cache_1_inst.mem.0.0.0 .port_b_read_enable_clock = "clock0";

// [snip]

  /* module_not_derived = 1 */
  /* src = "/home/lofty/mistral/flow/lutram_map.v:9" */
  cyclonev_mlab_cell \memory_tlb_ram_inst.tlb0_inst.mem.0.0.0  (
    .clk0(clk),
    .portaaddr({ 1'h0, \memory_tlb_ram_inst.tlb0_inst.wren_b , \memory_tlb_ram_inst.tlb0_inst.address_a  }),
    .portabyteenamasks(syn__000012_),
    .portadatain(\memory_tlb_ram_inst.tlb0_inst.data_a [19:0]),
    .portbaddr({ 2'h1, \memory_tlb_ram_inst.tlb0_inst.address_a  }),
    .portbdataout(\memory_tlb_ram_inst.tlb0_inst.q_b [19:0])
  ); // Line 376956
  defparam \memory_tlb_ram_inst.tlb0_inst.mem.0.0.0 .address_width = 5;
  defparam \memory_tlb_ram_inst.tlb0_inst.mem.0.0.0 .byte_enable_mask_width = 1;
  defparam \memory_tlb_ram_inst.tlb0_inst.mem.0.0.0 .data_width = 20;
  defparam \memory_tlb_ram_inst.tlb0_inst.mem.0.0.0 .first_address = 0;
  defparam \memory_tlb_ram_inst.tlb0_inst.mem.0.0.0 .first_bit_number = 0;
  defparam \memory_tlb_ram_inst.tlb0_inst.mem.0.0.0 .last_address = 31;
  defparam \memory_tlb_ram_inst.tlb0_inst.mem.0.0.0 .logical_ram_depth = 5;
  defparam \memory_tlb_ram_inst.tlb0_inst.mem.0.0.0 .logical_ram_name = "lutram";
  defparam \memory_tlb_ram_inst.tlb0_inst.mem.0.0.0 .logical_ram_width = 20;
  defparam \memory_tlb_ram_inst.tlb0_inst.mem.0.0.0 .operation_mode = "dual_port";