test.py

from amaranth import *

class Test1(Elaboratable):
        def __init__(self):
                self.x = Signal(8)
                self.y = Signal(8)
                self.o = Signal(32)

        def elaborate(self, platform):
                m = Module()
                m.d.comb += self.o.eq(self.x * self.y.shift_left(16))
                return m

class Test2(Elaboratable):
        def __init__(self):
                self.x = Signal(8)
                self.y = Signal(8)
                self.o = Signal(47)

        def elaborate(self, platform):
                m = Module()
                m.d.comb += self.o.eq(self.x * (self.y << C(16)))
                return m

from amaranth.back import rtlil
with open("test1.il", "w") as f:
        test1 = Test1()
        ports = [test1.x, test1.y, test1.o]
        f.write(rtlil.convert(test1, ports=ports))

with open("test2.il", "w") as f:
        test2 = Test2()
        ports = [test2.x, test2.y, test2.o]
        f.write(rtlil.convert(test2, ports=ports))

test1.log

2.48. Printing statistics.

=== top ===

   Number of wires:                 72
   Number of wire bits:            273
   Number of public wires:          72
   Number of public wire bits:     273
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                152
     SB_CARRY                       10
     SB_LUT4                       142

test2.log

2.48. Printing statistics.

=== top ===

   Number of wires:                 72
   Number of wire bits:            288
   Number of public wires:          72
   Number of public wire bits:     288
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                152
     SB_CARRY                       10
     SB_LUT4                       142