Ravenslofty

#!/usr/bin/env bash
python3 generate.py "$1" > "test$1.vqm"
../quartus.sh "$PWD/test$1.vqm" test
cp "test$1/test.sof" "bit$1.sof"

Ravenslofty

Cyclone V LUT LABCELL_X2_Y1_N0 (SOF format)

LUT bits are inverted.

0x26B47   0x26B48   0x26B49   0x26B4A
1111 1100 1101 1110 1111 1011 0001 1000
^^^^      ^^ ^ ^^^  ^^^^ ^ ^^
2525      25 3 030  2303 0 25
6879      57 5 342  4312 0 86

Ravenslofty

Estimate of Logic utilization (ALMs needed)	2523 <= (13356/2) = 6678, assuming ALM logic plays nice <= 4892

Combinational ALUT usage for logic	2509 <= 13218 <= 9768
-- 7 input functions	49      <= 0 (not supported)
-- 6 input functions	420     <= 33   <= 2551
-- 5 input functions	375     <= 39   <= 2114
-- 4 input functions	497     <= 5668 <= 1221
-- <=3 input functions	1168  <= 7478 <= 3900

Dedicated logic registers	4231 <= 4891, assuming this means DFFs

Ravenslofty

generate
    genvar n;
    
    for (n = 0; n < S_COUNT; n = n + 1) begin // Quartus: this block requires a name
        assign request[n] = s_udp_hdr_valid[n] && !grant[n];
        assign acknowledge[n] = grant[n] && s_udp_payload_axis_tvalid[n] && s_udp_payload_axis_tready[n] && s_udp_payload_axis_tlast[n];
    end
endgenerate

Ravenslofty

read_verilog ~/CPU/benchmarks/cordic_10_16.v
prep -flatten
design -stash gold

read_verilog ~/CPU/benchmarks/cordic_10_16.v
prep -flatten
synth -auto-top -lut 4 -run :fine
techmap
abc -luts 1,1,1,1,3,6 -dress
design -stash gate

Ravenslofty

read_verilog ~/CPU/benchmarks/counter.v
read_verilog ~/CPU/benchmarks/counter_tb.v
prep -flatten
design -stash gold

read_verilog ~/CPU/benchmarks/counter.v
read_verilog ~/CPU/benchmarks/counter_tb.v
prep -flatten
script synth_cyclone.ys
design -stash gate

Ravenslofty

read_verilog ~/yosys/tests/lut/map_and.v
design -stash gold

read_verilog ~/yosys/tests/lut/map_and.v
synth -auto-top -lut 4 -run :fine
opt -full
read_verilog -lib cells_sim.v
techmap -map alu_map.v
techmap
techmap -map dff_map.v

Ravenslofty

synth -lut 6
read_verilog -lib cells_sim.v
techmap -map cells_map.v
stat -width

Ravenslofty

Rough Retargeting Yosys

Prerequisites

You'll want Yosys itself; I am using Yosys 0.8+531 (git commit d4f77d40).

Gather all the information you can about your target; the more, the better.

As an example, I'm going to use the publicly available [Cyclone V Device Handbook][handbook]. Intel have not released any documentation of the Cyclone V bitstream, and reverse engineering

Ravenslofty

Rough Retargeting Yosys

Prerequisites

You'll want Yosys itself; I am using Yosys 0.8+531 (git commit d4f77d40).

Gather all the information you can about your target; the more, the better.

As an example, I'm going to use the publicly available [Cyclone V Device Handbook][handbook]. Intel have not released any documentation of the Cyclone V bitstream, and reverse engineering