Skip to content

Instantly share code, notes, and snippets.

@ShigekiKarita
Created June 11, 2014 06:08
Show Gist options
  • Save ShigekiKarita/8e10421b3e27f0576ee2 to your computer and use it in GitHub Desktop.
Save ShigekiKarita/8e10421b3e27f0576ee2 to your computer and use it in GitHub Desktop.
How to test verilog circuit
/* HOW TO USE
iverilog -o circuit circuit.v
vvp circuit
gtkwave circuit.vcd
*/
module CIRCUIT (x, clk, z) ;
input x, clk;
output z;
reg z, q1, q2, q3;
initial begin
q1 = 1;
q2 = 0;
q3 = 1;
z = 1;
end
always @(posedge clk)
begin
q1 <= ~x;
q2 <= ~q1;
q3 <= ~q2;
z <= ~(x & q1 & q2 & q3);
end
endmodule // CIRCUIT
module TEST(circuit_out, circuit_in, clk);
input circuit_out;
output circuit_in, clk;
reg circuit_in, clk;
//Run the test once
initial
begin
clk = 0;
//Dump results of the simulation
$dumpfile("circuit.vcd");
$dumpvars;
//Generate circuit_input signal
circuit_in = 0;
#1 circuit_in = 1;
#4 circuit_in = 0;
#4 circuit_in = 1;
#4 circuit_in = 0;
#4 circuit_in = 1;
#4 circuit_in = 1;
#4 circuit_in = 0;
#4 circuit_in = 0;
#4 circuit_in = 1;
#4 circuit_in = 0;
#4 circuit_in = 1;
#8 $finish;
end
//Generate periodic clock signal
always
begin
#2 clk=!clk;
end
endmodule
module TEST_CIRCUIT;
wire in, clk, out;
CIRCUIT in_circuit(in, clk, out);
TEST in_out(out, in, clk);
endmodule // TEST_CIRCUIT
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment