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Siddhant/2bit AND.cir

Created February 9, 2015 06:42
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wrong plots
Raw
2bit AND.cir
.title AND gate simulation
A1 [1 2] 3 and
.model and d_and(rise_delay=0.1ps fall_delay=0.2ps)
* now test it
Asource [1 2] d_source_model
.model d_source_model d_source(input_file="2bit_input_for_and") ;note that only lowercase file names are allowed
.tran 1ns 60ns
* ngspice needs at least one "regular" circuit node while this code has only "xspice" nodes.
* To work around this issue we add a dummy resistor:
Runused Nunused 0 1k
Raw
2bit input for and
* t n n
* i o o
* m d d
* e e e
* 1 2
0ns Uu Uu
1ns 0s 0s
10ns 0s 1s
20ns 0s 0s
30ns 1s 1s
40ns 0s 1s
50ns 0s 0s
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