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Siddhant/2bit AND.cir

Created February 5, 2015 12:20
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[ngspice] 2bit AND simulation
Raw
2bit AND.cir
.title AND gate simulation
A1 [1 2] 3 and
.model and d_and(rise_delay=0.1ps fall_delay=0.2ps)
* now test it
Asource [1 2] d_source_model
.model d_source_model d_source(input_file="2bit_input_for_AND")
.tran 1ns 50ns
Raw
2bit_input_for_AND
0ns Uu Uu
1ns 0s 0s
10ns 0s 1s
20ns 1s 0s
30ns 1s 1s
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