bus.py

from nmigen import *

class Bus(Elaboratable):
	def __init__(self):
		self.nrst = Signal()
		self.stb_reset = Signal()

	def elaborate(self, platform):
		m = Module()

		last_nrst = Signal(4)
		m.d.sync += last_nrst.eq(Cat(self.nrst, last_nrst[0:3]))

		with m.FSM() as fsm:
			with m.State("bus_reset"):
				m.d.sync += self.stb_reset.eq(1)

				with m.If((last_nrst[1] == 1)): # wait for nrst deasserted
					m.next = "wait_forever"
			with m.State("wait_forever"): # waiting for !cs low
				m.d.sync += self.stb_reset.eq(0)
		return m

cart.py

from nmigen import *
from bus import Bus

class DSCart(Elaboratable):
	def __init__(self):
		self.dbg = Signal(4)
		self.bus = Bus()

	def elaborate(self, platform):
		m = Module()
		m.submodules += self.bus

		with m.FSM() as fsm:
			with m.State("reset"):
				m.d.sync += self.dbg.eq(1)

				if m.If(~self.bus.stb_reset):
					m.next = "do_cmd"
			
			with m.State("do_cmd"):
				m.d.sync += self.dbg.eq(2)

				if m.If(self.bus.stb_reset):
					m.d.sync += self.dbg.eq(0xa)
					m.next = "reset"
		return m

main.py

#!/usr/bin/env python3

from nmigen import *
from cart import DSCart

if __name__ == "__main__":
    cart = DSCart()
    
    ports = [
    ]

    import argparse

    parser = argparse.ArgumentParser()
    p_action = parser.add_subparsers(dest="action")
    p_action.add_parser("simulate")
    p_action.add_parser("generate")

    args = parser.parse_args()
    if args.action == "simulate":
        from nmigen.back import pysim

        sim = pysim.Simulator(cart)
        with sim.write_vcd(vcd_file=open("cart.vcd", "w"),
                gtkw_file=open("cart.gtkw", "w"),
                traces=ports):
            sim.add_clock(1e-6)

            def ds_proc():
                yield cart.bus.nrst.eq(0)
                for i in range(0,2):
                    yield
                    yield

                yield cart.bus.nrst.eq(1)

                for i in range(0,10):
                    yield
                    yield

            sim.add_sync_process(ds_proc)

            sim.run()
   
    if args.action == "generate":
        from nmigen.back import verilog
        from nmigen.back import rtlil

        open("out.v","w").write(verilog.convert(cart, ports=ports))
        open("out.rtlil", "w").write(rtlil.convert(cart, ports=ports))

out.rtlil

attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.U$$0"
module \U$$0
  attribute \src "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py:540"
  wire width 1 input 0 \rst
  attribute \src "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py:540"
  wire width 1 input 1 \clk
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:11"
  wire width 4 \last_nrst
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:11"
  wire width 4 \last_nrst$next
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:5"
  wire width 1 \nrst
  process $group_0
    assign \last_nrst$next \last_nrst
    assign \last_nrst$next { \last_nrst [2:0] \nrst }
    attribute \src "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:528"
    switch \rst
      case 1'1
        assign \last_nrst$next 4'0000
    end
    sync init
      update \last_nrst 4'0000
    sync posedge \clk
      update \last_nrst \last_nrst$next
  end
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:6"
  wire width 1 \stb_reset
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:6"
  wire width 1 \stb_reset$next
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:14"
  wire width 1 \fsm_state
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:14"
  wire width 1 \fsm_state$next
  process $group_1
    assign \stb_reset$next \stb_reset
    attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:14"
    switch \fsm_state
      attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:15"
      attribute \nmigen.decoding "bus_reset/0"
      case 1'0
        assign \stb_reset$next 1'1
      attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:20"
      attribute \nmigen.decoding "wait_forever/1"
      case 1'1
        assign \stb_reset$next 1'0
    end
    attribute \src "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:528"
    switch \rst
      case 1'1
        assign \stb_reset$next 1'0
    end
    sync init
      update \stb_reset 1'0
    sync posedge \clk
      update \stb_reset \stb_reset$next
  end
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:18"
  wire width 1 $1
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:18"
  cell $eq $2
    parameter \A_SIGNED 1'0
    parameter \A_WIDTH 1'1
    parameter \B_SIGNED 1'0
    parameter \B_WIDTH 1'1
    parameter \Y_WIDTH 1'1
    connect \A \last_nrst [1]
    connect \B 1'1
    connect \Y $1
  end
  process $group_2
    assign \fsm_state$next \fsm_state
    attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:14"
    switch \fsm_state
      attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:15"
      attribute \nmigen.decoding "bus_reset/0"
      case 1'0
        attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:18"
        switch { $1 }
          attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:18"
          case 1'1
            assign \fsm_state$next 1'1
        end
      attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:20"
      attribute \nmigen.decoding "wait_forever/1"
      case 1'1
    end
    attribute \src "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:528"
    switch \rst
      case 1'1
        assign \fsm_state$next 1'0
    end
    sync init
      update \fsm_state 1'0
    sync posedge \clk
      update \fsm_state \fsm_state$next
  end
  connect \nrst 1'0
end
attribute \generator "nMigen"
attribute \top 1
attribute \nmigen.hierarchy "top"
module \top
  attribute \src "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py:540"
  wire width 1 input 0 \clk
  attribute \src "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py:540"
  wire width 1 input 1 \rst
  cell \U$$0 \U$$0
    connect \rst \rst
    connect \clk \clk
  end
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:6"
  wire width 4 \dbg
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:6"
  wire width 4 \dbg$next
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:13"
  wire width 1 \fsm_state
  attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:13"
  wire width 1 \fsm_state$next
  process $group_0
    assign \dbg$next \dbg
    attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:13"
    switch \fsm_state
      attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:14"
      attribute \nmigen.decoding "reset/0"
      case 1'0
        assign \dbg$next 4'0001
      attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:20"
      attribute \nmigen.decoding "do_cmd/1"
      case 1'1
        assign \dbg$next 4'0010
        assign \dbg$next 4'1010
    end
    attribute \src "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:528"
    switch \rst
      case 1'1
        assign \dbg$next 4'0000
    end
    sync init
      update \dbg 4'0000
    sync posedge \clk
      update \dbg \dbg$next
  end
  process $group_1
    assign \fsm_state$next \fsm_state
    attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:13"
    switch \fsm_state
      attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:14"
      attribute \nmigen.decoding "reset/0"
      case 1'0
        assign \fsm_state$next 1'1
      attribute \src "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:20"
      attribute \nmigen.decoding "do_cmd/1"
      case 1'1
        assign \fsm_state$next 1'0
    end
    attribute \src "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:528"
    switch \rst
      case 1'1
        assign \fsm_state$next 1'0
    end
    sync init
      update \fsm_state 1'0
    sync posedge \clk
      update \fsm_state \fsm_state$next
  end
end

out.v

/* Generated by Yosys 0.9+932 (git sha1 aa1adb0f, gcc 9.2.0 -march=x86-64 -mtune=generic -O2 -fstack-protector-strong -fno-plt -fPIC -Os) */

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "top.U$$0" *)
module \U$$0 (clk, rst);
  (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:18" *)
  wire \$1 ;
  (* src = "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py:540" *)
  input clk;
  (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:14" *)
  reg fsm_state = 1'h0;
  (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:14" *)
  reg \fsm_state$next ;
  (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:11" *)
  reg [3:0] last_nrst = 4'h0;
  (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:11" *)
  reg [3:0] \last_nrst$next ;
  (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:5" *)
  wire nrst;
  (* src = "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py:540" *)
  input rst;
  (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:6" *)
  reg stb_reset = 1'h0;
  (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:6" *)
  reg \stb_reset$next ;
  assign \$1  = last_nrst[1] == (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:18" *) 1'h1;
  always @(posedge clk)
      fsm_state <= \fsm_state$next ;
  always @(posedge clk)
      stb_reset <= \stb_reset$next ;
  always @(posedge clk)
      last_nrst <= \last_nrst$next ;
  always @* begin
    \last_nrst$next  = { last_nrst[2:0], nrst };
    (* src = "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:528" *)
    casez (rst)
      1'h1:
          \last_nrst$next  = 4'h0;
    endcase
  end
  always @* begin
    \stb_reset$next  = stb_reset;
    (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:14" *)
    casez (fsm_state)
      /* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:15" */
      /* \nmigen.decoding  = "bus_reset/0" */
      1'h0:
          \stb_reset$next  = 1'h1;
      /* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:20" */
      /* \nmigen.decoding  = "wait_forever/1" */
      1'h1:
          \stb_reset$next  = 1'h0;
    endcase
    (* src = "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:528" *)
    casez (rst)
      1'h1:
          \stb_reset$next  = 1'h0;
    endcase
  end
  always @* begin
    \fsm_state$next  = fsm_state;
    (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:14" *)
    casez (fsm_state)
      /* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:15" */
      /* \nmigen.decoding  = "bus_reset/0" */
      1'h0:
          (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:18" *)
          casez (\$1 )
            /* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/bus.py:18" */
            1'h1:
                \fsm_state$next  = 1'h1;
          endcase
    endcase
    (* src = "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:528" *)
    casez (rst)
      1'h1:
          \fsm_state$next  = 1'h0;
    endcase
  end
  assign nrst = 1'h0;
endmodule

(* generator = "nMigen" *)
(* top =  1  *)
(* \nmigen.hierarchy  = "top" *)
module top(rst, clk);
  (* src = "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py:540" *)
  input clk;
  (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:6" *)
  reg [3:0] dbg = 4'h0;
  (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:6" *)
  reg [3:0] \dbg$next ;
  (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:13" *)
  reg fsm_state = 1'h0;
  (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:13" *)
  reg \fsm_state$next ;
  (* src = "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py:540" *)
  input rst;
  always @(posedge clk)
      fsm_state <= \fsm_state$next ;
  always @(posedge clk)
      dbg <= \dbg$next ;
  \U$$0  \U$$0  (
    .clk(clk),
    .rst(rst)
  );
  always @* begin
    \dbg$next  = dbg;
    (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:13" *)
    casez (fsm_state)
      /* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:14" */
      /* \nmigen.decoding  = "reset/0" */
      1'h0:
          \dbg$next  = 4'h1;
      /* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:20" */
      /* \nmigen.decoding  = "do_cmd/1" */
      1'h1:
          \dbg$next  = 4'ha;
    endcase
    (* src = "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:528" *)
    casez (rst)
      1'h1:
          \dbg$next  = 4'h0;
    endcase
  end
  always @* begin
    \fsm_state$next  = fsm_state;
    (* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:13" *)
    casez (fsm_state)
      /* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:14" */
      /* \nmigen.decoding  = "reset/0" */
      1'h0:
          \fsm_state$next  = 1'h1;
      /* src = "/home/stary/develop/FPGA/dscart-migen/a-tale-of-2-fsms/cart.py:20" */
      /* \nmigen.decoding  = "do_cmd/1" */
      1'h1:
          \fsm_state$next  = 1'h0;
    endcase
    (* src = "/home/stary/.local/lib/python3.8/site-packages/nmigen/hdl/xfrm.py:528" *)
    casez (rst)
      1'h1:
          \fsm_state$next  = 1'h0;
    endcase
  end
endmodule