samples_from_file.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY samples_from_file IS
	
	GENERIC (
		filename    : string;		-- Name of the input file
		binary_mode : boolean := false	-- set to 'true' if the file
						-- contains the samples bit by
						-- bit. if the file contains the
						-- samples as bytes, set to
						-- false (default)
		);

	PORT (
		o_samples : OUT std_logic;  -- sample output
		i_clk	  : IN	std_logic);

END ENTITY samples_from_file;

ARCHITECTURE Arch OF samples_from_file IS
	TYPE t_int_file IS FILE OF character;
	SIGNAL bitnumber : unsigned (2 DOWNTO 0) := to_unsigned(0, 3);

BEGIN  -- ARCHITECTURE Arch
	--FILE_OPEN(f, filename, read_mode);

-- purpose: reads one value per clock tick and outputs it to 'o_samples'
-- type	  : sequential
-- inputs : i_clk
-- outputs: o_samples
	PROCESS IS
		FILE f		: t_int_file OPEN read_mode IS filename;
		VARIABLE byte	: character;
		VARIABLE int8	: unsigned(7 DOWNTO 0);
		VARIABLE output : std_logic;
	BEGIN  -- PROCESS
		WAIT UNTIL rising_edge(i_clk);


		IF binary_mode THEN
			IF bitnumber = 0 AND NOT endfile(f) THEN
				read(f, byte);
				int8 := to_unsigned(character'pos(byte), 8);
			END IF;
			output := std_logic(int8(to_integer(bitnumber)));
		ELSE
			IF NOT endfile(f) THEN
				read(f, byte);
			END IF;
			IF character'pos(byte) > 127 THEN
				output := '0';
			ELSE
				output := '1';
			END IF;
		END IF;

		bitnumber <= bitnumber + 1;
		o_samples <= output;
		
	END PROCESS;

END ARCHITECTURE Arch;

snippet1.vhd

-- This is a snippet how I wrote some simulation data to a file. This is much faster than using the wave output option of the ghdl simulation:

-- pragma translate_off
	--! Writes simulation data to a file. This is only used in simulation, not in synthesis.
	fileout : PROCESS
		FILE fIprompt : t_int_file OPEN write_mode IS "dump_I_Prompt_ch" & integer'image(channel_num);
		FILE fQprompt : t_int_file OPEN write_mode IS "dump_Q_Prompt_ch" & integer'image(channel_num);
		FILE fcarrfcw : t_int_file OPEN write_mode IS "dump_carrfcw_ch" & integer'image(channel_num);
		FILE fcodefcw : t_int_file OPEN write_mode IS "dump_codefcw_ch" & integer'image(channel_num);
	BEGIN
		WAIT UNTIL rising_edge(nco_to_ca_codegen.Ena_clk_div1023);
		write(fIprompt, to_integer(i_and_d_out.I_Prompt));
		write(fQprompt, to_integer(i_and_d_out.Q_Prompt));
		write(fcarrfcw, to_integer(r.carrier_FCW));
		write(fcodefcw, to_integer(r.code_FCW));
	END PROCESS;
	-- pragma translate_on

snippet2.vhd

-- This is another snippet how I wrote some debug messages to stdout during simulation:

-- pragma translate_off
	--! Prints a message to the console when the softcore CPU reads or writes one of the registers.
	--! This is only used for simulation, not in synthesis.
	PROCEDURE register_access_report(dmem_in : IN dmem_out_type) IS
		VARIABLE message       : line;
		VARIABLE message_level : severity_level := note;
	BEGIN
		IF (i_dmem.ena_o = '1') THEN
			IF (i_dmem.we_o = '1') THEN
				write(message, string'("Ch" & integer'image(channel_num) & " Write: "));
			ELSE
				write(message, string'("Ch" & integer'image(channel_num) & " Read: "));
			END IF;

			CASE dmem_in.adr_o(7 DOWNTO 0) IS
				WHEN addr_I_Early     => write(message, string'("I_Early"));
				WHEN addr_Q_Early     => write(message, string'("Q_Early"));
				WHEN addr_I_Prompt    => write(message, string'("I_Prompt"));
				WHEN addr_Q_Prompt    => write(message, string'("Q_Prompt"));
				WHEN addr_I_Late      => write(message, string'("I_Late"));
				WHEN addr_Q_Late      => write(message, string'("Q_Late"));
				WHEN addr_code_fcw    => write(message, string'("code_fcw"));
				WHEN addr_carrier_fcw => write(message, string'("carrier_fcw"));
				WHEN addr_PRN	      => write(message, string'("PRN"));
				WHEN addr_codephase   => write(message, string'("codephase"));
				WHEN addr_flags	      => write(message, string'("flags"));
				WHEN OTHERS =>
					write(message, string'("invalid register!"));
					message_level := error;
			END CASE;
			REPORT message.ALL SEVERITY message_level;
		END IF;
	END PROCEDURE;
-- pragma translate_on

testbench.vhd

-- This is not the complete testbench, but only an example in how to use the samples_from_file entity

samples_from_file_1 : ENTITY work.samples_from_file
		GENERIC MAP (
			filename    => "./infile",
			binary_mode => false)
		PORT MAP (
			o_samples => i_ADC.I(0),
			i_clk	  => sysclk);