Makefile C template

Makefile

SHELL = /bin/bash
CC = gcc
OBJECT_FLAG = -c
CFLAGS = -O2 -pedantic -std=c99 -Wall -Wextra -Wshadow -W
LIBS = -lexample
OBJS = example.o
OUT = example
SUPPRESS_OUTPUT = > /dev/null 2>&1

all:$(OBJS)
	@for OBJ in $(OBJS); do echo -e "\tLD $$OBJ"; done
	@$(CC) $(OBJS) $(LIBS) -o $(OUT) && echo -e '\tELF $(OUT)'

$(OBJS): %.o: %.c
	@echo -e '\tCC $<'
	@$(CC) $(CFLAGS) $< $(OBJECT_FLAG) -o $@

clean:
	@for OBJ in $(OBJS); do echo -e "\tRM $$OBJ"; done
	@rm $(OBJS) $(SUPPRESS_OUTPUT) || echo -e "\tRM no object files"

cleanall: clean
	@echo -e "\tRM $(OUT)"
	@rm $(OUT) $(SUPPRESS_OUTPUT) || echo -e "\tRM no executable files"

.PHONY: all, clean, cleanall