.cpp

STREX_INST : {
    if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
        generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
        unsigned int write_addr = cpu->Reg[inst_cream->Rn];

        if (cpu->IsExclusiveMemoryAccess(write_addr)) {
            cpu->UnsetExclusiveMemoryAddress();
            cpu->WriteMemory32(write_addr, RM);
            RD = 0;
        } else {
            // Failed to write due to mutex access
            RD = 1;
        }
    }
    cpu->Reg[15] += cpu->GetInstructionSize();
    INC_PC(sizeof(generic_arm_inst));
    FETCH_INST;
    GOTO_NEXT_INST;
}
LDREX_INST : {
    if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
        generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
        unsigned int read_addr = RN;

        cpu->SetExclusiveMemoryAddress(read_addr);

        RD = cpu->ReadMemory32(read_addr);
    }
    cpu->Reg[15] += cpu->GetInstructionSize();
    INC_PC(sizeof(generic_arm_inst));
    FETCH_INST;
    GOTO_NEXT_INST;
}
CLREX_INST : {
    cpu->UnsetExclusiveMemoryAddress();
    cpu->Reg[15] += cpu->GetInstructionSize();
    INC_PC(sizeof(clrex_inst));
    FETCH_INST;
    GOTO_NEXT_INST;
}

armstate.cpp

static u32 exclusive_addresses[4] = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF};

bool ARMul_State::IsExclusiveMemoryAccess(u32 address) const {
    if (!exclusive_state) {
        return false;
    }

    const auto tag = address & RESERVATION_GRANULE_MASK;

    if (exclusive_addresses[core_id] != tag) {
        return false;
    }

    for (u32 i = 0; i < 4; ++i) {
        if (exclusive_addresses[i] == tag) {
            exclusive_addresses[i] = 0xFFFFFFFF;
        }
    }

    return true;
}

void ARMul_State::SetExclusiveMemoryAddress(u32 address) {
    const auto tag = address & RESERVATION_GRANULE_MASK;
    exclusive_addresses[core_id] = tag;
    exclusive_state = true;
}

void ARMul_State::UnsetExclusiveMemoryAddress() {
    exclusive_state = false;
}