Nihstro super-speedup

gistfile1.diff

diff --git a/include/nihstro/shader_bytecode.h b/include/nihstro/shader_bytecode.h
index 4b609eb..ff3217c 100644
--- a/include/nihstro/shader_bytecode.h
+++ b/include/nihstro/shader_bytecode.h
@@ -380,8 +380,8 @@ struct OpCode {
     }
 
     const Info& GetInfo() const {
-        static const OpCode::Info unknown_instruction = { OpCode::Type::Unknown, 0, "UNK" };
-        static const OpCode::Info dummy = { OpCode::Type::Unknown, 0, "DMY" };
+        #define unknown_instruction { OpCode::Type::Unknown, 0, "UNK" }
+        #define dummy { OpCode::Type::Unknown, 0, "DMY" }
         static const OpCode::Info info_table[] =  {
             { OpCode::Type::Arithmetic, OpCode::Info::TwoArguments, "add" },
             { OpCode::Type::Arithmetic, OpCode::Info::TwoArguments, "dp3" },
@@ -430,18 +430,27 @@ struct OpCode {
             { OpCode::Type::Conditional, OpCode::Info::JMPC, "jmpc" },
             { OpCode::Type::Conditional, OpCode::Info::JMPU, "jmpu" },
             { OpCode::Type::Arithmetic, OpCode::Info::Compare, "cmp" },
-            dummy,
+            { OpCode::Type::Arithmetic, OpCode::Info::Compare, "cmp" },
+            { OpCode::Type::MultiplyAdd, OpCode::Info::SrcInversed, "madi" },
+            { OpCode::Type::MultiplyAdd, OpCode::Info::SrcInversed, "madi" },
+            { OpCode::Type::MultiplyAdd, OpCode::Info::SrcInversed, "madi" },
+            { OpCode::Type::MultiplyAdd, OpCode::Info::SrcInversed, "madi" },
             { OpCode::Type::MultiplyAdd, OpCode::Info::SrcInversed, "madi" },
-            dummy,
-            dummy,
-            dummy,
-            dummy,
-            dummy,
-            dummy,
-            dummy,
+            { OpCode::Type::MultiplyAdd, OpCode::Info::SrcInversed, "madi" },
+            { OpCode::Type::MultiplyAdd, OpCode::Info::SrcInversed, "madi" },
+            { OpCode::Type::MultiplyAdd, OpCode::Info::SrcInversed, "madi" },
+            { OpCode::Type::MultiplyAdd, 0, "mad" },
+            { OpCode::Type::MultiplyAdd, 0, "mad" },
+            { OpCode::Type::MultiplyAdd, 0, "mad" },
+            { OpCode::Type::MultiplyAdd, 0, "mad" },
+            { OpCode::Type::MultiplyAdd, 0, "mad" },
+            { OpCode::Type::MultiplyAdd, 0, "mad" },
+            { OpCode::Type::MultiplyAdd, 0, "mad" },
             { OpCode::Type::MultiplyAdd, 0, "mad" }
         };
-        return info_table[(int)EffectiveOpCode()];
+        #undef dummy
+        #undef unknown_instruction
+        return info_table[value];
     }
 
     operator Id() const {
@@ -613,7 +622,7 @@ union Instruction {
                 return src2i;
             }
         }
-        
+
         const SourceRegister GetSrc3(bool is_inverted) const {
             if (!is_inverted) {
                 return src3;
@@ -627,7 +636,7 @@ union Instruction {
         BitField<0x05, 0x5, SourceRegister> src3;
         BitField<0x0a, 0x7, SourceRegister> src2;
         BitField<0x11, 0x7, SourceRegister> src1;
-        
+
         BitField<0x05, 0x7, SourceRegister> src3i;
         BitField<0x0c, 0x5, SourceRegister> src2i;