Skip to content

Instantly share code, notes, and snippets.

@TG9541 TG9541/ws2812.fs
Last active Nov 12, 2019

Embed
What would you like to do?
An STM8 eForth WS2812 demo that takes some freedoms with the timing
\ A STM8 eForth WS2812 demo that takes some freedoms with the timing
\ 8 x WS2812B on PCB with 470µF capacitor at 5V supply
\ 3.3V MINDEV: PB4 with 1K pull-up to 5V works well
\res MCU: STM8S103
\res export PB_DDR PB_ODR PB_CR1
#require ]B!
#require ]CB
NVM
: WS2812 ( a1 a0 -- )
DO [
$1601 , \ LDW Y,(1,SP)
$90F6 , \ LD A,(Y)
$88 C, \ PUSH A
$A608 , \ LD A,#8
HERE \ 0$:
] [ 1 PB_ODR 4 ]B! [
$0901 , \ RLC (1,SP)
$9D C, \ NOP
$9D C, \ NOP
] [ PB_ODR 4 ]CB [
$9D C, \ NOP
$9D C, \ NOP
$9D C, \ NOP
$9D C, \ NOP
] [ 0 PB_ODR 4 ]B! [
$9D C, \ NOP
$4A C, \ DEC A
$4D C, \ TNZ A
$26 C, \ JRNE ...
HERE - 1- C, \ ... 0$
$84 C, \ POP A
]
LOOP ;
: init ( -- )
[ 0 PB_ODR 4 ]B!
[ 1 PB_DDR 4 ]B!
[ 1 PB_CR1 4 ]B! ;
RAM
\\ Example
8 3 * CONSTANT #mem
VARIABLE wsmem 22 ALLOT
: test ( n -- )
init
255 FOR
wsmem #mem i FILL
wsmem #mem + wsmem WS2812
DUP FOR ( wait ) NEXT
NEXT DROP ;
\ e.g. 10000 test
@TG9541

This comment has been minimized.

Copy link
Owner Author

TG9541 commented Dec 23, 2018

Here is some support for the timing hypothesis: https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/
The author basically states that:

  • T1H doesn't matter much ( > 0.55µs)
  • T0L and T1L should be > 0.2µs and <= 5µs

This means that bit-banging can be simplified

@TG9541

This comment has been minimized.

Copy link
Owner Author

TG9541 commented Dec 24, 2018

New findings by testing the claims above and comparing (failed) timing with refreshed signals at the WS2812B output:

  • the bit timing should be balanced and result in a cadence of no less than 0.9µs
  • bit high time will be reshaped to spec (0.35µs, 0.7µs)
  • bit low time and inter byte delay can be relaxed (0.3125 to 4.8µs)
  • bit low time 0.25µs to 5µs still works

The code above has a cadence of 1µs independent of high/low. The inter byte delay is 4.8 µs.
Tested with WS2812 (64 units) and WS2812B (8 units).
Power supply is critical: 64 units WS2812 fully lit (0xFFFFFF) draws about 3A.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
You can’t perform that action at this time.