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@TG9541 TG9541/INTRX

Last active Jun 14, 2020
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Buffered ?RX for STM8S Low Density
\ STM8 eForth buffered UART receive
\ the code assumes that the target CPU resource was loaded
\ e.g. \res MCU: STM8S103
\ and the RX buffer length was defined as a constant
\ e.g. 8 CONSTANT RBLEN
\ more in the example at the end of the file
\res export INT_UARTRX UART_DR UART_CR2
#require WIPE
#require :NVM
#require ALIAS
#require ]B!
#require '?KEY
5 CONSTANT #RIEN
NVM
VARIABLE rxbuf RBLEN 2- ALLOT
VARIABLE rxp \ UART RX ISR buffer write pointer
VARIABLE rrp \ ?RXB buffer read pointer
\ increment buffer pointer w/ wrap around
:NVM ( a -- )
DUP @ 1+ ( a ab1 ) [ rxbuf RBLEN + 1- ] LITERAL OVER < IF
( a n1 ) DROP rxbuf ( a n0 )
THEN
( a n ) SWAP !
;RAM ALIAS rpi
\ RX ISR handler
:NVM
SAVEC
UART1_DR C@ rxp @ C! rxp rpi
IRET
[ OVERT INT_UARTRX !
\ like ?RX only buffered
: ?RXB ( -- c T | F )
rrp @ rxp @ = IF
0
ELSE
rrp @ C@ -1 rrp rpi
THEN
;
\ Interrupt RX UART handler
: INTRX ( -- )
[ ' ?RXB ] LITERAL '?KEY !
rxbuf DUP rxp ! rrp !
[ 1 UART1_CR2 #RIEN ]B!
;
WIPE RAM
\\ Example
\ select the (STM8S) controller first (alt. STM8S105. STM8S207)
\res MCU: STM8S103
\ define the UART buffer length
8 CONSTANT RBLEN
\ then load the controller independent code
#require INTRX
\ put it to work
#require WIPE
#require :NVM
#require OSCFREQ
#require UART_DIV
#require UARTBRR
NVM
'BOOT ( xt )
:NVM
INTRX
( xt ) LITERAL EXECUTE
;NVM 'BOOT !
\ calculate UART_DIV settings for 38400 baud at the CPU clock rate
3840 OSCFREQ UART_DIV UARTBRR !
WIPE RAM
\ make it survive a RESET command
#require PERSIST
PERSIST
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TG9541 commented May 23, 2020

\ Test with MINDEV:
\res MCU: STM8S103
8 CONSTANT RBLEN
#require INTRX

INTRX
\ a simple delay loop in a background task
: test 0 OUT! 0 @ 1+ for next  1 OUT! ;
' test BG !
2850 0 !   \ the background task now runs for 4.65 ms out of 5.00 ms:
\ this slows down the console but it won't block it.

image

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TG9541 commented Jun 9, 2020

There is also a HaD log entry, here.

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