root.vhdl

-------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/05/2017 08:40:01 AM
-- Design Name:
-- Module Name: root - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity root is
    generic (DIGIT_NUM: integer := 4);
    port(
            a: in STD_LOGIC_VECTOR(DIGIT_NUM - 1 downto 0);
            n: in integer;
            clk: in STD_LOGIC;
            rooted : out STD_LOGIC_VECTOR(DIGIT_NUM - 1 downto 0);
            ready_out: out STD_LOGIC
        );
end root;

architecture Behavioral of root is
    signal ready: STD_LOGIC := '0';
    signal i: integer := 0;
    signal a_old: STD_LOGIC_VECTOR(DIGIT_NUM - 1 downto 0);
    signal n_old: integer;
begin

    ready_out <= ready;

    process(clk)
        variable temp: STD_LOGIC_VECTOR(DIGIT_NUM - 1 downto 0) := (others => '0');
        variable x_n_2: STD_LOGIC_VECTOR(DIGIT_NUM - 1 downto 0) := (others => '1');
        variable x_n_1: STD_LOGIC_VECTOR(DIGIT_NUM - 1 downto 0) := (others => '1');
        variable x_n: STD_LOGIC_VECTOR(DIGIT_NUM - 1 downto 0) := (others => '0');
        variable x_n_1_image: integer;

    begin
        if(x_n = x_n_1 or x_n = x_n_2) then
            i <= 0;
            ready <= '1';
            rooted <= x_n;
        else
            ready <= '0';

            if(i = 0) then
                x_n_1 := std_logic_vector(to_unsigned(1, DIGIT_NUM));
            else
                temp := x_n_1;
                x_n_1 := x_n;
                x_n_1_image := to_integer(unsigned(x_n_1, DIGIT_NUM));
                report integer'image();
                x_n := std_logic_vector(to_unsigned(to_integer(unsigned(temp)) + 1, DIGIT_NUM));
            end if;
        end if;

        if(a_old /= a or n_old /= n) then
            i <= 0;
            ready <= '0';
        end if;

        a_old <= a;
        n_old <= n;

    end process;
end Behavioral;