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Created November 27, 2022 17:47
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static.c of P8Z77-V LX2 with https://review.coreboot.org/56912
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static.c
#include <boot/coreboot_tables.h>
#include <device/device.h>
#include <device/pci.h>
#include <fw_config.h>
#include <static.h>
#include "cpu/intel/model_206ax/chip.h"
#include "northbridge/intel/sandybridge/chip.h"
#include "southbridge/intel/bd82x6x/chip.h"
#if !DEVTREE_EARLY
__attribute__((weak)) struct chip_operations mainboard_ops = {};
__attribute__((weak)) struct chip_operations cpu_intel_model_206ax_ops = {};
extern struct chip_operations northbridge_intel_sandybridge_ops;
extern struct chip_operations southbridge_intel_bd82x6x_ops;
extern struct chip_operations superio_nuvoton_nct6779d_ops;
#endif
#define STORAGE static __maybe_unused DEVTREE_CONST
/* pass 0 */
STORAGE struct bus dev_root_links[];
STORAGE struct device _dev_0;
STORAGE struct bus _dev_0_links[];
STORAGE struct device _dev_1;
STORAGE struct bus _dev_1_links[];
STORAGE struct device _dev_2;
STORAGE struct device _dev_3;
STORAGE struct device _dev_hb;
STORAGE struct device _dev_peg10;
STORAGE struct device _dev_peg11;
STORAGE struct device _dev_peg12;
STORAGE struct device _dev_igd;
STORAGE struct device _dev_dev4;
STORAGE struct device _dev_peg60;
STORAGE struct device _dev_xhci;
STORAGE struct device _dev_mei1;
STORAGE struct device _dev_mei2;
STORAGE struct device _dev_me_ide_r;
STORAGE struct device _dev_me_kt;
STORAGE struct device _dev_gbe;
STORAGE struct device _dev_ehci2;
STORAGE struct device _dev_hda;
STORAGE struct device _dev_rp1;
STORAGE struct device _dev_rp2;
STORAGE struct device _dev_rp3;
STORAGE struct device _dev_rp4;
STORAGE struct device _dev_rp5;
STORAGE struct device _dev_rp6;
STORAGE struct device _dev_rp7;
STORAGE struct device _dev_rp8;
STORAGE struct device _dev_ehci1;
STORAGE struct device _dev_pci_b;
STORAGE struct device _dev_lpc;
STORAGE struct bus _dev_lpc_links[];
STORAGE struct device _dev_sata1;
STORAGE struct device _dev_smbus;
STORAGE struct device _dev_sata2;
STORAGE struct device _dev_thermal;
STORAGE struct device _dev_4;
STORAGE struct device _dev_5;
STORAGE struct resource _dev_5_res[];
STORAGE struct device _dev_6;
STORAGE struct device _dev_7;
STORAGE struct resource _dev_7_res[];
STORAGE struct device _dev_8;
STORAGE struct device _dev_9;
STORAGE struct device _dev_10;
STORAGE struct device _dev_11;
STORAGE struct device _dev_12;
STORAGE struct device _dev_13;
STORAGE struct device _dev_14;
STORAGE struct resource _dev_14_res[];
STORAGE struct device _dev_15;
STORAGE struct device _dev_16;
STORAGE struct device _dev_17;
STORAGE struct device _dev_18;
STORAGE struct device _dev_19;
STORAGE struct device _dev_20;
STORAGE struct device _dev_21;
STORAGE struct resource _dev_21_res[];
STORAGE struct device _dev_22;
STORAGE struct device _dev_23;
STORAGE struct device _dev_24;
STORAGE struct device _dev_25;
STORAGE struct device _dev_26;
DEVTREE_CONST struct device * DEVTREE_CONST last_dev = &_dev_26;
/* chip configs */
STORAGE struct cpu_intel_model_206ax_config cpu_intel_model_206ax_info_1 = {
.acpi_c1 = 1,
.acpi_c2 = 3,
.acpi_c3 = 5,
};
STORAGE struct northbridge_intel_sandybridge_config northbridge_intel_sandybridge_info_1 = {};
STORAGE struct southbridge_intel_bd82x6x_config southbridge_intel_bd82x6x_info_1 = {
.gen1_dec = 0x000c0291,
.sata_interface_speed_support = 0x3,
.sata_port_map = 0x3f,
.spi_lvscc = 0x2005,
.spi_uvscc = 0x2005,
.superspeed_capable_ports = 0x0000000f,
.xhci_overcurrent_mapping = 0x00000c03,
.xhci_switchable_ports = 0x0000000f,
};
/* pass 1 */
DEVTREE_CONST struct device dev_root = {
#if !DEVTREE_EARLY
.ops = &default_dev_ops_root,
#endif
.bus = &dev_root_links[0],
.path = { .type = DEVICE_PATH_ROOT },
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.link_list = &dev_root_links[0],
.sibling = NULL,
#if !DEVTREE_EARLY
.chip_ops = &mainboard_ops,
.name = mainboard_name,
#endif
.next=&_dev_0,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct bus dev_root_links[] = {
[0] = {
.link_num = 0,
.dev = &dev_root,
.children = &_dev_0,
.next = NULL,
},
};
STORAGE struct device _dev_0 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &dev_root_links[0],
.path = {.type=DEVICE_PATH_CPU_CLUSTER,{.cpu_cluster={ .cluster = 0x0 }}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.link_list = &_dev_0_links[0],
.sibling = &_dev_1,
#if !DEVTREE_EARLY
.chip_ops = &northbridge_intel_sandybridge_ops,
#endif
.chip_info = &northbridge_intel_sandybridge_info_1,
.next=&_dev_1,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct bus _dev_0_links[] = {
[0] = {
.link_num = 0,
.dev = &_dev_0,
.children = &_dev_2,
.next = NULL,
},
};
STORAGE struct device _dev_1 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &dev_root_links[0],
.path = {.type=DEVICE_PATH_DOMAIN,{.domain={ .domain = 0x0 }}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = &_dev_1_links[0],
.sibling = NULL,
#if !DEVTREE_EARLY
.chip_ops = &northbridge_intel_sandybridge_ops,
#endif
.chip_info = &northbridge_intel_sandybridge_info_1,
.next=&_dev_2,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct bus _dev_1_links[] = {
[0] = {
.link_num = 0,
.dev = &_dev_1,
.children = &_dev_hb,
.next = NULL,
},
};
STORAGE struct device _dev_2 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_0_links[0],
.path = {.type=DEVICE_PATH_APIC,{.apic={ .apic_id = 0x0 }}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.link_list = NULL,
.sibling = &_dev_3,
#if !DEVTREE_EARLY
.chip_ops = &cpu_intel_model_206ax_ops,
#endif
.chip_info = &cpu_intel_model_206ax_info_1,
.next=&_dev_3,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_3 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_0_links[0],
.path = {.type=DEVICE_PATH_APIC,{.apic={ .apic_id = 0xacac }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.link_list = NULL,
.sibling = NULL,
#if !DEVTREE_EARLY
.chip_ops = &cpu_intel_model_206ax_ops,
#endif
.chip_info = &cpu_intel_model_206ax_info_1,
.next=&_dev_hb,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_hb = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x0,0)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_peg10,
#if !DEVTREE_EARLY
.chip_ops = &northbridge_intel_sandybridge_ops,
#endif
.chip_info = &northbridge_intel_sandybridge_info_1,
.next=&_dev_peg10,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_peg10 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1,0)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_peg11,
#if !DEVTREE_EARLY
.chip_ops = &northbridge_intel_sandybridge_ops,
#endif
.chip_info = &northbridge_intel_sandybridge_info_1,
.next=&_dev_peg11,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_peg11 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1,1)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_peg12,
#if !DEVTREE_EARLY
.chip_ops = &northbridge_intel_sandybridge_ops,
#endif
.chip_info = &northbridge_intel_sandybridge_info_1,
.next=&_dev_peg12,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_peg12 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1,2)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_igd,
#if !DEVTREE_EARLY
.chip_ops = &northbridge_intel_sandybridge_ops,
#endif
.chip_info = &northbridge_intel_sandybridge_info_1,
.next=&_dev_igd,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_igd = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x2,0)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_dev4,
#if !DEVTREE_EARLY
.chip_ops = &northbridge_intel_sandybridge_ops,
#endif
.chip_info = &northbridge_intel_sandybridge_info_1,
.next=&_dev_dev4,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_dev4 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x4,0)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_peg60,
#if !DEVTREE_EARLY
.chip_ops = &northbridge_intel_sandybridge_ops,
#endif
.chip_info = &northbridge_intel_sandybridge_info_1,
.next=&_dev_peg60,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_peg60 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x6,0)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_xhci,
#if !DEVTREE_EARLY
.chip_ops = &northbridge_intel_sandybridge_ops,
#endif
.chip_info = &northbridge_intel_sandybridge_info_1,
.next=&_dev_xhci,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_xhci = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x14,0)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_mei1,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_mei1,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_mei1 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x16,0)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_mei2,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_mei2,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_mei2 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x16,1)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_me_ide_r,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_me_ide_r,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_me_ide_r = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x16,2)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_me_kt,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_me_kt,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_me_kt = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x16,3)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_gbe,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_gbe,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_gbe = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x19,0)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_ehci2,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_ehci2,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_ehci2 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1a,0)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_hda,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_hda,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_hda = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1b,0)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_rp1,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_rp1,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_rp1 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,0)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_rp2,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_rp2,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_rp2 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,1)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_rp3,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_rp3,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_rp3 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,2)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_rp4,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_rp4,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_rp4 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_rp5,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_rp5,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_rp5 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,4)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_rp6,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_rp6,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_rp6 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,5)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_rp7,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_rp7,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_rp7 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,6)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_rp8,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_rp8,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_rp8 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,7)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_ehci1,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_ehci1,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_ehci1 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1d,0)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_pci_b,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_pci_b,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_pci_b = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1e,0)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_lpc,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_lpc,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_lpc = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1f,0)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = &_dev_lpc_links[0],
.sibling = &_dev_sata1,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_sata1,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct bus _dev_lpc_links[] = {
[0] = {
.link_num = 0,
.dev = &_dev_lpc,
.children = &_dev_4,
.next = NULL,
},
};
STORAGE struct device _dev_sata1 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1f,2)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_smbus,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_smbus,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_smbus = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1f,3)}}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_sata2,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_sata2,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_sata2 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1f,5)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_thermal,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_thermal,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_thermal = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_1_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1f,6)}}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = NULL,
#if !DEVTREE_EARLY
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_1,
.next=&_dev_4,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_4 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x1 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_5,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_5,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_5 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x2 }}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.resource_list = &_dev_5_res[0],
.link_list = NULL,
.sibling = &_dev_6,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_6,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct resource _dev_5_res[] = {
{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x60, .base=0x3f8,.next=&_dev_5_res[1]},
{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IRQ, .index=0x70, .base=0x4,.next=NULL },
};
STORAGE struct device _dev_6 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x3 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_7,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_7,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_7 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x5 }}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.resource_list = &_dev_7_res[0],
.link_list = NULL,
.sibling = &_dev_8,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_8,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct resource _dev_7_res[] = {
{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x60, .base=0x60,.next=&_dev_7_res[1]},
{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x62, .base=0x64,.next=&_dev_7_res[2]},
{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IRQ, .index=0x70, .base=0x1,.next=&_dev_7_res[3]},
{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IRQ, .index=0x72, .base=0xc,.next=NULL },
};
STORAGE struct device _dev_8 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x6 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_9,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_9,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_9 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x7 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_10,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_10,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_10 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x8 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_11,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_11,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_11 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x108 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_12,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_12,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_12 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x9 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_13,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_13,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_13 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x109 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_14,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_14,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_14 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x209 }}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.resource_list = &_dev_14_res[0],
.link_list = NULL,
.sibling = &_dev_15,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_15,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct resource _dev_14_res[] = {
{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IRQ, .index=0xe0, .base=0xff,.next=NULL },
};
STORAGE struct device _dev_15 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x309 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_16,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_16,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_16 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x409 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_17,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_17,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_17 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x509 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_18,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_18,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_18 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x609 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_19,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_19,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_19 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x709 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_20,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_20,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_20 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0xa }}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_21,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_21,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_21 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0xb }}},
.enabled = 1,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.resource_list = &_dev_21_res[0],
.link_list = NULL,
.sibling = &_dev_22,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_22,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct resource _dev_21_res[] = {
{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x60, .base=0x290,.next=&_dev_21_res[1]},
{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x62, .base=0x0,.next=&_dev_21_res[2]},
{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IRQ, .index=0x70, .base=0x0,.next=NULL },
};
STORAGE struct device _dev_22 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0xd }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_23,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_23,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_23 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0xe }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_24,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_24,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_24 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0xf }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_25,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_25,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_25 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x14 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = &_dev_26,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
.next=&_dev_26,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
STORAGE struct device _dev_26 = {
#if !DEVTREE_EARLY
.ops = NULL,
#endif
.bus = &_dev_lpc_links[0],
.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x2e, .device = 0x16 }}},
.enabled = 0,
.hidden = 0,
.mandatory = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1043,
.subsystem_device = 0x84ca,
.link_list = NULL,
.sibling = NULL,
#if !DEVTREE_EARLY
.chip_ops = &superio_nuvoton_nct6779d_ops,
#endif
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
#endif
#endif
};
DEVTREE_CONST struct device *const __pci_0_00_0 = &_dev_hb;
DEVTREE_CONST void *const __pci_0_00_0_config = &northbridge_intel_sandybridge_info_1;
DEVTREE_CONST struct device *const _dev_hb_ptr = &_dev_hb;
DEVTREE_CONST struct device *const __pci_0_01_0 = &_dev_peg10;
DEVTREE_CONST void *const __pci_0_01_0_config = &northbridge_intel_sandybridge_info_1;
DEVTREE_CONST struct device *const _dev_peg10_ptr = &_dev_peg10;
DEVTREE_CONST struct device *const __pci_0_01_1 = &_dev_peg11;
DEVTREE_CONST void *const __pci_0_01_1_config = &northbridge_intel_sandybridge_info_1;
DEVTREE_CONST struct device *const _dev_peg11_ptr = &_dev_peg11;
DEVTREE_CONST struct device *const __pci_0_01_2 = &_dev_peg12;
DEVTREE_CONST void *const __pci_0_01_2_config = &northbridge_intel_sandybridge_info_1;
DEVTREE_CONST struct device *const _dev_peg12_ptr = &_dev_peg12;
DEVTREE_CONST struct device *const __pci_0_02_0 = &_dev_igd;
DEVTREE_CONST void *const __pci_0_02_0_config = &northbridge_intel_sandybridge_info_1;
DEVTREE_CONST struct device *const _dev_igd_ptr = &_dev_igd;
DEVTREE_CONST struct device *const __pci_0_04_0 = &_dev_dev4;
DEVTREE_CONST void *const __pci_0_04_0_config = &northbridge_intel_sandybridge_info_1;
DEVTREE_CONST struct device *const _dev_dev4_ptr = &_dev_dev4;
DEVTREE_CONST struct device *const __pci_0_06_0 = &_dev_peg60;
DEVTREE_CONST void *const __pci_0_06_0_config = &northbridge_intel_sandybridge_info_1;
DEVTREE_CONST struct device *const _dev_peg60_ptr = &_dev_peg60;
DEVTREE_CONST struct device *const __pci_0_14_0 = &_dev_xhci;
DEVTREE_CONST void *const __pci_0_14_0_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_xhci_ptr = &_dev_xhci;
DEVTREE_CONST struct device *const __pci_0_16_0 = &_dev_mei1;
DEVTREE_CONST void *const __pci_0_16_0_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_mei1_ptr = &_dev_mei1;
DEVTREE_CONST struct device *const __pci_0_16_1 = &_dev_mei2;
DEVTREE_CONST void *const __pci_0_16_1_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_mei2_ptr = &_dev_mei2;
DEVTREE_CONST struct device *const __pci_0_16_2 = &_dev_me_ide_r;
DEVTREE_CONST void *const __pci_0_16_2_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_me_ide_r_ptr = &_dev_me_ide_r;
DEVTREE_CONST struct device *const __pci_0_16_3 = &_dev_me_kt;
DEVTREE_CONST void *const __pci_0_16_3_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_me_kt_ptr = &_dev_me_kt;
DEVTREE_CONST struct device *const __pci_0_19_0 = &_dev_gbe;
DEVTREE_CONST void *const __pci_0_19_0_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_gbe_ptr = &_dev_gbe;
DEVTREE_CONST struct device *const __pci_0_1a_0 = &_dev_ehci2;
DEVTREE_CONST void *const __pci_0_1a_0_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_ehci2_ptr = &_dev_ehci2;
DEVTREE_CONST struct device *const __pci_0_1b_0 = &_dev_hda;
DEVTREE_CONST void *const __pci_0_1b_0_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_hda_ptr = &_dev_hda;
DEVTREE_CONST struct device *const __pci_0_1c_0 = &_dev_rp1;
DEVTREE_CONST void *const __pci_0_1c_0_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_rp1_ptr = &_dev_rp1;
DEVTREE_CONST struct device *const __pci_0_1c_1 = &_dev_rp2;
DEVTREE_CONST void *const __pci_0_1c_1_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_rp2_ptr = &_dev_rp2;
DEVTREE_CONST struct device *const __pci_0_1c_2 = &_dev_rp3;
DEVTREE_CONST void *const __pci_0_1c_2_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_rp3_ptr = &_dev_rp3;
DEVTREE_CONST struct device *const __pci_0_1c_3 = &_dev_rp4;
DEVTREE_CONST void *const __pci_0_1c_3_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_rp4_ptr = &_dev_rp4;
DEVTREE_CONST struct device *const __pci_0_1c_4 = &_dev_rp5;
DEVTREE_CONST void *const __pci_0_1c_4_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_rp5_ptr = &_dev_rp5;
DEVTREE_CONST struct device *const __pci_0_1c_5 = &_dev_rp6;
DEVTREE_CONST void *const __pci_0_1c_5_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_rp6_ptr = &_dev_rp6;
DEVTREE_CONST struct device *const __pci_0_1c_6 = &_dev_rp7;
DEVTREE_CONST void *const __pci_0_1c_6_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_rp7_ptr = &_dev_rp7;
DEVTREE_CONST struct device *const __pci_0_1c_7 = &_dev_rp8;
DEVTREE_CONST void *const __pci_0_1c_7_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_rp8_ptr = &_dev_rp8;
DEVTREE_CONST struct device *const __pci_0_1d_0 = &_dev_ehci1;
DEVTREE_CONST void *const __pci_0_1d_0_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_ehci1_ptr = &_dev_ehci1;
DEVTREE_CONST struct device *const __pci_0_1e_0 = &_dev_pci_b;
DEVTREE_CONST void *const __pci_0_1e_0_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_pci_b_ptr = &_dev_pci_b;
DEVTREE_CONST struct device *const __pci_0_1f_0 = &_dev_lpc;
DEVTREE_CONST void *const __pci_0_1f_0_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_lpc_ptr = &_dev_lpc;
DEVTREE_CONST struct device *const __pci_0_1f_2 = &_dev_sata1;
DEVTREE_CONST void *const __pci_0_1f_2_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_sata1_ptr = &_dev_sata1;
DEVTREE_CONST struct device *const __pci_0_1f_3 = &_dev_smbus;
DEVTREE_CONST void *const __pci_0_1f_3_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_smbus_ptr = &_dev_smbus;
DEVTREE_CONST struct device *const __pci_0_1f_5 = &_dev_sata2;
DEVTREE_CONST void *const __pci_0_1f_5_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_sata2_ptr = &_dev_sata2;
DEVTREE_CONST struct device *const __pci_0_1f_6 = &_dev_thermal;
DEVTREE_CONST void *const __pci_0_1f_6_config = &southbridge_intel_bd82x6x_info_1;
DEVTREE_CONST struct device *const _dev_thermal_ptr = &_dev_thermal;
DEVTREE_CONST struct device *const __pnp_002e_01 = &_dev_4;
DEVTREE_CONST struct device *const __pnp_002e_02 = &_dev_5;
DEVTREE_CONST struct device *const __pnp_002e_03 = &_dev_6;
DEVTREE_CONST struct device *const __pnp_002e_05 = &_dev_7;
DEVTREE_CONST struct device *const __pnp_002e_06 = &_dev_8;
DEVTREE_CONST struct device *const __pnp_002e_07 = &_dev_9;
DEVTREE_CONST struct device *const __pnp_002e_08 = &_dev_10;
DEVTREE_CONST struct device *const __pnp_002e_108 = &_dev_11;
DEVTREE_CONST struct device *const __pnp_002e_09 = &_dev_12;
DEVTREE_CONST struct device *const __pnp_002e_109 = &_dev_13;
DEVTREE_CONST struct device *const __pnp_002e_209 = &_dev_14;
DEVTREE_CONST struct device *const __pnp_002e_309 = &_dev_15;
DEVTREE_CONST struct device *const __pnp_002e_409 = &_dev_16;
DEVTREE_CONST struct device *const __pnp_002e_509 = &_dev_17;
DEVTREE_CONST struct device *const __pnp_002e_609 = &_dev_18;
DEVTREE_CONST struct device *const __pnp_002e_709 = &_dev_19;
DEVTREE_CONST struct device *const __pnp_002e_0a = &_dev_20;
DEVTREE_CONST struct device *const __pnp_002e_0b = &_dev_21;
DEVTREE_CONST struct device *const __pnp_002e_0d = &_dev_22;
DEVTREE_CONST struct device *const __pnp_002e_0e = &_dev_23;
DEVTREE_CONST struct device *const __pnp_002e_0f = &_dev_24;
DEVTREE_CONST struct device *const __pnp_002e_14 = &_dev_25;
DEVTREE_CONST struct device *const __pnp_002e_16 = &_dev_26;
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