MyHDL Init Problem

init.py

from __future__ import print_function
from myhdl import *



@block
def unit(clock,reset):

    ip = Signal(intbv(0xc0000000)[32:])

    @always_seq(clock.posedge,reset=reset)
    def seq():

        ip.next = ip + 1

    return instances()


def gen_core():
    clock = Signal(bool(0))
    reset = ResetSignal(0, active=1, isasync=False)

    i_unit = unit(clock,reset)
    i_unit.convert(hdl="VHDL",std_logic_ports=True, initial_values=True)  


gen_core()

unit.vhd

-- File: unit.vhd
-- Generated by MyHDL 0.11
-- Date: Mon Aug  3 19:35:01 2020


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_011.all;

entity unit is
    port (
        clock: in std_logic;
        reset: in std_logic
    );
end entity unit;


architecture MyHDL of unit is



signal ip: unsigned(31 downto 0) := 32X"c0000000";

begin




UNIT_SEQ: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            ip <= unsigned'("11000000000000000000000000000000");
        else
            ip <= (ip + 1);
        end if;
    end if;
end process UNIT_SEQ;

end architecture MyHDL;