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Thraetaona / consciousness.pdf
Last active May 30, 2024 08:22
Consciousness
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Thraetaona / srl_prescaler.vhd
Last active January 30, 2024 23:05
A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers
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-- SPDX-License-Identifier: LGPL-3.0-or-later or CERN-OHL-W-2.0
--
-- srl_prescaler.vhd: A Simple VHDL Abstraction of an Efficient Clock
-- Prescaler Using Cascading Shift Registers.
--
-- Copyright (C) 2024 Fereydoun Memarzanjany
--
-- This hardware-descriptive model is free hardware design dual-licensed under
-- the GNU LGPL or CERN OHL v2 Weakly Reciprocal: you can redistribute it