Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
------------------------------------------------------------------------------- | |
-- SPDX-License-Identifier: LGPL-3.0-or-later or CERN-OHL-W-2.0 | |
-- | |
-- srl_prescaler.vhd: A Simple VHDL Abstraction of an Efficient Clock | |
-- Prescaler Using Cascading Shift Registers. | |
-- | |
-- Copyright (C) 2024 Fereydoun Memarzanjany | |
-- | |
-- This hardware-descriptive model is free hardware design dual-licensed under | |
-- the GNU LGPL or CERN OHL v2 Weakly Reciprocal: you can redistribute it |