ComeNCapture Frontend using iCE40LP1K

ComeNCapFPGA.v

// ComeNCapture front end part. Handles the data sampling and buffer by using iCE40LP1K FPGA as logic capturer.
// Coded by TinLethax 2021/11/26 +7

// Block RAM module, We use ALL bits of BRAM as STORAGE.
module BRAM(
	input CLK,
	input RCLK,
	
	input [7:0]BRAM_IN,
	output reg [7:0]BRAM_OUT,
	
	input [12:0] BRAM_ADDR_R,
	input [12:0] BRAM_ADDR_W,
	
	input B_CE_W,
	input B_CE_R);
	
reg [7:0] mem1 [8191:0];// 8192 Bytes worth of BRAM as logic CAP mem.

initial begin 
mem1[0] <= 255;// this will make Yosys infer this reg as BRAM.

end
always@(posedge RCLK) begin// reading from RAM sync with system clock 
	if(B_CE_R) 
		BRAM_OUT <= mem1[BRAM_ADDR_R];	

end	

always@(posedge CLK) begin// writing to RAM sync with system clock.
	if(B_CE_W) 
		mem1[BRAM_ADDR_W] <= BRAM_IN;

end
	
endmodule// GRAM

// Slave SPI module
module SSPI (
	input MOSI,
	output reg MISO,
	input SCLK,
	input SCE,
	
	// Send back captured data from BRAM to HOST.
	input [7:0] BYTE_2HOST,// memory lane route from BRAM.
	output reg [12:0]B2H_ADDR,// request data from BRAM at address n that count from 0 to 8191.
	output reg R_CE,// BRAM read enable, active high.
	
	// receive command from HOST.
	output reg [7:0]BYTE_CMD,// Host send command to FPGA.
	output reg [1:0]CMD_LEN,// command lenght is 4 bytes.
	output reg CMD_flag// goes 1 when there's cmd from host.
	);
	
// MOSI regs
reg [7:0] SPIbuffer;// buffer for command 
reg [2:0] mosibitCnt;// 3-bit counter from 0-7

// MISO regs
reg [2:0] MISObitCnt;// 3-bit counter from 0-7

initial begin
	SPIbuffer <= 0;
	mosibitCnt <= 0;
	MISObitCnt <= 0;
	B2H_ADDR <= 0;
	CMD_LEN <= 0;
	CMD_flag <= 0;
	R_CE <= 0;
end

always@(posedge SCLK & ~SCE) begin

	// MOSI part, data in. Host will release chip select when host sent 4 bytes, no need for if else checking how many we received.
		if(!mosibitCnt) begin// every 8 clock cycle.
			mosibitCnt <= 0;// reset bit counter 
			CMD_LEN <= CMD_LEN + 1;// move to next byte 
			BYTE_CMD[CMD_LEN] <= SPIbuffer;// copy the freshly made byte to mem.
			CMD_flag <= 1;// at the same time, turn write enable on.
			end
		else
			mosibitCnt <= mosibitCnt + 1;// keep tack of bit 		
		
			
		SPIbuffer[mosibitCnt] <= MOSI;// storing each bit into 8bit reg.

	
	// MISO part, data out. Host will release chip select, no if else to check whether we send 8KBytes or not.
		R_CE <= 1;
		if(!MISObitCnt) begin 
			MISObitCnt <= 0;// reset bit counter 
			B2H_ADDR <= B2H_ADDR + 1;// move to read next byte of BRAM.
			end
		else
			MISObitCnt <= MISObitCnt + 1;// keep counting.
	
		MISO <= BYTE_2HOST[MISObitCnt];// extract each bit and send over MISO line.
	
end// always@

// Host release SPI chip select. logic lvl goes back to HIGH
always@(posedge SCE)begin
	SPIbuffer <= 0;
	mosibitCnt <= 0;
	MISObitCnt <= 0;
	//R_CE <= 0;
end

endmodule// SSPI


module main (input CLK,
	input [7:0]CAP,// 8 Input pins used for data capturing 
	
	//Slave SPI stuffs.
	input SCK,
	input MOSI,
	output wire MISO,
	input CE,
	
	//Interrupt for host.
	output wire INT0);
	
// Sample clock stuffs.
// 12MHz
reg clk_12M;
// 6MHz
reg clk_6M;
// 3MHz
reg clk_3M;
// 1MHz
reg clk_1M;
reg [5:0]clk1m_cnt = 0;
	
// Buffer counter, keep track of every byte to write to BRAM.
reg [12:0] Cap_count = 0;// 14bit counter from 0 to 8191	
	
// Memory stuffs.
// From input channels 
reg [12:0]cap_wr_addr = 0;
reg cap_wr_ce = 0;
// to HOST
wire [7:0]cap2host;
wire [12:0]cap_rd_addr;
wire cap_rd_ce;

// Command buffer.
reg [7:0]cmdbuf[3:0];
wire [7:0]cmd_in;
wire [1:0]cmd_byte_n; 
wire cmd_done;

// params for command and flags
parameter cap_size = 8191;
parameter cmd_cap = 8'h01;
parameter cmd_settrig = 8'hc2;

parameter cap_24m = 8'd24;
parameter cap_12m = 8'd12;
parameter cap_6m = 8'd6;
parameter cap_3m = 8'd3;
parameter cap_1m = 8'd1;

// capture flags set by host.
reg cap24m = 0;// 24MHz cap flag.
reg cap12m = 0;// 12MHz cap flag.
reg cap6m = 0;// 6MHz cap flag.
reg cap3m = 0;// 3MHz cap flag.
reg cap1m = 0;// 1MHz cap flag.

// Trigger mask and sensitivity.
// Trigger mask is to set which will be use as trigger.
// mask : [7:0,CH7, CH6, CH5, CH4, CH3, CH2, CH1, CH0].
// Sensitivity is use for rising or falling detection.
// sensi : [7:0, CH7, CH6, CH5, CH4, CH3, CH2, CH1, CH0].
reg [7:0]trig_mask;
reg [7:0]trig_sens;

// INT flag
// Interrupt flag set to 1 after capture is done.
reg INT_flag;
assign INT0 = INT_flag;

BRAM capRam(
	.CLK(CLK),
	.RCLK(SCK),
	.BRAM_IN(CAP),
	.BRAM_OUT(cap2host),
	
	.BRAM_ADDR_R(cap_rd_addr),
	.BRAM_ADDR_W(cap_wr_addr),
	
	.B_CE_W(cap_wr_ce),
	.B_CE_R(cap_rd_ce)
	);
	
SSPI SPIPHY(
	.MOSI(MOSI),
	.MISO(MISO),
	.SCLK(SCK),
	.SCE(CE),
	
	.BYTE_2HOST(cap2host),
	.B2H_ADDR(cap_rd_addr),
	.R_CE(cap_rd_ce),
	
	.BYTE_CMD(cmd_in),
	.CMD_LEN(cmd_byte_n),
	.CMD_flag(cmd_done)
	);
	
// 24MSa/s
// running at 48MHz for sampling 24MHz.
always@(posedge CLK)begin// We use to generate various clock frequency for each sample rate.

	// Sys clock running at 48MHz, use for 24MHz capture. can be improved in future.
	if(cap24m) begin 
		cap_wr_ce <= 1;// enable mem write.
		Cap_count <= Cap_count + 1;
		if(Cap_count == cap_size) begin 
			//cap_wr_addr <= 8191;// set to last address and ready to write to it.
			//Cap_count <= 0;// reset the capture count.
			cap24m <= 0;// stop capture
			//cap_wr_ce <= 0;// prevent from unnecessay write to BRAM.
			INT_flag <= 1;// Set interrupt flag
			end
		
		cap_wr_addr <= Cap_count;// write at current address.

	end// 24MHz capture
	
	
	//  command decoder.
	//cmdbuf[cmd_byte_n] <= cmd_in;// store all 4 bytes into command buffer, auto-increment.
	
	if(cmd_done) begin // if host sent all 4 byte cmd
		case(cmdbuf[0])
		
			// Flag: Capture setup, host sends what Sample rate will be captured. Capture start immediately after this command is decoded.
			// Format [0:cmd][1:speed][2:0x00][3:0x00]
			cmd_cap: begin
				case(cmdbuf[1])
					cap_24m: cap24m <= 1;
					cap_12m: cap12m <= 1;
					cap_6m:	cap6m <= 1;
					cap_3m: cap3m <= 1; 
					cap_1m: cap1m <= 1;
					//default:
				endcase
				end
				
			// Flag: Trigger setup, host sends trigger mask (to select which channel) and trigger sensitivity of each channel (trig when low or hi).
			// Host sends before send flag_cap.
			// Format [0:cmd][1:mask][2:sensi][3:0x00]
			cmd_settrig: begin
					trig_mask <= cmdbuf[1];
					trig_sens <= cmdbuf[2];
				end
				
			//default: //Other than that, do nothing.
		endcase
	end
	
	
	// clock dividers for each sample rate.
	
	// 12Mhz
	clk_12M <= ~clk_12M;
	
	// 1MHz
	clk1m_cnt <= clk1m_cnt + 1;
	if(clk1m_cnt == 47) begin
		clk_1M = ~ clk_1M;
		clk1m_cnt <= 0;
	end
	
end

// 12MSa/s
// Running at 24MHz for sampling 12MHz.
always@(posedge clk_12M) begin
	clk_6M <= ~clk_6M;
	
	if(cap12m) begin 
		cap_wr_ce <= 1;// enable mem write.
		Cap_count <= Cap_count + 1;
		if(Cap_count == cap_size) begin 
			//cap_wr_addr <= 8191;// set to last address and ready to write to it.
			//Cap_count <= 0;// reset the capture count.
			cap12m <= 0;// stop capture
			//cap_wr_ce <= 0;// prevent from unnecessay write to BRAM.
			INT_flag <= 1;// Set interrupt flag
			end
		
			cap_wr_addr <= Cap_count;// write at current address.

	end// 12MHz capture
	
end

// 6MSa/s
// Running at 12MHz for sampling 6MHz.
always@(posedge clk_6M) begin
	clk_3M <= ~clk_3M;
	
	if(cap6m) begin 
		cap_wr_ce <= 1;// enable mem write.
		Cap_count <= Cap_count + 1;
		if(Cap_count == cap_size) begin 
			//cap_wr_addr <= 8191;// set to last address and ready to write to it.
			//Cap_count <= 0;// reset the capture count.
			cap6m <= 0;// stop capture
			//cap_wr_ce <= 0;// prevent from unnecessay write to BRAM.
			INT_flag <= 1;// Set interrupt flag
			end
		else
			cap_wr_addr <= Cap_count;// write at current address.

	end// 6MHz capture
	
end

// 3MSa/s
// Running at 6MHz for sampling 3MHz
always@(posedge clk_3M) begin

	if(cap3m) begin 
		cap_wr_ce <= 1;// enable mem write.
		Cap_count <= Cap_count + 1;
		if(Cap_count == cap_size) begin 
			//cap_wr_addr <= 8191;// set to last address and ready to write to it.
			//Cap_count <= 0;// reset the capture count.
			cap3m <= 0;// stop capture
			//cap_wr_ce <= 0;// prevent from unnecessay write to BRAM.
			INT_flag <= 1;// Set interrupt flag
			end
		
			cap_wr_addr <= Cap_count;// write at current address.

	end// 3MHz capture
	
end

// 1MSa/s
// Running at 2MHz for sampling 1MHz
always@(posedge clk_1M) begin

	if(cap1m) begin 
		cap_wr_ce <= 1;// enable mem write.
		Cap_count <= Cap_count + 1;
		if(Cap_count == cap_size) begin 
			//cap_wr_addr <= 8191;// set to last address and ready to write to it.
			//Cap_count <= 0;// reset the capture count.
			cap1m <= 0;// stop capture
			//cap_wr_ce <= 0;// prevent from unnecessay write to BRAM.
			INT_flag <= 1;// Set interrupt flag
			end
		else
			cap_wr_addr <= Cap_count;// write at current address.

	end// 1MHz capture
	
end

always@(posedge INT_flag) begin
		// at pos edge of INT_flag, LED turns on and trigger host into IRQ to receive data from FPGA.
		//cap_rd_ce <= 1;// allow Slave SPI module to read from BRAM.
end

// reset values to default after host release SPI (which it means that we have done the capture).
always@(posedge CE) begin
	//cap_wr_addr <= 0;
	INT_flag <= 0;
end

endmodule// main

Yosys_log.txt

yosys -g -p "synth_ice40 -json main.json -blif main.blif" main.v

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.11+50 (git sha1 707d98b06, clang 11.0.1-2 -fPIC -Os)


-- Parsing `main.v' using frontend `verilog' --

1. Executing Verilog-2005 frontend: main.v
Parsing Verilog input from `main.v' to AST representation.
Generating RTLIL representation for module `\BRAM'.
Generating RTLIL representation for module `\SSPI'.
Generating RTLIL representation for module `\main'.
Successfully finished Verilog frontend.

-- Running command `synth_ice40 -json main.json -blif main.blif' --

2. Executing SYNTH_ICE40 pass.

2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_sim.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\SB_IO'.
Generating RTLIL representation for module `\SB_GB_IO'.
Generating RTLIL representation for module `\SB_GB'.
Generating RTLIL representation for module `\SB_LUT4'.
Generating RTLIL representation for module `\SB_CARRY'.
Generating RTLIL representation for module `\SB_DFF'.
Generating RTLIL representation for module `\SB_DFFE'.
Generating RTLIL representation for module `\SB_DFFSR'.
Generating RTLIL representation for module `\SB_DFFR'.
Generating RTLIL representation for module `\SB_DFFSS'.
Generating RTLIL representation for module `\SB_DFFS'.
Generating RTLIL representation for module `\SB_DFFESR'.
Generating RTLIL representation for module `\SB_DFFER'.
Generating RTLIL representation for module `\SB_DFFESS'.
Generating RTLIL representation for module `\SB_DFFES'.
Generating RTLIL representation for module `\SB_DFFN'.
Generating RTLIL representation for module `\SB_DFFNE'.
Generating RTLIL representation for module `\SB_DFFNSR'.
Generating RTLIL representation for module `\SB_DFFNR'.
Generating RTLIL representation for module `\SB_DFFNSS'.
Generating RTLIL representation for module `\SB_DFFNS'.
Generating RTLIL representation for module `\SB_DFFNESR'.
Generating RTLIL representation for module `\SB_DFFNER'.
Generating RTLIL representation for module `\SB_DFFNESS'.
Generating RTLIL representation for module `\SB_DFFNES'.
Generating RTLIL representation for module `\SB_RAM40_4K'.
Generating RTLIL representation for module `\SB_RAM40_4KNR'.
Generating RTLIL representation for module `\SB_RAM40_4KNW'.
Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
Generating RTLIL representation for module `\ICESTORM_LC'.
Generating RTLIL representation for module `\SB_PLL40_CORE'.
Generating RTLIL representation for module `\SB_PLL40_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
Generating RTLIL representation for module `\SB_WARMBOOT'.
Generating RTLIL representation for module `\SB_SPRAM256KA'.
Generating RTLIL representation for module `\SB_HFOSC'.
Generating RTLIL representation for module `\SB_LFOSC'.
Generating RTLIL representation for module `\SB_RGBA_DRV'.
Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
Generating RTLIL representation for module `\SB_RGB_DRV'.
Generating RTLIL representation for module `\SB_I2C'.
Generating RTLIL representation for module `\SB_SPI'.
Generating RTLIL representation for module `\SB_LEDDA_IP'.
Generating RTLIL representation for module `\SB_FILTER_50NS'.
Generating RTLIL representation for module `\SB_IO_I3C'.
Generating RTLIL representation for module `\SB_IO_OD'.
Generating RTLIL representation for module `\SB_MAC16'.
Generating RTLIL representation for module `\ICESTORM_RAM'.
Successfully finished Verilog frontend.

2.2. Executing HIERARCHY pass (managing design hierarchy).

2.2.1. Finding top of design hierarchy..
root of   1 design levels: main                
root of   0 design levels: SSPI                
root of   0 design levels: BRAM                
Automatically selected main as design top module.

2.2.2. Analyzing design hierarchy..
Top module:  \main
Used module:     \SSPI
Used module:     \BRAM

2.2.3. Analyzing design hierarchy..
Top module:  \main
Used module:     \SSPI
Used module:     \BRAM
Removed 0 unused modules.

2.3. Executing PROC pass (convert processes to netlists).

2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `main.$proc$main.v:366$79'.
Cleaned up 0 empty switches.

2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1386$330 in module SB_DFFNES.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1328$323 in module SB_DFFNESS.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1251$319 in module SB_DFFNER.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1193$312 in module SB_DFFNESR.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1122$309 in module SB_DFFNS.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1072$306 in module SB_DFFNSS.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1001$303 in module SB_DFFNR.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:951$300 in module SB_DFFNSR.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:789$292 in module SB_DFFES.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:731$285 in module SB_DFFESS.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:654$281 in module SB_DFFER.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:596$274 in module SB_DFFESR.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:525$271 in module SB_DFFS.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:475$268 in module SB_DFFSS.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:404$265 in module SB_DFFR.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:354$262 in module SB_DFFSR.
Marked 1 switch rules as full_case in process $proc$main.v:347$76 in module main.
Marked 1 switch rules as full_case in process $proc$main.v:304$69 in module main.
Marked 1 switch rules as full_case in process $proc$main.v:215$54 in module main.
Marked 2 switch rules as full_case in process $proc$main.v:73$21 in module SSPI.
Marked 1 switch rules as full_case in process $proc$main.v:30$5 in module BRAM.
Removed a total of 0 dead cases.

2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 10 redundant assignments.
Promoted 60 assignments to connections.

2.3.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$333'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$329'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$322'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$318'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$311'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$308'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$305'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$302'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$299'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$297'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$295'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$291'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$284'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$280'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$273'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$270'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$267'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$264'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$261'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$259'.
  Set init value: \Q = 1'0
Found init rule in `\main.$proc$main.v:169$88'.
  Set init value: \cap3m = 1'0
Found init rule in `\main.$proc$main.v:168$87'.
  Set init value: \cap6m = 1'0
Found init rule in `\main.$proc$main.v:167$86'.
  Set init value: \cap12m = 1'0
Found init rule in `\main.$proc$main.v:166$85'.
  Set init value: \cap24m = 1'0
Found init rule in `\main.$proc$main.v:142$84'.
  Set init value: \cap_wr_ce = 1'0
Found init rule in `\main.$proc$main.v:141$83'.
  Set init value: \cap_wr_addr = 13'0000000000000
Found init rule in `\main.$proc$main.v:137$82'.
  Set init value: \Cap_count = 13'0000000000000
Found init rule in `\main.$proc$main.v:134$81'.
  Set init value: \clk1m_cnt = 6'000000
Found init rule in `\main.$proc$main.v:170$89'.
  Set init value: \cap1m = 1'0
Found init rule in `\SSPI.$proc$main.v:0$53'.
  Set init value: \B2H_ADDR = 13'0000000000000
  Set init value: \R_CE = 1'0
  Set init value: \CMD_LEN = 2'00
  Set init value: \CMD_flag = 1'0
  Set init value: \SPIbuffer = 8'00000000
  Set init value: \mosibitCnt = 3'000
  Set init value: \MISObitCnt = 3'000

2.3.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \S in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1386$330'.
Found async reset \R in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1251$319'.
Found async reset \S in `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1122$309'.
Found async reset \R in `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1001$303'.
Found async reset \S in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:789$292'.
Found async reset \R in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:654$281'.
Found async reset \S in `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:525$271'.
Found async reset \R in `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:404$265'.

2.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$333'.
Creating decoders for process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1386$330'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$329'.
Creating decoders for process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1328$323'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$322'.
Creating decoders for process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1251$319'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$318'.
Creating decoders for process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1193$312'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$311'.
Creating decoders for process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1122$309'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$308'.
Creating decoders for process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1072$306'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$305'.
Creating decoders for process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1001$303'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$302'.
Creating decoders for process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:951$300'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$299'.
Creating decoders for process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:906$298'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$297'.
Creating decoders for process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:868$296'.
Creating decoders for process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$295'.
Creating decoders for process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:789$292'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$291'.
Creating decoders for process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:731$285'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$284'.
Creating decoders for process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:654$281'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$280'.
Creating decoders for process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:596$274'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$273'.
Creating decoders for process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:525$271'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$270'.
Creating decoders for process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:475$268'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$267'.
Creating decoders for process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:404$265'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$264'.
Creating decoders for process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:354$262'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$261'.
Creating decoders for process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:309$260'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$259'.
Creating decoders for process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:271$258'.
Creating decoders for process `\main.$proc$main.v:169$88'.
Creating decoders for process `\main.$proc$main.v:168$87'.
Creating decoders for process `\main.$proc$main.v:167$86'.
Creating decoders for process `\main.$proc$main.v:166$85'.
Creating decoders for process `\main.$proc$main.v:142$84'.
Creating decoders for process `\main.$proc$main.v:141$83'.
Creating decoders for process `\main.$proc$main.v:137$82'.
Creating decoders for process `\main.$proc$main.v:134$81'.
Creating decoders for process `\main.$proc$main.v:372$80'.
Creating decoders for process `\main.$proc$main.v:170$89'.
Creating decoders for process `\main.$proc$main.v:347$76'.
     1/5: $4\INT_flag[0:0]
     2/5: $1\cap1m[0:0]
     3/5: $4\cap_wr_ce[0:0]
     4/5: $4\cap_wr_addr[12:0]
     5/5: $4\Cap_count[12:0]
Creating decoders for process `\main.$proc$main.v:326$73'.
     1/5: $3\INT_flag[0:0]
     2/5: $1\cap3m[0:0]
     3/5: $3\cap_wr_ce[0:0]
     4/5: $3\cap_wr_addr[12:0]
     5/5: $3\Cap_count[12:0]
Creating decoders for process `\main.$proc$main.v:304$69'.
     1/5: $2\INT_flag[0:0]
     2/5: $1\cap6m[0:0]
     3/5: $2\cap_wr_ce[0:0]
     4/5: $2\cap_wr_addr[12:0]
     5/5: $2\Cap_count[12:0]
Creating decoders for process `\main.$proc$main.v:282$65'.
     1/5: $1\INT_flag[0:0]
     2/5: $1\cap12m[0:0]
     3/5: $1\cap_wr_ce[0:0]
     4/5: $1\cap_wr_addr[12:0]
     5/5: $1\Cap_count[12:0]
Creating decoders for process `\main.$proc$main.v:215$54'.
     1/13: $1\clk_1M[0:0]
     2/13: $0\clk1m_cnt[5:0]
     3/13: $0\INT_flag[0:0]
     4/13: $0\trig_sens[7:0]
     5/13: $0\trig_mask[7:0]
     6/13: $0\cap1m[0:0]
     7/13: $0\cap3m[0:0]
     8/13: $0\cap6m[0:0]
     9/13: $0\cap12m[0:0]
    10/13: $0\cap24m[0:0]
    11/13: $0\cap_wr_ce[0:0]
    12/13: $0\cap_wr_addr[12:0]
    13/13: $0\Cap_count[12:0]
Creating decoders for process `\SSPI.$proc$main.v:0$53'.
Creating decoders for process `\SSPI.$proc$main.v:103$52'.
Creating decoders for process `\SSPI.$proc$main.v:73$21'.
     1/8: $0\MISObitCnt[2:0]
     2/8: $1$lookahead\BYTE_CMD$19[7:0]$33
     3/8: $1$bitselwrite$data$main.v:79$16[7:0]$32
     4/8: $1$bitselwrite$mask$main.v:79$15[7:0]$31
     5/8: $0\mosibitCnt[2:0]
     6/8: $0\CMD_flag[0:0]
     7/8: $0\CMD_LEN[1:0]
     8/8: $0\B2H_ADDR[12:0]
Creating decoders for process `\BRAM.$proc$main.v:0$13'.
Creating decoders for process `\BRAM.$proc$main.v:30$5'.
     1/3: $1$memwr$\mem1$main.v:32$2_EN[7:0]$11
     2/3: $1$memwr$\mem1$main.v:32$2_DATA[7:0]$10
     3/3: $1$memwr$\mem1$main.v:32$2_ADDR[12:0]$9
Creating decoders for process `\BRAM.$proc$main.v:24$3'.
     1/1: $0\BRAM_OUT[7:0]

2.3.7. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\BRAM.$memwr$\mem1$main.v:21$1_EN' from process `\BRAM.$proc$main.v:0$13'.

2.3.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1386$330'.
  created $adff cell `$procdff$688' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1328$323'.
  created $dff cell `$procdff$689' with negative edge clock.
Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1251$319'.
  created $adff cell `$procdff$690' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1193$312'.
  created $dff cell `$procdff$691' with negative edge clock.
Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1122$309'.
  created $adff cell `$procdff$692' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1072$306'.
  created $dff cell `$procdff$693' with negative edge clock.
Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1001$303'.
  created $adff cell `$procdff$694' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:951$300'.
  created $dff cell `$procdff$695' with negative edge clock.
Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:906$298'.
  created $dff cell `$procdff$696' with negative edge clock.
Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:868$296'.
  created $dff cell `$procdff$697' with negative edge clock.
Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:789$292'.
  created $adff cell `$procdff$698' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:731$285'.
  created $dff cell `$procdff$699' with positive edge clock.
Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:654$281'.
  created $adff cell `$procdff$700' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:596$274'.
  created $dff cell `$procdff$701' with positive edge clock.
Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:525$271'.
  created $adff cell `$procdff$702' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:475$268'.
  created $dff cell `$procdff$703' with positive edge clock.
Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:404$265'.
  created $adff cell `$procdff$704' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:354$262'.
  created $dff cell `$procdff$705' with positive edge clock.
Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:309$260'.
  created $dff cell `$procdff$706' with positive edge clock.
Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:271$258'.
  created $dff cell `$procdff$707' with positive edge clock.
Creating register for signal `\main.\INT_flag' using process `\main.$proc$main.v:372$80'.
  created $dff cell `$procdff$708' with positive edge clock.
Creating register for signal `\main.\Cap_count' using process `\main.$proc$main.v:347$76'.
  created $dff cell `$procdff$709' with positive edge clock.
Creating register for signal `\main.\cap_wr_addr' using process `\main.$proc$main.v:347$76'.
  created $dff cell `$procdff$710' with positive edge clock.
Creating register for signal `\main.\cap_wr_ce' using process `\main.$proc$main.v:347$76'.
  created $dff cell `$procdff$711' with positive edge clock.
Creating register for signal `\main.\cap1m' using process `\main.$proc$main.v:347$76'.
  created $dff cell `$procdff$712' with positive edge clock.
Creating register for signal `\main.\INT_flag' using process `\main.$proc$main.v:347$76'.
  created $dff cell `$procdff$713' with positive edge clock.
Creating register for signal `\main.\Cap_count' using process `\main.$proc$main.v:326$73'.
  created $dff cell `$procdff$714' with positive edge clock.
Creating register for signal `\main.\cap_wr_addr' using process `\main.$proc$main.v:326$73'.
  created $dff cell `$procdff$715' with positive edge clock.
Creating register for signal `\main.\cap_wr_ce' using process `\main.$proc$main.v:326$73'.
  created $dff cell `$procdff$716' with positive edge clock.
Creating register for signal `\main.\cap3m' using process `\main.$proc$main.v:326$73'.
  created $dff cell `$procdff$717' with positive edge clock.
Creating register for signal `\main.\INT_flag' using process `\main.$proc$main.v:326$73'.
  created $dff cell `$procdff$718' with positive edge clock.
Creating register for signal `\main.\clk_3M' using process `\main.$proc$main.v:304$69'.
  created $dff cell `$procdff$719' with positive edge clock.
Creating register for signal `\main.\Cap_count' using process `\main.$proc$main.v:304$69'.
  created $dff cell `$procdff$720' with positive edge clock.
Creating register for signal `\main.\cap_wr_addr' using process `\main.$proc$main.v:304$69'.
  created $dff cell `$procdff$721' with positive edge clock.
Creating register for signal `\main.\cap_wr_ce' using process `\main.$proc$main.v:304$69'.
  created $dff cell `$procdff$722' with positive edge clock.
Creating register for signal `\main.\cap6m' using process `\main.$proc$main.v:304$69'.
  created $dff cell `$procdff$723' with positive edge clock.
Creating register for signal `\main.\INT_flag' using process `\main.$proc$main.v:304$69'.
  created $dff cell `$procdff$724' with positive edge clock.
Creating register for signal `\main.\clk_6M' using process `\main.$proc$main.v:282$65'.
  created $dff cell `$procdff$725' with positive edge clock.
Creating register for signal `\main.\Cap_count' using process `\main.$proc$main.v:282$65'.
  created $dff cell `$procdff$726' with positive edge clock.
Creating register for signal `\main.\cap_wr_addr' using process `\main.$proc$main.v:282$65'.
  created $dff cell `$procdff$727' with positive edge clock.
Creating register for signal `\main.\cap_wr_ce' using process `\main.$proc$main.v:282$65'.
  created $dff cell `$procdff$728' with positive edge clock.
Creating register for signal `\main.\cap12m' using process `\main.$proc$main.v:282$65'.
  created $dff cell `$procdff$729' with positive edge clock.
Creating register for signal `\main.\INT_flag' using process `\main.$proc$main.v:282$65'.
  created $dff cell `$procdff$730' with positive edge clock.
Creating register for signal `\main.\clk_12M' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$731' with positive edge clock.
Creating register for signal `\main.\clk_1M' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$732' with positive edge clock.
Creating register for signal `\main.\clk1m_cnt' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$733' with positive edge clock.
Creating register for signal `\main.\Cap_count' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$734' with positive edge clock.
Creating register for signal `\main.\cap_wr_addr' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$735' with positive edge clock.
Creating register for signal `\main.\cap_wr_ce' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$736' with positive edge clock.
Creating register for signal `\main.\cap24m' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$737' with positive edge clock.
Creating register for signal `\main.\cap12m' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$738' with positive edge clock.
Creating register for signal `\main.\cap6m' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$739' with positive edge clock.
Creating register for signal `\main.\cap3m' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$740' with positive edge clock.
Creating register for signal `\main.\cap1m' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$741' with positive edge clock.
Creating register for signal `\main.\trig_mask' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$742' with positive edge clock.
Creating register for signal `\main.\trig_sens' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$743' with positive edge clock.
Creating register for signal `\main.\INT_flag' using process `\main.$proc$main.v:215$54'.
  created $dff cell `$procdff$744' with positive edge clock.
Creating register for signal `\SSPI.\SPIbuffer' using process `\SSPI.$proc$main.v:103$52'.
  created $dff cell `$procdff$745' with positive edge clock.
Creating register for signal `\SSPI.\mosibitCnt' using process `\SSPI.$proc$main.v:103$52'.
  created $dff cell `$procdff$746' with positive edge clock.
Creating register for signal `\SSPI.\MISObitCnt' using process `\SSPI.$proc$main.v:103$52'.
  created $dff cell `$procdff$747' with positive edge clock.
Creating register for signal `\SSPI.\MISO' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$748' with positive edge clock.
Creating register for signal `\SSPI.\B2H_ADDR' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$749' with positive edge clock.
Creating register for signal `\SSPI.\R_CE' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$750' with positive edge clock.
Creating register for signal `\SSPI.\BYTE_CMD' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$751' with positive edge clock.
Creating register for signal `\SSPI.\CMD_LEN' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$752' with positive edge clock.
Creating register for signal `\SSPI.\CMD_flag' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$753' with positive edge clock.
Creating register for signal `\SSPI.\SPIbuffer' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$754' with positive edge clock.
Creating register for signal `\SSPI.\mosibitCnt' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$755' with positive edge clock.
Creating register for signal `\SSPI.\MISObitCnt' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$756' with positive edge clock.
Creating register for signal `\SSPI.$bitselwrite$mask$main.v:79$15' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$757' with positive edge clock.
Creating register for signal `\SSPI.$bitselwrite$data$main.v:79$16' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$758' with positive edge clock.
Creating register for signal `\SSPI.$bitselwrite$mask$main.v:86$17' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$759' with positive edge clock.
Creating register for signal `\SSPI.$bitselwrite$data$main.v:86$18' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$760' with positive edge clock.
Creating register for signal `\SSPI.$lookahead\BYTE_CMD$19' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$761' with positive edge clock.
Creating register for signal `\SSPI.$lookahead\SPIbuffer$20' using process `\SSPI.$proc$main.v:73$21'.
  created $dff cell `$procdff$762' with positive edge clock.
Creating register for signal `\BRAM.$memwr$\mem1$main.v:32$2_ADDR' using process `\BRAM.$proc$main.v:30$5'.
  created $dff cell `$procdff$763' with positive edge clock.
Creating register for signal `\BRAM.$memwr$\mem1$main.v:32$2_DATA' using process `\BRAM.$proc$main.v:30$5'.
  created $dff cell `$procdff$764' with positive edge clock.
Creating register for signal `\BRAM.$memwr$\mem1$main.v:32$2_EN' using process `\BRAM.$proc$main.v:30$5'.
  created $dff cell `$procdff$765' with positive edge clock.
Creating register for signal `\BRAM.\BRAM_OUT' using process `\BRAM.$proc$main.v:24$3'.
  created $dff cell `$procdff$766' with positive edge clock.

2.3.9. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$333'.
Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1386$330'.
Removing empty process `SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1386$330'.
Removing empty process `SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$329'.
Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1328$323'.
Removing empty process `SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1328$323'.
Removing empty process `SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$322'.
Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1251$319'.
Removing empty process `SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1251$319'.
Removing empty process `SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$318'.
Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1193$312'.
Removing empty process `SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1193$312'.
Removing empty process `SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$311'.
Removing empty process `SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1122$309'.
Removing empty process `SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$308'.
Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1072$306'.
Removing empty process `SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1072$306'.
Removing empty process `SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$305'.
Removing empty process `SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1001$303'.
Removing empty process `SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$302'.
Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:951$300'.
Removing empty process `SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:951$300'.
Removing empty process `SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$299'.
Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:906$298'.
Removing empty process `SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:906$298'.
Removing empty process `SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$297'.
Removing empty process `SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:868$296'.
Removing empty process `SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$295'.
Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:789$292'.
Removing empty process `SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:789$292'.
Removing empty process `SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$291'.
Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:731$285'.
Removing empty process `SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:731$285'.
Removing empty process `SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$284'.
Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:654$281'.
Removing empty process `SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:654$281'.
Removing empty process `SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$280'.
Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:596$274'.
Removing empty process `SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:596$274'.
Removing empty process `SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$273'.
Removing empty process `SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:525$271'.
Removing empty process `SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$270'.
Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:475$268'.
Removing empty process `SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:475$268'.
Removing empty process `SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$267'.
Removing empty process `SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:404$265'.
Removing empty process `SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$264'.
Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:354$262'.
Removing empty process `SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:354$262'.
Removing empty process `SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$261'.
Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:309$260'.
Removing empty process `SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:309$260'.
Removing empty process `SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$259'.
Removing empty process `SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:271$258'.
Removing empty process `main.$proc$main.v:169$88'.
Removing empty process `main.$proc$main.v:168$87'.
Removing empty process `main.$proc$main.v:167$86'.
Removing empty process `main.$proc$main.v:166$85'.
Removing empty process `main.$proc$main.v:142$84'.
Removing empty process `main.$proc$main.v:141$83'.
Removing empty process `main.$proc$main.v:137$82'.
Removing empty process `main.$proc$main.v:134$81'.
Removing empty process `main.$proc$main.v:372$80'.
Removing empty process `main.$proc$main.v:170$89'.
Found and cleaned up 2 empty switches in `\main.$proc$main.v:347$76'.
Removing empty process `main.$proc$main.v:347$76'.
Found and cleaned up 2 empty switches in `\main.$proc$main.v:326$73'.
Removing empty process `main.$proc$main.v:326$73'.
Found and cleaned up 2 empty switches in `\main.$proc$main.v:304$69'.
Removing empty process `main.$proc$main.v:304$69'.
Found and cleaned up 2 empty switches in `\main.$proc$main.v:282$65'.
Removing empty process `main.$proc$main.v:282$65'.
Found and cleaned up 6 empty switches in `\main.$proc$main.v:215$54'.
Removing empty process `main.$proc$main.v:215$54'.
Removing empty process `SSPI.$proc$main.v:0$53'.
Removing empty process `SSPI.$proc$main.v:103$52'.
Found and cleaned up 2 empty switches in `\SSPI.$proc$main.v:73$21'.
Removing empty process `SSPI.$proc$main.v:73$21'.
Removing empty process `BRAM.$proc$main.v:0$13'.
Found and cleaned up 1 empty switch in `\BRAM.$proc$main.v:30$5'.
Removing empty process `BRAM.$proc$main.v:30$5'.
Found and cleaned up 1 empty switch in `\BRAM.$proc$main.v:24$3'.
Removing empty process `BRAM.$proc$main.v:24$3'.
Cleaned up 36 empty switches.

2.3.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.
Optimizing module SSPI.
Replacing $and cell `$and$main.v:0$43' (and_or_buffer) in module `\SSPI' with constant driver `$and$main.v:0$43_Y = { 7'0000000 \MOSI }'.
Optimizing module BRAM.

2.4. Executing FLATTEN pass (flatten design).
Flattening main.capRam (BRAM).
Flattening main.SPIPHY (SSPI).
Deleting now unused module SSPI.
Deleting now unused module BRAM.

2.5. Executing TRIBUF pass.

2.6. Executing DEMINOUT pass (demote inout ports to input or output).

2.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
  removing unused `$memrd' cell `$memrd$\cmdbuf$main.v:257$59'.
  removing unused `$memrd' cell `$memrd$\cmdbuf$main.v:258$60'.
  removing unused `$dff' cell `$flatten\capRam.$procdff$765'.
  removing unused `$dff' cell `$flatten\capRam.$procdff$764'.
  removing unused `$dff' cell `$flatten\capRam.$procdff$763'.
  removing unused `$eq' cell `$procmux$591_CMP0'.
  removing unused `$mux' cell `$procmux$590'.
  removing unused `$mux' cell `$procmux$592'.
  removing unused `$eq' cell `$procmux$595_CMP0'.
  removing unused `$mux' cell `$procmux$594'.
  removing unused `$mux' cell `$procmux$596'.
  removing unused `$dff' cell `$procdff$742'.
  removing unused `$dff' cell `$procdff$743'.
  removing unused `$dff' cell `$flatten\SPIPHY.$procdff$761'.
  removing unused `$dff' cell `$flatten\SPIPHY.$procdff$760'.
  removing unused `$dff' cell `$flatten\SPIPHY.$procdff$759'.
  removing unused `$dff' cell `$flatten\SPIPHY.$procdff$758'.
  removing unused `$dff' cell `$flatten\SPIPHY.$procdff$757'.
  removing unused `$dff' cell `$flatten\SPIPHY.$procdff$754'.
  removing unused `$dff' cell `$flatten\SPIPHY.$procdff$752'.
  removing unused `$dff' cell `$flatten\SPIPHY.$procdff$751'.
  removing unused `$dff' cell `$flatten\SPIPHY.$procdff$745'.
  removing unused `$mux' cell `$flatten\SPIPHY.$procmux$672'.
  removing unused `$mux' cell `$flatten\SPIPHY.$procmux$663'.
  removing unused `$mux' cell `$flatten\SPIPHY.$procmux$660'.
  removing unused `$mux' cell `$flatten\SPIPHY.$procmux$657'.
  removing unused `$or' cell `$flatten\SPIPHY.$or$main.v:0$47'.
  removing unused `$and' cell `$flatten\SPIPHY.$and$main.v:0$46'.
  removing unused `$not' cell `$flatten\SPIPHY.$not$main.v:0$45'.
  removing unused `$shl' cell `$flatten\SPIPHY.$shl$main.v:0$44'.
  removing unused `$dff' cell `$flatten\SPIPHY.$procdff$762'.
  removing unused `$shl' cell `$flatten\SPIPHY.$shl$main.v:0$42'.
  removing unused `$or' cell `$flatten\SPIPHY.$or$main.v:0$40'.
  removing unused `$and' cell `$flatten\SPIPHY.$and$main.v:0$39'.
  removing unused `$not' cell `$flatten\SPIPHY.$not$main.v:0$38'.
  removing unused `$shl' cell `$flatten\SPIPHY.$shl$main.v:0$37'.
  removing unused `$and' cell `$flatten\SPIPHY.$and$main.v:0$36'.
  removing unused `$shl' cell `$flatten\SPIPHY.$shl$main.v:0$35'.
  removing unused `$add' cell `$flatten\SPIPHY.$add$main.v:78$34'.
  removing unused non-port wire \trig_mask.
  removing unused non-port wire \trig_sens.
  removing unused non-port wire $0\trig_mask[7:0].
  removing unused non-port wire $0\trig_sens[7:0].
  removing unused non-port wire $memrd$\cmdbuf$main.v:257$59_DATA.
  removing unused non-port wire $memrd$\cmdbuf$main.v:258$60_DATA.
  removing unused non-port wire $not$main.v:269$61_Y.
  removing unused non-port wire $1\clk_1M[0:0].
  removing unused non-port wire $not$main.v:283$66_Y.
  removing unused non-port wire $not$main.v:305$70_Y.
  removing unused non-port wire $5\INT_flag[0:0].
  removing unused non-port wire $1\clk1m_cnt[5:0].
  removing unused non-port wire $5\Cap_count[12:0].
  removing unused non-port wire $5\cap_wr_addr[12:0].
  removing unused non-port wire $5\cap_wr_ce[0:0].
  removing unused non-port wire $1\cap24m[0:0].
  removing unused non-port wire $2\cap12m[0:0].
  removing unused non-port wire $2\cap6m[0:0].
  removing unused non-port wire $2\cap3m[0:0].
  removing unused non-port wire $2\cap1m[0:0].
  removing unused non-port wire $procmux$516_CMP.
  removing unused non-port wire $procmux$518_CMP.
  removing unused non-port wire $procmux$517_Y.
  removing unused non-port wire $procmux$521_CMP.
  removing unused non-port wire $procmux$523_CMP.
  removing unused non-port wire $procmux$522_Y.
  removing unused non-port wire $procmux$525_CMP.
  removing unused non-port wire $procmux$524_Y.
  removing unused non-port wire $procmux$528_CMP.
  removing unused non-port wire $procmux$530_CMP.
  removing unused non-port wire $procmux$529_Y.
  removing unused non-port wire $procmux$532_CMP.
  removing unused non-port wire $procmux$531_Y.
  removing unused non-port wire $procmux$534_CMP.
  removing unused non-port wire $procmux$536_CMP.
  removing unused non-port wire $procmux$535_Y.
  removing unused non-port wire $procmux$538_CMP.
  removing unused non-port wire $procmux$540_CMP.
  removing unused non-port wire $procmux$539_Y.
  removing unused non-port wire $procmux$542_CMP.
  removing unused non-port wire $procmux$541_Y.
  removing unused non-port wire $procmux$544_CMP.
  removing unused non-port wire $procmux$543_Y.
  removing unused non-port wire $procmux$546_CMP.
  removing unused non-port wire $procmux$545_Y.
  removing unused non-port wire $procmux$549_CMP.
  removing unused non-port wire $procmux$551_CMP.
  removing unused non-port wire $procmux$550_Y.
  removing unused non-port wire $procmux$554_CMP.
  removing unused non-port wire $procmux$556_CMP.
  removing unused non-port wire $procmux$555_Y.
  removing unused non-port wire $procmux$558_CMP.
  removing unused non-port wire $procmux$557_Y.
  removing unused non-port wire $procmux$561_CMP.
  removing unused non-port wire $procmux$563_CMP.
  removing unused non-port wire $procmux$562_Y.
  removing unused non-port wire $procmux$565_CMP.
  removing unused non-port wire $procmux$564_Y.
  removing unused non-port wire $procmux$567_CMP.
  removing unused non-port wire $procmux$569_CMP.
  removing unused non-port wire $procmux$568_Y.
  removing unused non-port wire $procmux$571_CMP.
  removing unused non-port wire $procmux$573_CMP.
  removing unused non-port wire $procmux$572_Y.
  removing unused non-port wire $procmux$575_CMP.
  removing unused non-port wire $procmux$574_Y.
  removing unused non-port wire $procmux$577_CMP.
  removing unused non-port wire $procmux$576_Y.
  removing unused non-port wire $procmux$579_CMP.
  removing unused non-port wire $procmux$578_Y.
  removing unused non-port wire $procmux$582_CMP.
  removing unused non-port wire $procmux$581_Y.
  removing unused non-port wire $procmux$585_CMP.
  removing unused non-port wire $procmux$584_Y.
  removing unused non-port wire $procmux$587_CMP.
  removing unused non-port wire $procmux$589_CMP.
  removing unused non-port wire $procmux$588_Y.
  removing unused non-port wire $procmux$591_CMP.
  removing unused non-port wire $procmux$590_Y.
  removing unused non-port wire $procmux$593_CMP.
  removing unused non-port wire $procmux$592_Y.
  removing unused non-port wire $procmux$595_CMP.
  removing unused non-port wire $procmux$594_Y.
  removing unused non-port wire $procmux$597_CMP.
  removing unused non-port wire $procmux$596_Y.
  removing unused non-port wire $procmux$604_CMP.
  removing unused non-port wire $procmux$603_Y.
  removing unused non-port wire $procmux$612_CMP.
  removing unused non-port wire $procmux$611_Y.
  removing unused non-port wire $procmux$621_CMP.
  removing unused non-port wire $procmux$620_Y.
  removing unused non-port wire $procmux$631_CMP.
  removing unused non-port wire $procmux$630_Y.
  removing unused non-port wire $procmux$633_CMP.
  removing unused non-port wire $procmux$635_CMP.
  removing unused non-port wire $procmux$646_CMP.
  removing unused non-port wire $procmux$645_Y.
  removing unused non-port wire $procmux$648_CMP.
  removing unused non-port wire $procmux$647_Y.
  removing unused non-port wire $procmux$650_CMP.
  removing unused non-port wire $procmux$649_Y.
  removing unused non-port wire $procmux$652_CMP.
  removing unused non-port wire $procmux$651_Y.
  removing unused non-port wire $flatten\capRam.$procmux$686_Y.
  removing unused non-port wire $flatten\capRam.$procmux$687_CMP.
  removing unused non-port wire $flatten\capRam.$procmux$684_Y.
  removing unused non-port wire $flatten\capRam.$procmux$685_CMP.
  removing unused non-port wire $flatten\capRam.$procmux$681_Y.
  removing unused non-port wire $flatten\capRam.$procmux$682_CMP.
  removing unused non-port wire $flatten\capRam.$procmux$678_Y.
  removing unused non-port wire $flatten\capRam.$procmux$679_CMP.
  removing unused non-port wire $flatten\capRam.$0$memwr$\mem1$main.v:21$1_EN[7:0]$14.
  removing unused non-port wire $flatten\capRam.$1$memwr$\mem1$main.v:32$2_EN[7:0]$11.
  removing unused non-port wire $flatten\capRam.$1$memwr$\mem1$main.v:32$2_DATA[7:0]$10.
  removing unused non-port wire $flatten\capRam.$1$memwr$\mem1$main.v:32$2_ADDR[12:0]$9.
  removing unused non-port wire $flatten\capRam.$memwr$\mem1$main.v:32$2_EN.
  removing unused non-port wire $flatten\capRam.$memwr$\mem1$main.v:32$2_DATA.
  removing unused non-port wire $flatten\capRam.$memwr$\mem1$main.v:32$2_ADDR.
  removing unused non-port wire $flatten\capRam.$memwr$\mem1$main.v:21$1_EN.
  removing unused non-port wire $flatten\SPIPHY.$procmux$675_Y.
  removing unused non-port wire $flatten\SPIPHY.$procmux$676_CMP.
  removing unused non-port wire $flatten\SPIPHY.$procmux$672_Y.
  removing unused non-port wire $flatten\SPIPHY.$procmux$673_CMP.
  removing unused non-port wire $flatten\SPIPHY.$procmux$669_Y.
  removing unused non-port wire $flatten\SPIPHY.$procmux$670_CMP.
  removing unused non-port wire $flatten\SPIPHY.$procmux$666_Y.
  removing unused non-port wire $flatten\SPIPHY.$procmux$667_CMP.
  removing unused non-port wire $flatten\SPIPHY.$procmux$663_Y.
  removing unused non-port wire $flatten\SPIPHY.$procmux$664_CMP.
  removing unused non-port wire $flatten\SPIPHY.$procmux$660_Y.
  removing unused non-port wire $flatten\SPIPHY.$procmux$661_CMP.
  removing unused non-port wire $flatten\SPIPHY.$procmux$657_Y.
  removing unused non-port wire $flatten\SPIPHY.$procmux$658_CMP.
  removing unused non-port wire $flatten\SPIPHY.$procmux$654_Y.
  removing unused non-port wire $flatten\SPIPHY.$procmux$655_CMP.
  removing unused non-port wire $flatten\SPIPHY.$2\MISObitCnt[2:0].
  removing unused non-port wire $flatten\SPIPHY.$2\mosibitCnt[2:0].
  removing unused non-port wire $flatten\SPIPHY.$2\SPIbuffer[7:0].
  removing unused non-port wire $flatten\SPIPHY.$1\CMD_flag[0:0].
  removing unused non-port wire $flatten\SPIPHY.$1\CMD_LEN[1:0].
  removing unused non-port wire $flatten\SPIPHY.$1\R_CE[0:0].
  removing unused non-port wire $flatten\SPIPHY.$1\B2H_ADDR[12:0].
  removing unused non-port wire $flatten\SPIPHY.$1\MISObitCnt[2:0].
  removing unused non-port wire $flatten\SPIPHY.$1\mosibitCnt[2:0].
  removing unused non-port wire $flatten\SPIPHY.$1\SPIbuffer[7:0].
  removing unused non-port wire $flatten\SPIPHY.$shiftx$main.v:0$51_Y.
  removing unused non-port wire $flatten\SPIPHY.$or$main.v:0$47_Y.
  removing unused non-port wire $flatten\SPIPHY.$and$main.v:0$46_Y.
  removing unused non-port wire $flatten\SPIPHY.$not$main.v:0$45_Y.
  removing unused non-port wire $flatten\SPIPHY.$shl$main.v:0$44_Y.
  removing unused non-port wire $flatten\SPIPHY.$and$main.v:0$43_Y.
  removing unused non-port wire $flatten\SPIPHY.$shl$main.v:0$42_Y.
  removing unused non-port wire $flatten\SPIPHY.$or$main.v:0$40_Y.
  removing unused non-port wire $flatten\SPIPHY.$and$main.v:0$39_Y.
  removing unused non-port wire $flatten\SPIPHY.$not$main.v:0$38_Y.
  removing unused non-port wire $flatten\SPIPHY.$shl$main.v:0$37_Y.
  removing unused non-port wire $flatten\SPIPHY.$and$main.v:0$36_Y.
  removing unused non-port wire $flatten\SPIPHY.$shl$main.v:0$35_Y.
  removing unused non-port wire $flatten\SPIPHY.$add$main.v:78$34_Y.
  removing unused non-port wire $flatten\SPIPHY.$1$lookahead\BYTE_CMD$19[7:0]$33.
  removing unused non-port wire $flatten\SPIPHY.$1$bitselwrite$data$main.v:79$16[7:0]$32.
  removing unused non-port wire $flatten\SPIPHY.$1$bitselwrite$mask$main.v:79$15[7:0]$31.
  removing unused non-port wire $flatten\SPIPHY.$0$lookahead\SPIbuffer$20[7:0]$27.
  removing unused non-port wire $flatten\SPIPHY.$0$lookahead\BYTE_CMD$19[7:0]$26.
  removing unused non-port wire $flatten\SPIPHY.$0$bitselwrite$data$main.v:86$18[7:0]$25.
  removing unused non-port wire $flatten\SPIPHY.$0$bitselwrite$mask$main.v:86$17[7:0]$24.
  removing unused non-port wire $flatten\SPIPHY.$0$bitselwrite$data$main.v:79$16[7:0]$23.
  removing unused non-port wire $flatten\SPIPHY.$0$bitselwrite$mask$main.v:79$15[7:0]$22.
  removing unused non-port wire $flatten\SPIPHY.$0\SPIbuffer[7:0].
  removing unused non-port wire $flatten\SPIPHY.$0\CMD_LEN[1:0].
  removing unused non-port wire $flatten\SPIPHY.$0\BYTE_CMD[7:0].
  removing unused non-port wire $flatten\SPIPHY.$0\R_CE[0:0].
  removing unused non-port wire $flatten\SPIPHY.$lookahead\SPIbuffer$20.
  removing unused non-port wire $flatten\SPIPHY.$lookahead\BYTE_CMD$19.
  removing unused non-port wire $flatten\SPIPHY.$bitselwrite$data$main.v:86$18.
  removing unused non-port wire $flatten\SPIPHY.$bitselwrite$mask$main.v:86$17.
  removing unused non-port wire $flatten\SPIPHY.$bitselwrite$data$main.v:79$16.
  removing unused non-port wire $flatten\SPIPHY.$bitselwrite$mask$main.v:79$15.
  removing unused non-port wire \SPIPHY.SPIbuffer.
  removing unused non-port wire \SPIPHY.CMD_LEN.
  removing unused non-port wire \SPIPHY.BYTE_CMD.
  removing unused non-port wire \cmd_in.
  removing unused non-port wire \cmd_byte_n.
Removed 39 unused cells and 183 unused wires.

2.9. Executing CHECK pass (checking for obvious problems).
Checking module main...
Warning: multiple conflicting drivers for main.\cap12m:
    port Q[0] of cell $procdff$729 ($dff)
    port Q[0] of cell $procdff$738 ($dff)
Warning: multiple conflicting drivers for main.\cap6m:
    port Q[0] of cell $procdff$723 ($dff)
    port Q[0] of cell $procdff$739 ($dff)
Warning: multiple conflicting drivers for main.\cap3m:
    port Q[0] of cell $procdff$717 ($dff)
    port Q[0] of cell $procdff$740 ($dff)
Warning: multiple conflicting drivers for main.\cap1m:
    port Q[0] of cell $procdff$712 ($dff)
    port Q[0] of cell $procdff$741 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_ce:
    port Q[0] of cell $procdff$711 ($dff)
    port Q[0] of cell $procdff$716 ($dff)
    port Q[0] of cell $procdff$722 ($dff)
    port Q[0] of cell $procdff$728 ($dff)
    port Q[0] of cell $procdff$736 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [12]:
    port Q[12] of cell $procdff$710 ($dff)
    port Q[12] of cell $procdff$715 ($dff)
    port Q[12] of cell $procdff$721 ($dff)
    port Q[12] of cell $procdff$727 ($dff)
    port Q[12] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [11]:
    port Q[11] of cell $procdff$710 ($dff)
    port Q[11] of cell $procdff$715 ($dff)
    port Q[11] of cell $procdff$721 ($dff)
    port Q[11] of cell $procdff$727 ($dff)
    port Q[11] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [10]:
    port Q[10] of cell $procdff$710 ($dff)
    port Q[10] of cell $procdff$715 ($dff)
    port Q[10] of cell $procdff$721 ($dff)
    port Q[10] of cell $procdff$727 ($dff)
    port Q[10] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [9]:
    port Q[9] of cell $procdff$710 ($dff)
    port Q[9] of cell $procdff$715 ($dff)
    port Q[9] of cell $procdff$721 ($dff)
    port Q[9] of cell $procdff$727 ($dff)
    port Q[9] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [8]:
    port Q[8] of cell $procdff$710 ($dff)
    port Q[8] of cell $procdff$715 ($dff)
    port Q[8] of cell $procdff$721 ($dff)
    port Q[8] of cell $procdff$727 ($dff)
    port Q[8] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [7]:
    port Q[7] of cell $procdff$710 ($dff)
    port Q[7] of cell $procdff$715 ($dff)
    port Q[7] of cell $procdff$721 ($dff)
    port Q[7] of cell $procdff$727 ($dff)
    port Q[7] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [6]:
    port Q[6] of cell $procdff$710 ($dff)
    port Q[6] of cell $procdff$715 ($dff)
    port Q[6] of cell $procdff$721 ($dff)
    port Q[6] of cell $procdff$727 ($dff)
    port Q[6] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [5]:
    port Q[5] of cell $procdff$710 ($dff)
    port Q[5] of cell $procdff$715 ($dff)
    port Q[5] of cell $procdff$721 ($dff)
    port Q[5] of cell $procdff$727 ($dff)
    port Q[5] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [4]:
    port Q[4] of cell $procdff$710 ($dff)
    port Q[4] of cell $procdff$715 ($dff)
    port Q[4] of cell $procdff$721 ($dff)
    port Q[4] of cell $procdff$727 ($dff)
    port Q[4] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [3]:
    port Q[3] of cell $procdff$710 ($dff)
    port Q[3] of cell $procdff$715 ($dff)
    port Q[3] of cell $procdff$721 ($dff)
    port Q[3] of cell $procdff$727 ($dff)
    port Q[3] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [2]:
    port Q[2] of cell $procdff$710 ($dff)
    port Q[2] of cell $procdff$715 ($dff)
    port Q[2] of cell $procdff$721 ($dff)
    port Q[2] of cell $procdff$727 ($dff)
    port Q[2] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [1]:
    port Q[1] of cell $procdff$710 ($dff)
    port Q[1] of cell $procdff$715 ($dff)
    port Q[1] of cell $procdff$721 ($dff)
    port Q[1] of cell $procdff$727 ($dff)
    port Q[1] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\cap_wr_addr [0]:
    port Q[0] of cell $procdff$710 ($dff)
    port Q[0] of cell $procdff$715 ($dff)
    port Q[0] of cell $procdff$721 ($dff)
    port Q[0] of cell $procdff$727 ($dff)
    port Q[0] of cell $procdff$735 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [12]:
    port Q[12] of cell $procdff$709 ($dff)
    port Q[12] of cell $procdff$714 ($dff)
    port Q[12] of cell $procdff$720 ($dff)
    port Q[12] of cell $procdff$726 ($dff)
    port Q[12] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [11]:
    port Q[11] of cell $procdff$709 ($dff)
    port Q[11] of cell $procdff$714 ($dff)
    port Q[11] of cell $procdff$720 ($dff)
    port Q[11] of cell $procdff$726 ($dff)
    port Q[11] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [10]:
    port Q[10] of cell $procdff$709 ($dff)
    port Q[10] of cell $procdff$714 ($dff)
    port Q[10] of cell $procdff$720 ($dff)
    port Q[10] of cell $procdff$726 ($dff)
    port Q[10] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [9]:
    port Q[9] of cell $procdff$709 ($dff)
    port Q[9] of cell $procdff$714 ($dff)
    port Q[9] of cell $procdff$720 ($dff)
    port Q[9] of cell $procdff$726 ($dff)
    port Q[9] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [8]:
    port Q[8] of cell $procdff$709 ($dff)
    port Q[8] of cell $procdff$714 ($dff)
    port Q[8] of cell $procdff$720 ($dff)
    port Q[8] of cell $procdff$726 ($dff)
    port Q[8] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [7]:
    port Q[7] of cell $procdff$709 ($dff)
    port Q[7] of cell $procdff$714 ($dff)
    port Q[7] of cell $procdff$720 ($dff)
    port Q[7] of cell $procdff$726 ($dff)
    port Q[7] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [6]:
    port Q[6] of cell $procdff$709 ($dff)
    port Q[6] of cell $procdff$714 ($dff)
    port Q[6] of cell $procdff$720 ($dff)
    port Q[6] of cell $procdff$726 ($dff)
    port Q[6] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [5]:
    port Q[5] of cell $procdff$709 ($dff)
    port Q[5] of cell $procdff$714 ($dff)
    port Q[5] of cell $procdff$720 ($dff)
    port Q[5] of cell $procdff$726 ($dff)
    port Q[5] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [4]:
    port Q[4] of cell $procdff$709 ($dff)
    port Q[4] of cell $procdff$714 ($dff)
    port Q[4] of cell $procdff$720 ($dff)
    port Q[4] of cell $procdff$726 ($dff)
    port Q[4] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [3]:
    port Q[3] of cell $procdff$709 ($dff)
    port Q[3] of cell $procdff$714 ($dff)
    port Q[3] of cell $procdff$720 ($dff)
    port Q[3] of cell $procdff$726 ($dff)
    port Q[3] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [2]:
    port Q[2] of cell $procdff$709 ($dff)
    port Q[2] of cell $procdff$714 ($dff)
    port Q[2] of cell $procdff$720 ($dff)
    port Q[2] of cell $procdff$726 ($dff)
    port Q[2] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [1]:
    port Q[1] of cell $procdff$709 ($dff)
    port Q[1] of cell $procdff$714 ($dff)
    port Q[1] of cell $procdff$720 ($dff)
    port Q[1] of cell $procdff$726 ($dff)
    port Q[1] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\Cap_count [0]:
    port Q[0] of cell $procdff$709 ($dff)
    port Q[0] of cell $procdff$714 ($dff)
    port Q[0] of cell $procdff$720 ($dff)
    port Q[0] of cell $procdff$726 ($dff)
    port Q[0] of cell $procdff$734 ($dff)
Warning: multiple conflicting drivers for main.\INT_flag:
    port Q[0] of cell $procdff$708 ($dff)
    port Q[0] of cell $procdff$713 ($dff)
    port Q[0] of cell $procdff$718 ($dff)
    port Q[0] of cell $procdff$724 ($dff)
    port Q[0] of cell $procdff$730 ($dff)
    port Q[0] of cell $procdff$744 ($dff)
Warning: multiple conflicting drivers for main.\SPIPHY.MISObitCnt [2]:
    port Q[2] of cell $flatten\SPIPHY.$procdff$747 ($dff)
    port Q[2] of cell $flatten\SPIPHY.$procdff$756 ($dff)
Warning: multiple conflicting drivers for main.\SPIPHY.MISObitCnt [1]:
    port Q[1] of cell $flatten\SPIPHY.$procdff$747 ($dff)
    port Q[1] of cell $flatten\SPIPHY.$procdff$756 ($dff)
Warning: multiple conflicting drivers for main.\SPIPHY.MISObitCnt [0]:
    port Q[0] of cell $flatten\SPIPHY.$procdff$747 ($dff)
    port Q[0] of cell $flatten\SPIPHY.$procdff$756 ($dff)
Warning: multiple conflicting drivers for main.\SPIPHY.mosibitCnt [2]:
    port Q[2] of cell $flatten\SPIPHY.$procdff$746 ($dff)
    port Q[2] of cell $flatten\SPIPHY.$procdff$755 ($dff)
Warning: multiple conflicting drivers for main.\SPIPHY.mosibitCnt [1]:
    port Q[1] of cell $flatten\SPIPHY.$procdff$746 ($dff)
    port Q[1] of cell $flatten\SPIPHY.$procdff$755 ($dff)
Warning: multiple conflicting drivers for main.\SPIPHY.mosibitCnt [0]:
    port Q[0] of cell $flatten\SPIPHY.$procdff$746 ($dff)
    port Q[0] of cell $flatten\SPIPHY.$procdff$755 ($dff)
Found and reported 38 problems.

2.10. Executing OPT pass (performing simple optimizations).

2.10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
  Cell `$add$main.v:287$67' is identical to cell `$add$main.v:220$55'.
    Redirecting output \Y: $add$main.v:287$67_Y = $add$main.v:220$55_Y
    Removing $add cell `$add$main.v:287$67' from module `\main'.
  Cell `$add$main.v:309$71' is identical to cell `$add$main.v:220$55'.
    Redirecting output \Y: $add$main.v:309$71_Y = $add$main.v:220$55_Y
    Removing $add cell `$add$main.v:309$71' from module `\main'.
  Cell `$add$main.v:330$74' is identical to cell `$add$main.v:220$55'.
    Redirecting output \Y: $add$main.v:330$74_Y = $add$main.v:220$55_Y
    Removing $add cell `$add$main.v:330$74' from module `\main'.
  Cell `$add$main.v:351$77' is identical to cell `$add$main.v:220$55'.
    Redirecting output \Y: $add$main.v:351$77_Y = $add$main.v:220$55_Y
    Removing $add cell `$add$main.v:351$77' from module `\main'.
  Cell `$eq$main.v:288$68' is identical to cell `$eq$main.v:221$56'.
    Redirecting output \Y: $eq$main.v:288$68_Y = $eq$main.v:221$56_Y
    Removing $eq cell `$eq$main.v:288$68' from module `\main'.
  Cell `$eq$main.v:310$72' is identical to cell `$eq$main.v:221$56'.
    Redirecting output \Y: $eq$main.v:310$72_Y = $eq$main.v:221$56_Y
    Removing $eq cell `$eq$main.v:310$72' from module `\main'.
  Cell `$eq$main.v:331$75' is identical to cell `$eq$main.v:221$56'.
    Redirecting output \Y: $eq$main.v:331$75_Y = $eq$main.v:221$56_Y
    Removing $eq cell `$eq$main.v:331$75' from module `\main'.
  Cell `$eq$main.v:352$78' is identical to cell `$eq$main.v:221$56'.
    Redirecting output \Y: $eq$main.v:352$78_Y = $eq$main.v:221$56_Y
    Removing $eq cell `$eq$main.v:352$78' from module `\main'.
  Cell `$flatten\SPIPHY.$procdff$747' is identical to cell `$flatten\SPIPHY.$procdff$746'.
    Redirecting output \Q: \SPIPHY.MISObitCnt = \SPIPHY.mosibitCnt
    Removing $dff cell `$flatten\SPIPHY.$procdff$747' from module `\main'.
  Cell `$procmux$610_CMP0' is identical to cell `$procmux$602_CMP0'.
    Redirecting output \Y: $procmux$610_CMP = $procmux$602_CMP
    Removing $eq cell `$procmux$610_CMP0' from module `\main'.
  Cell `$procmux$619_CMP0' is identical to cell `$procmux$602_CMP0'.
    Redirecting output \Y: $procmux$619_CMP = $procmux$602_CMP
    Removing $eq cell `$procmux$619_CMP0' from module `\main'.
  Cell `$procmux$629_CMP0' is identical to cell `$procmux$602_CMP0'.
    Redirecting output \Y: $procmux$629_CMP = $procmux$602_CMP
    Removing $eq cell `$procmux$629_CMP0' from module `\main'.
  Cell `$procmux$644_CMP0' is identical to cell `$procmux$602_CMP0'.
    Redirecting output \Y: $procmux$644_CMP = $procmux$602_CMP
    Removing $eq cell `$procmux$644_CMP0' from module `\main'.
  Cell `$flatten\SPIPHY.$logic_not$main.v:91$48' is identical to cell `$flatten\SPIPHY.$logic_not$main.v:76$30'.
    Redirecting output \Y: $flatten\SPIPHY.$logic_not$main.v:91$48_Y = $flatten\SPIPHY.$logic_not$main.v:76$30_Y
    Removing $logic_not cell `$flatten\SPIPHY.$logic_not$main.v:91$48' from module `\main'.
  Cell `$flatten\SPIPHY.$add$main.v:83$41' is identical to cell `$flatten\SPIPHY.$add$main.v:96$50'.
    Redirecting output \Y: $flatten\SPIPHY.$add$main.v:83$41_Y = $flatten\SPIPHY.$add$main.v:96$50_Y
    Removing $add cell `$flatten\SPIPHY.$add$main.v:83$41' from module `\main'.
Removed a total of 15 cells.

2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \main..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $flatten\SPIPHY.$procmux$654 (pure)
    Root of a mux tree: $flatten\SPIPHY.$procmux$666 (pure)
    Root of a mux tree: $flatten\SPIPHY.$procmux$669 (pure)
    Root of a mux tree: $flatten\SPIPHY.$procmux$675 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$678 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$681 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$684 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$686 (pure)
    Root of a mux tree: $procmux$517 (pure)
    Root of a mux tree: $procmux$522 (pure)
      Replacing known input bits on port A of cell $procmux$522: \cap1m -> 1'0
      Replacing known input bits on port A of cell $procmux$520: \cap1m -> 1'1
    Root of a mux tree: $procmux$524 (pure)
    Root of a mux tree: $procmux$529 (pure)
    Root of a mux tree: $procmux$531 (pure)
    Root of a mux tree: $procmux$535 (pure)
    Root of a mux tree: $procmux$539 (pure)
      Replacing known input bits on port A of cell $procmux$539: \cap3m -> 1'0
      Replacing known input bits on port A of cell $procmux$537: \cap3m -> 1'1
    Root of a mux tree: $procmux$541 (pure)
    Root of a mux tree: $procmux$543 (pure)
    Root of a mux tree: $procmux$545 (pure)
    Root of a mux tree: $procmux$550 (pure)
    Root of a mux tree: $procmux$555 (pure)
      Replacing known input bits on port A of cell $procmux$555: \cap6m -> 1'0
      Replacing known input bits on port A of cell $procmux$553: \cap6m -> 1'1
    Root of a mux tree: $procmux$557 (pure)
    Root of a mux tree: $procmux$562 (pure)
    Root of a mux tree: $procmux$564 (pure)
    Root of a mux tree: $procmux$568 (pure)
    Root of a mux tree: $procmux$572 (pure)
      Replacing known input bits on port A of cell $procmux$572: \cap12m -> 1'0
      Replacing known input bits on port A of cell $procmux$570: \cap12m -> 1'1
    Root of a mux tree: $procmux$574 (pure)
    Root of a mux tree: $procmux$576 (pure)
    Root of a mux tree: $procmux$578 (pure)
    Root of a mux tree: $procmux$581 (pure)
    Root of a mux tree: $procmux$584 (pure)
    Root of a mux tree: $procmux$588 (pure)
    Root of a mux tree: $procmux$603 (pure)
    Root of a mux tree: $procmux$611 (pure)
    Root of a mux tree: $procmux$620 (pure)
    Root of a mux tree: $procmux$630 (pure)
    Root of a mux tree: $procmux$634
      Replacing known input bits on port A of cell $procmux$634: \cap24m -> 1'0
      Replacing known input bits on port A of cell $procmux$632: \cap24m -> 1'1
    Root of a mux tree: $procmux$645 (pure)
    Root of a mux tree: $procmux$647 (pure)
    Root of a mux tree: $procmux$649 (pure)
    Root of a mux tree: $procmux$651 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \main.
    Consolidated identical input bits for $mux cell $flatten\capRam.$procmux$678:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\capRam.$0$memwr$\mem1$main.v:32$2_EN[7:0]$8
      New ports: A=1'0, B=1'1, Y=$flatten\capRam.$0$memwr$\mem1$main.v:32$2_EN[7:0]$8 [0]
      New connections: $flatten\capRam.$0$memwr$\mem1$main.v:32$2_EN[7:0]$8 [7:1] = { $flatten\capRam.$0$memwr$\mem1$main.v:32$2_EN[7:0]$8 [0] $flatten\capRam.$0$memwr$\mem1$main.v:32$2_EN[7:0]$8 [0] $flatten\capRam.$0$memwr$\mem1$main.v:32$2_EN[7:0]$8 [0] $flatten\capRam.$0$memwr$\mem1$main.v:32$2_EN[7:0]$8 [0] $flatten\capRam.$0$memwr$\mem1$main.v:32$2_EN[7:0]$8 [0] $flatten\capRam.$0$memwr$\mem1$main.v:32$2_EN[7:0]$8 [0] $flatten\capRam.$0$memwr$\mem1$main.v:32$2_EN[7:0]$8 [0] }
  Optimizing cells in module \main.
Performed a total of 1 changes.

2.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
  Cell `$flatten\SPIPHY.$procmux$666' is identical to cell `$flatten\SPIPHY.$procmux$654'.
    Redirecting output \Y: $flatten\SPIPHY.$0\mosibitCnt[2:0] = $flatten\SPIPHY.$0\MISObitCnt[2:0]
    Removing $mux cell `$flatten\SPIPHY.$procmux$666' from module `\main'.
  Cell `$procmux$533' is identical to cell `$procmux$515'.
    Redirecting output \Y: $procmux$533_Y = $procmux$515_Y
    Removing $mux cell `$procmux$533' from module `\main'.
  Cell `$procmux$537' is identical to cell `$procmux$520'.
    Redirecting output \Y: $procmux$537_Y = $procmux$520_Y
    Removing $mux cell `$procmux$537' from module `\main'.
  Cell `$procmux$548' is identical to cell `$procmux$515'.
    Redirecting output \Y: $procmux$548_Y = $procmux$515_Y
    Removing $mux cell `$procmux$548' from module `\main'.
  Cell `$procmux$553' is identical to cell `$procmux$520'.
    Redirecting output \Y: $procmux$553_Y = $procmux$520_Y
    Removing $mux cell `$procmux$553' from module `\main'.
  Cell `$procmux$560' is identical to cell `$procmux$527'.
    Redirecting output \Y: $procmux$560_Y = $procmux$527_Y
    Removing $mux cell `$procmux$560' from module `\main'.
  Cell `$procmux$566' is identical to cell `$procmux$515'.
    Redirecting output \Y: $procmux$566_Y = $procmux$515_Y
    Removing $mux cell `$procmux$566' from module `\main'.
  Cell `$procmux$570' is identical to cell `$procmux$520'.
    Redirecting output \Y: $procmux$570_Y = $procmux$520_Y
    Removing $mux cell `$procmux$570' from module `\main'.
  Cell `$procmux$586' is identical to cell `$procmux$515'.
    Redirecting output \Y: $procmux$586_Y = $procmux$515_Y
    Removing $mux cell `$procmux$586' from module `\main'.
  Cell `$procmux$632' is identical to cell `$procmux$520'.
    Redirecting output \Y: $procmux$632_Y = $procmux$520_Y
    Removing $mux cell `$procmux$632' from module `\main'.
  Cell `$flatten\SPIPHY.$procdff$756' is identical to cell `$flatten\SPIPHY.$procdff$755'.
    Redirecting output \Q: \SPIPHY.MISObitCnt = \SPIPHY.mosibitCnt
    Removing $dff cell `$flatten\SPIPHY.$procdff$756' from module `\main'.
Removed a total of 11 cells.

2.10.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $flatten\SPIPHY.$procdff$746 ($dff) from module main.
Setting constant 0-bit at position 1 on $flatten\SPIPHY.$procdff$746 ($dff) from module main.
Setting constant 0-bit at position 2 on $flatten\SPIPHY.$procdff$746 ($dff) from module main.
Setting constant 0-bit at position 0 on $procdff$708 ($dff) from module main.

2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
  removing unused `$mux' cell `$procmux$515'.
  removing unused `$mux' cell `$procmux$517'.
  removing unused `$mux' cell `$procmux$535'.
  removing unused `$mux' cell `$procmux$550'.
  removing unused `$mux' cell `$procmux$568'.
  removing unused `$mux' cell `$procmux$588'.
  removing unused `$dff' cell `$procdff$713'.
  removing unused `$dff' cell `$procdff$718'.
  removing unused `$dff' cell `$procdff$724'.
  removing unused `$dff' cell `$procdff$730'.
  removing unused `$dff' cell `$procdff$744'.
  removing unused `$dff' cell `$flatten\SPIPHY.$procdff$755'.
  removing unused `$mux' cell `$flatten\SPIPHY.$procmux$654'.
  removing unused `$add' cell `$flatten\SPIPHY.$add$main.v:96$50'.
Warning: Driver-driver conflict for \SPIPHY.mosibitCnt [2] between cell $flatten\SPIPHY.$procdff$755.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \SPIPHY.mosibitCnt [1] between cell $flatten\SPIPHY.$procdff$755.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \SPIPHY.mosibitCnt [0] between cell $flatten\SPIPHY.$procdff$755.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \INT_flag between cell $procdff$713.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \INT_flag between cell $procdff$718.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \INT_flag between cell $procdff$724.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \INT_flag between cell $procdff$730.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \INT_flag between cell $procdff$744.Q and constant 1'0 in main: Resolved using constant.
  removing unused non-port wire $procmux$644_CMP.
  removing unused non-port wire $procmux$632_Y.
  removing unused non-port wire $procmux$629_CMP.
  removing unused non-port wire $procmux$619_CMP.
  removing unused non-port wire $procmux$610_CMP.
  removing unused non-port wire $procmux$586_Y.
  removing unused non-port wire $procmux$570_Y.
  removing unused non-port wire $procmux$566_Y.
  removing unused non-port wire $procmux$560_Y.
  removing unused non-port wire $procmux$553_Y.
  removing unused non-port wire $procmux$548_Y.
  removing unused non-port wire $procmux$537_Y.
  removing unused non-port wire $procmux$533_Y.
  removing unused non-port wire $procmux$515_Y.
  removing unused non-port wire $flatten\SPIPHY.$logic_not$main.v:91$48_Y.
  removing unused non-port wire $flatten\SPIPHY.$add$main.v:96$50_Y.
  removing unused non-port wire $flatten\SPIPHY.$add$main.v:83$41_Y.
  removing unused non-port wire $flatten\SPIPHY.$0\mosibitCnt[2:0].
  removing unused non-port wire $flatten\SPIPHY.$0\MISObitCnt[2:0].
  removing unused non-port wire $eq$main.v:352$78_Y.
  removing unused non-port wire $eq$main.v:331$75_Y.
  removing unused non-port wire $eq$main.v:310$72_Y.
  removing unused non-port wire $eq$main.v:288$68_Y.
  removing unused non-port wire $add$main.v:351$77_Y.
  removing unused non-port wire $add$main.v:330$74_Y.
  removing unused non-port wire $add$main.v:309$71_Y.
  removing unused non-port wire $add$main.v:287$67_Y.
  removing unused non-port wire $4\INT_flag[0:0].
  removing unused non-port wire $3\INT_flag[0:0].
  removing unused non-port wire $2\INT_flag[0:0].
  removing unused non-port wire $1\INT_flag[0:0].
  removing unused non-port wire $0\INT_flag[0:0].
Removed 14 unused cells and 32 unused wires.

2.10.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.
Replacing $logic_not cell `$flatten\SPIPHY.$logic_not$main.v:76$30' (3'000) in module `\main' with constant driver `$flatten\SPIPHY.$logic_not$main.v:76$30_Y = 1'1'.
Replacing $mux cell `$flatten\SPIPHY.$procmux$675' (1) in module `\main' with constant driver `$flatten\SPIPHY.$0\B2H_ADDR[12:0] = $flatten\SPIPHY.$add$main.v:93$49_Y [12:0]'.
Replacing $mux cell `$flatten\SPIPHY.$procmux$669' (1) in module `\main' with constant driver `$flatten\SPIPHY.$0\CMD_flag[0:0] = 1'1'.
Replacing $shiftx cell `$flatten\SPIPHY.$shiftx$main.v:0$51' (B=3'000, SHR=0) in module `main' with fixed wiring: \capRam.BRAM_OUT [0]

2.10.9. Rerunning OPT passes. (Maybe there is more to do..)

2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \main..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $flatten\capRam.$procmux$678 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$681 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$684 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$686 (pure)
    Root of a mux tree: $procmux$520
    Root of a mux tree: $procmux$522 (pure)
    Root of a mux tree: $procmux$524 (pure)
    Root of a mux tree: $procmux$527
    Root of a mux tree: $procmux$529 (pure)
    Root of a mux tree: $procmux$531 (pure)
    Root of a mux tree: $procmux$539 (pure)
    Root of a mux tree: $procmux$541 (pure)
    Root of a mux tree: $procmux$543 (pure)
    Root of a mux tree: $procmux$545 (pure)
    Root of a mux tree: $procmux$555 (pure)
    Root of a mux tree: $procmux$557 (pure)
    Root of a mux tree: $procmux$562 (pure)
    Root of a mux tree: $procmux$564 (pure)
    Root of a mux tree: $procmux$572 (pure)
    Root of a mux tree: $procmux$574 (pure)
    Root of a mux tree: $procmux$576 (pure)
    Root of a mux tree: $procmux$578 (pure)
    Root of a mux tree: $procmux$581 (pure)
    Root of a mux tree: $procmux$584 (pure)
    Root of a mux tree: $procmux$603 (pure)
    Root of a mux tree: $procmux$611 (pure)
    Root of a mux tree: $procmux$620 (pure)
    Root of a mux tree: $procmux$630 (pure)
    Root of a mux tree: $procmux$634
    Root of a mux tree: $procmux$645 (pure)
    Root of a mux tree: $procmux$647 (pure)
    Root of a mux tree: $procmux$649 (pure)
    Root of a mux tree: $procmux$651 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \main.
Performed a total of 0 changes.

2.10.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
  Cell `$flatten\SPIPHY.$procdff$753' is identical to cell `$flatten\SPIPHY.$procdff$750'.
    Redirecting output \Q: \SPIPHY.CMD_flag = \SPIPHY.R_CE
    Removing $dff cell `$flatten\SPIPHY.$procdff$753' from module `\main'.
Removed a total of 1 cells.

2.10.13. Executing OPT_DFF pass (perform DFF optimizations).

2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
  removing unused non-port wire $flatten\SPIPHY.$logic_not$main.v:76$30_Y.
  removing unused non-port wire $flatten\SPIPHY.$0\MISO[0:0].
  removing unused non-port wire $flatten\SPIPHY.$0\CMD_flag[0:0].
Removed 0 unused cells and 3 unused wires.

2.10.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.10.16. Rerunning OPT passes. (Maybe there is more to do..)

2.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \main..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $flatten\capRam.$procmux$678 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$681 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$684 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$686 (pure)
    Root of a mux tree: $procmux$520
    Root of a mux tree: $procmux$522 (pure)
    Root of a mux tree: $procmux$524 (pure)
    Root of a mux tree: $procmux$527
    Root of a mux tree: $procmux$529 (pure)
    Root of a mux tree: $procmux$531 (pure)
    Root of a mux tree: $procmux$539 (pure)
    Root of a mux tree: $procmux$541 (pure)
    Root of a mux tree: $procmux$543 (pure)
    Root of a mux tree: $procmux$545 (pure)
    Root of a mux tree: $procmux$555 (pure)
    Root of a mux tree: $procmux$557 (pure)
    Root of a mux tree: $procmux$562 (pure)
    Root of a mux tree: $procmux$564 (pure)
    Root of a mux tree: $procmux$572 (pure)
    Root of a mux tree: $procmux$574 (pure)
    Root of a mux tree: $procmux$576 (pure)
    Root of a mux tree: $procmux$578 (pure)
    Root of a mux tree: $procmux$581 (pure)
    Root of a mux tree: $procmux$584 (pure)
    Root of a mux tree: $procmux$603 (pure)
    Root of a mux tree: $procmux$611 (pure)
    Root of a mux tree: $procmux$620 (pure)
    Root of a mux tree: $procmux$630 (pure)
    Root of a mux tree: $procmux$634
    Root of a mux tree: $procmux$645 (pure)
    Root of a mux tree: $procmux$647 (pure)
    Root of a mux tree: $procmux$649 (pure)
    Root of a mux tree: $procmux$651 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

2.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \main.
Performed a total of 0 changes.

2.10.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.10.20. Executing OPT_DFF pass (perform DFF optimizations).

2.10.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..

2.10.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.10.23. Finished OPT passes. (There is nothing left to do.)

2.11. Executing FSM pass (extract and optimize FSM).

2.11.1. Executing FSM_DETECT pass (finding FSMs in design).

2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).

2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).

2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..

2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).

2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

2.12. Executing OPT pass (performing simple optimizations).

2.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \main..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $flatten\capRam.$procmux$678 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$681 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$684 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$686 (pure)
    Root of a mux tree: $procmux$520
    Root of a mux tree: $procmux$522 (pure)
    Root of a mux tree: $procmux$524 (pure)
    Root of a mux tree: $procmux$527
    Root of a mux tree: $procmux$529 (pure)
    Root of a mux tree: $procmux$531 (pure)
    Root of a mux tree: $procmux$539 (pure)
    Root of a mux tree: $procmux$541 (pure)
    Root of a mux tree: $procmux$543 (pure)
    Root of a mux tree: $procmux$545 (pure)
    Root of a mux tree: $procmux$555 (pure)
    Root of a mux tree: $procmux$557 (pure)
    Root of a mux tree: $procmux$562 (pure)
    Root of a mux tree: $procmux$564 (pure)
    Root of a mux tree: $procmux$572 (pure)
    Root of a mux tree: $procmux$574 (pure)
    Root of a mux tree: $procmux$576 (pure)
    Root of a mux tree: $procmux$578 (pure)
    Root of a mux tree: $procmux$581 (pure)
    Root of a mux tree: $procmux$584 (pure)
    Root of a mux tree: $procmux$603 (pure)
    Root of a mux tree: $procmux$611 (pure)
    Root of a mux tree: $procmux$620 (pure)
    Root of a mux tree: $procmux$630 (pure)
    Root of a mux tree: $procmux$634
    Root of a mux tree: $procmux$645 (pure)
    Root of a mux tree: $procmux$647 (pure)
    Root of a mux tree: $procmux$649 (pure)
    Root of a mux tree: $procmux$651 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \main.
Performed a total of 0 changes.

2.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.12.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $procdff$741 ($dff) from module main (D = 1'1, Q = \cap1m).
Adding EN signal on $procdff$740 ($dff) from module main (D = 1'1, Q = \cap3m).
Adding EN signal on $procdff$739 ($dff) from module main (D = 1'1, Q = \cap6m).
Adding EN signal on $procdff$738 ($dff) from module main (D = 1'1, Q = \cap12m).
Adding EN signal on $procdff$736 ($dff) from module main (D = 1'1, Q = \cap_wr_ce).
Adding EN signal on $procdff$735 ($dff) from module main (D = \Cap_count, Q = \cap_wr_addr).
Adding EN signal on $procdff$734 ($dff) from module main (D = $add$main.v:220$55_Y [12:0], Q = \Cap_count).
Adding SRST signal on $procdff$733 ($dff) from module main (D = $add$main.v:272$62_Y [5:0], Q = \clk1m_cnt, rval = 6'000000).
Adding EN signal on $procdff$732 ($dff) from module main (D = $not$main.v:274$64_Y, Q = \clk_1M).
Adding SRST signal on $procdff$729 ($dff) from module main (D = $procmux$520_Y, Q = \cap12m, rval = 1'0).
Adding EN signal on $procdff$728 ($dff) from module main (D = 1'1, Q = \cap_wr_ce).
Adding EN signal on $procdff$727 ($dff) from module main (D = \Cap_count, Q = \cap_wr_addr).
Adding EN signal on $procdff$726 ($dff) from module main (D = $add$main.v:220$55_Y [12:0], Q = \Cap_count).
Adding SRST signal on $procdff$723 ($dff) from module main (D = $procmux$520_Y, Q = \cap6m, rval = 1'0).
Adding EN signal on $procdff$722 ($dff) from module main (D = 1'1, Q = \cap_wr_ce).
Adding EN signal on $procdff$721 ($dff) from module main (D = $procmux$527_Y, Q = \cap_wr_addr).
Adding EN signal on $procdff$720 ($dff) from module main (D = $add$main.v:220$55_Y [12:0], Q = \Cap_count).
Adding SRST signal on $procdff$717 ($dff) from module main (D = $procmux$520_Y, Q = \cap3m, rval = 1'0).
Adding EN signal on $procdff$716 ($dff) from module main (D = 1'1, Q = \cap_wr_ce).
Adding EN signal on $procdff$715 ($dff) from module main (D = \Cap_count, Q = \cap_wr_addr).
Adding EN signal on $procdff$714 ($dff) from module main (D = $add$main.v:220$55_Y [12:0], Q = \Cap_count).
Adding SRST signal on $procdff$712 ($dff) from module main (D = $procmux$520_Y, Q = \cap1m, rval = 1'0).
Adding EN signal on $procdff$711 ($dff) from module main (D = 1'1, Q = \cap_wr_ce).
Adding EN signal on $procdff$710 ($dff) from module main (D = $procmux$527_Y, Q = \cap_wr_addr).
Adding EN signal on $procdff$709 ($dff) from module main (D = $add$main.v:220$55_Y [12:0], Q = \Cap_count).
Adding EN signal on $flatten\capRam.$procdff$766 ($dff) from module main (D = $flatten\capRam.$memrd$\mem1$main.v:26$4_DATA, Q = \capRam.BRAM_OUT).

2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
  removing unused `$mux' cell `$flatten\capRam.$procmux$686'.
  removing unused `$mux' cell `$procmux$522'.
  removing unused `$mux' cell `$procmux$524'.
  removing unused `$mux' cell `$procmux$529'.
  removing unused `$mux' cell `$procmux$531'.
  removing unused `$mux' cell `$procmux$539'.
  removing unused `$mux' cell `$procmux$541'.
  removing unused `$mux' cell `$procmux$543'.
  removing unused `$mux' cell `$procmux$545'.
  removing unused `$mux' cell `$procmux$555'.
  removing unused `$mux' cell `$procmux$557'.
  removing unused `$mux' cell `$procmux$562'.
  removing unused `$mux' cell `$procmux$564'.
  removing unused `$mux' cell `$procmux$572'.
  removing unused `$mux' cell `$procmux$574'.
  removing unused `$mux' cell `$procmux$576'.
  removing unused `$mux' cell `$procmux$578'.
  removing unused `$mux' cell `$procmux$581'.
  removing unused `$mux' cell `$procmux$584'.
  removing unused `$mux' cell `$procmux$599'.
  removing unused `$mux' cell `$procmux$601'.
  removing unused `$mux' cell `$procmux$603'.
  removing unused `$mux' cell `$procmux$607'.
  removing unused `$mux' cell `$procmux$609'.
  removing unused `$mux' cell `$procmux$611'.
  removing unused `$mux' cell `$procmux$616'.
  removing unused `$mux' cell `$procmux$618'.
  removing unused `$mux' cell `$procmux$620'.
  removing unused `$mux' cell `$procmux$626'.
  removing unused `$mux' cell `$procmux$628'.
  removing unused `$mux' cell `$procmux$630'.
  removing unused `$mux' cell `$procmux$647'.
  removing unused `$mux' cell `$procmux$649'.
  removing unused `$mux' cell `$procmux$651'.
  removing unused non-port wire $procmux$628_Y.
  removing unused non-port wire $procmux$626_Y.
  removing unused non-port wire $procmux$618_Y.
  removing unused non-port wire $procmux$616_Y.
  removing unused non-port wire $procmux$609_Y.
  removing unused non-port wire $procmux$607_Y.
  removing unused non-port wire $procmux$601_Y.
  removing unused non-port wire $procmux$599_Y.
  removing unused non-port wire $flatten\capRam.$0\BRAM_OUT[7:0].
  removing unused non-port wire $4\cap_wr_ce[0:0].
  removing unused non-port wire $4\cap_wr_addr[12:0].
  removing unused non-port wire $4\Cap_count[12:0].
  removing unused non-port wire $3\cap_wr_ce[0:0].
  removing unused non-port wire $3\cap_wr_addr[12:0].
  removing unused non-port wire $3\Cap_count[12:0].
  removing unused non-port wire $2\cap_wr_ce[0:0].
  removing unused non-port wire $2\cap_wr_addr[12:0].
  removing unused non-port wire $2\Cap_count[12:0].
  removing unused non-port wire $1\cap_wr_ce[0:0].
  removing unused non-port wire $1\cap_wr_addr[12:0].
  removing unused non-port wire $1\cap6m[0:0].
  removing unused non-port wire $1\cap3m[0:0].
  removing unused non-port wire $1\cap1m[0:0].
  removing unused non-port wire $1\cap12m[0:0].
  removing unused non-port wire $1\Cap_count[12:0].
  removing unused non-port wire $0\clk_1M[0:0].
  removing unused non-port wire $0\clk1m_cnt[5:0].
  removing unused non-port wire $0\cap_wr_ce[0:0].
  removing unused non-port wire $0\cap_wr_addr[12:0].
  removing unused non-port wire $0\cap6m[0:0].
  removing unused non-port wire $0\cap3m[0:0].
  removing unused non-port wire $0\cap1m[0:0].
  removing unused non-port wire $0\cap12m[0:0].
  removing unused non-port wire $0\Cap_count[12:0].
Removed 34 unused cells and 34 unused wires.

2.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.12.9. Rerunning OPT passes. (Maybe there is more to do..)

2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \main..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $flatten\capRam.$procmux$678 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$681 (pure)
    Root of a mux tree: $flatten\capRam.$procmux$684 (pure)
    Root of a mux tree: $procmux$520 (pure)
    Root of a mux tree: $procmux$527 (pure)
    Root of a mux tree: $procmux$634
    Root of a mux tree: $procmux$645 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \main.
Performed a total of 0 changes.

2.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.12.13. Executing OPT_DFF pass (perform DFF optimizations).

2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..

2.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.12.16. Finished OPT passes. (There is nothing left to do.)

2.13. Executing WREDUCE pass (reducing word size of cells).
Removed top 19 address bits (of 32) from memory init port main.$flatten\capRam.$meminit$\mem1$main.v:21$12 (capRam.mem1).
Removed top 30 address bits (of 32) from memory read port main.$memrd$\cmdbuf$main.v:238$57 (cmdbuf).
Removed top 30 address bits (of 32) from memory read port main.$memrd$\cmdbuf$main.v:243$58 (cmdbuf).
Removed top 31 bits (of 32) from port B of cell main.$add$main.v:220$55 ($add).
Removed top 19 bits (of 32) from port Y of cell main.$add$main.v:220$55 ($add).
Removed top 31 bits (of 32) from port B of cell main.$add$main.v:272$62 ($add).
Removed top 26 bits (of 32) from port Y of cell main.$add$main.v:272$62 ($add).
Removed cell main.$flatten\capRam.$procmux$684 ($mux).
Removed cell main.$flatten\capRam.$procmux$681 ($mux).
Removed top 7 bits (of 8) from port B of cell main.$procmux$600_CMP0 ($eq).
Removed top 7 bits (of 8) from port B of cell main.$procmux$602_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell main.$procmux$608_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell main.$procmux$617_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell main.$procmux$627_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell main.$procmux$642_CMP0 ($eq).
Removed top 7 bits (of 8) from FF cell main.$auto$ff.cc:262:slice$801 ($dffe).
Removed top 31 bits (of 32) from port B of cell main.$flatten\SPIPHY.$add$main.v:93$49 ($add).
Removed top 19 bits (of 32) from port Y of cell main.$flatten\SPIPHY.$add$main.v:93$49 ($add).
Removed top 19 bits (of 32) from wire main.$add$main.v:220$55_Y.

2.14. Executing PEEPOPT pass (run peephole optimizers).

2.15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
  removing unused non-port wire $flatten\capRam.$0$memwr$\mem1$main.v:32$2_DATA[7:0]$7.
  removing unused non-port wire $flatten\capRam.$0$memwr$\mem1$main.v:32$2_ADDR[12:0]$6.
  removing unused non-port wire $flatten\SPIPHY.$add$main.v:93$49_Y.
  removing unused non-port wire $auto$wreduce.cc:454:run$802.
Removed 0 unused cells and 4 unused wires.

2.16. Executing SHARE pass (SAT-based resource sharing).

2.17. Executing TECHMAP pass (map to technology primitives).

2.17.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

2.17.2. Continuing TECHMAP pass.
Cell type mappings to use:
    $ge: _90_lut_cmp_
    $gt: _90_lut_cmp_
    $le: _90_lut_cmp_
    $lt: _90_lut_cmp_

No more expansions possible.

2.18. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..

2.20. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module main:
  creating $macc model for $add$main.v:220$55 ($add).
  creating $macc model for $add$main.v:272$62 ($add).
  creating $macc model for $flatten\SPIPHY.$add$main.v:93$49 ($add).
  creating $alu model for $macc $flatten\SPIPHY.$add$main.v:93$49.
  creating $alu model for $macc $add$main.v:272$62.
  creating $alu model for $macc $add$main.v:220$55.
  creating $alu cell for $add$main.v:220$55: $auto$alumacc.cc:485:replace_alu$804
  creating $alu cell for $add$main.v:272$62: $auto$alumacc.cc:485:replace_alu$807
  creating $alu cell for $flatten\SPIPHY.$add$main.v:93$49: $auto$alumacc.cc:485:replace_alu$810
  created 3 $alu and 0 $macc cells.

2.21. Executing OPT pass (performing simple optimizations).

2.21.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.21.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \main..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $flatten\capRam.$procmux$678 (pure)
    Root of a mux tree: $procmux$520 (pure)
    Root of a mux tree: $procmux$527 (pure)
    Root of a mux tree: $procmux$634
    Root of a mux tree: $procmux$645 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \main.
Performed a total of 0 changes.

2.21.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.21.6. Executing OPT_DFF pass (perform DFF optimizations).

2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..

2.21.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.21.9. Finished OPT passes. (There is nothing left to do.)

2.22. Executing MEMORY pass.

2.22.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 1 transformations.

2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing main.capRam.mem1 write port 0.

2.22.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\capRam.mem1'[0] in module `\main': merging output FF to cell.

2.22.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
  removing unused `$dffe' cell `$auto$ff.cc:262:slice$801'.
  removing unused non-port wire $memrd$\cmdbuf$main.v:243$58_DATA.
  removing unused non-port wire $memrd$\cmdbuf$main.v:238$57_DATA.
  removing unused non-port wire $ffmerge_disconnected$814.
Removed 1 unused cells and 3 unused wires.

2.22.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

2.22.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

2.22.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..

2.22.9. Executing MEMORY_COLLECT pass (generating $mem cells).

2.23. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..

2.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
Processing main.capRam.mem1:
  Properties: ports=2 bits=65536 rports=1 wports=1 dbits=8 abits=13 words=8192
  Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1):
    Bram geometry: abits=8 dbits=16 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50
    Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted.
    Mapping to bram type $__ICE40_RAM4K_M0 (variant 1):
      Write port #0 is in clock domain \CLK.
        Mapped to bram port B1.
      Read port #0 is in clock domain \SCK.
        Mapped to bram port A1.1.
      Updated properties: dups=1 waste=2048 efficiency=50
      Storing for later selection.
  Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1):
    Bram geometry: abits=8 dbits=16 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50
    Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
  Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1):
    Bram geometry: abits=8 dbits=16 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50
    Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met.
  Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1):
    Bram geometry: abits=9 dbits=8 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
    Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 1):
      Write port #0 is in clock domain \CLK.
        Mapped to bram port B1.
      Read port #0 is in clock domain \SCK.
        Mapped to bram port A1.1.
      Updated properties: dups=1 waste=0 efficiency=100
      Storing for later selection.
  Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2):
    Bram geometry: abits=10 dbits=4 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
    Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 2):
      Write port #0 is in clock domain \CLK.
        Mapped to bram port B1.
      Read port #0 is in clock domain \SCK.
        Mapped to bram port A1.1.
      Updated properties: dups=1 waste=0 efficiency=100
      Storing for later selection.
  Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3):
    Bram geometry: abits=11 dbits=2 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
    Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 3):
      Write port #0 is in clock domain \CLK.
        Mapped to bram port B1.
      Read port #0 is in clock domain \SCK.
        Mapped to bram port A1.1.
      Updated properties: dups=1 waste=0 efficiency=100
      Storing for later selection.
  Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1):
    Bram geometry: abits=9 dbits=8 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
    Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
  Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2):
    Bram geometry: abits=10 dbits=4 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
    Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
  Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3):
    Bram geometry: abits=11 dbits=2 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
    Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
  Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1):
    Bram geometry: abits=9 dbits=8 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
    Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met.
  Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2):
    Bram geometry: abits=10 dbits=4 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
    Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met.
  Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3):
    Bram geometry: abits=11 dbits=2 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
    Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met.
  Selecting best of 4 rules:
    Efficiency for rule 4.3: efficiency=100, cells=16, acells=4
    Efficiency for rule 4.2: efficiency=100, cells=16, acells=8
    Efficiency for rule 4.1: efficiency=100, cells=16, acells=16
    Efficiency for rule 1.1: efficiency=50, cells=32, acells=32
    Selected rule 4.3 with efficiency 100.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 3):
      Write port #0 is in clock domain \CLK.
        Mapped to bram port B1.
      Read port #0 is in clock domain \SCK.
        Mapped to bram port A1.1.
      Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: capRam.mem1.0.0.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <0 1 0>: capRam.mem1.0.1.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <0 2 0>: capRam.mem1.0.2.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <0 3 0>: capRam.mem1.0.3.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <1 0 0>: capRam.mem1.1.0.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <1 1 0>: capRam.mem1.1.1.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <1 2 0>: capRam.mem1.1.2.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <1 3 0>: capRam.mem1.1.3.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <2 0 0>: capRam.mem1.2.0.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <2 1 0>: capRam.mem1.2.1.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <2 2 0>: capRam.mem1.2.2.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <2 3 0>: capRam.mem1.2.3.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <3 0 0>: capRam.mem1.3.0.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <3 1 0>: capRam.mem1.3.1.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <3 2 0>: capRam.mem1.3.2.0
      Creating $__ICE40_RAM4K_M123 cell at grid position <3 3 0>: capRam.mem1.3.3.0

2.25. Executing TECHMAP pass (map to technology primitives).

2.25.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/brams_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_RAM4K'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'.
Successfully finished Verilog frontend.

2.25.2. Continuing TECHMAP pass.
Cell type mappings to use:
    $__ICE40_RAM4K: \$__ICE40_RAM4K
    $__ICE40_RAM4K_M0: \$__ICE40_RAM4K_M0
    $__ICE40_RAM4K_M123: \$__ICE40_RAM4K_M123

Parameter \CFG_ABITS = 11
Parameter \CFG_DBITS = 2
Parameter \CLKPOL2 = 1
Parameter \CLKPOL3 = 1
Parameter \INIT = 4096'x

2.25.3. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
Parameter \CFG_ABITS = 11
Parameter \CFG_DBITS = 2
Parameter \CLKPOL2 = 1
Parameter \CLKPOL3 = 1
Parameter \INIT = 4096'x
Generating RTLIL representation for module `$paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123'.

2.25.4. Continuing TECHMAP pass.
Using template $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123 for cells of type $__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.2.3.0 ($__ICE40_RAM4K_M123) using $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123.
Parameter \CFG_ABITS = 11
Parameter \CFG_DBITS = 2
Parameter \CLKPOL2 = 1
Parameter \CLKPOL3 = 1
Parameter \INIT = 4096'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11

2.25.5. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K_M123'.
Parameter \CFG_ABITS = 11
Parameter \CFG_DBITS = 2
Parameter \CLKPOL2 = 1
Parameter \CLKPOL3 = 1
Parameter \INIT = 4096'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11
Generating RTLIL representation for module `$paramod$bfffde337fca5c335e56add59c90f0e763cbe355\$__ICE40_RAM4K_M123'.

2.25.6. Continuing TECHMAP pass.
Using template $paramod$bfffde337fca5c335e56add59c90f0e763cbe355\$__ICE40_RAM4K_M123 for cells of type $__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.0.0.0 ($__ICE40_RAM4K_M123) using $paramod$bfffde337fca5c335e56add59c90f0e763cbe355\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.1.1.0 ($__ICE40_RAM4K_M123) using $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.0.1.0 ($__ICE40_RAM4K_M123) using $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.3.3.0 ($__ICE40_RAM4K_M123) using $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.1.0.0 ($__ICE40_RAM4K_M123) using $paramod$bfffde337fca5c335e56add59c90f0e763cbe355\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.1.3.0 ($__ICE40_RAM4K_M123) using $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.2.1.0 ($__ICE40_RAM4K_M123) using $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.0.3.0 ($__ICE40_RAM4K_M123) using $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.2.2.0 ($__ICE40_RAM4K_M123) using $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.0.2.0 ($__ICE40_RAM4K_M123) using $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.2.0.0 ($__ICE40_RAM4K_M123) using $paramod$bfffde337fca5c335e56add59c90f0e763cbe355\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.3.2.0 ($__ICE40_RAM4K_M123) using $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.3.1.0 ($__ICE40_RAM4K_M123) using $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.1.2.0 ($__ICE40_RAM4K_M123) using $paramod$feb134910fde09087577f274dd7228fe583d4853\$__ICE40_RAM4K_M123.
Mapping main.capRam.mem1.3.0.0 ($__ICE40_RAM4K_M123) using $paramod$bfffde337fca5c335e56add59c90f0e763cbe355\$__ICE40_RAM4K_M123.
Parameter \READ_MODE = 3
Parameter \WRITE_MODE = 3
Parameter \NEGCLK_R = 1'0
Parameter \NEGCLK_W = 1'0
Parameter \INIT_0 = 256'x
Parameter \INIT_1 = 256'x
Parameter \INIT_2 = 256'x
Parameter \INIT_3 = 256'x
Parameter \INIT_4 = 256'x
Parameter \INIT_5 = 256'x
Parameter \INIT_6 = 256'x
Parameter \INIT_7 = 256'x
Parameter \INIT_8 = 256'x
Parameter \INIT_9 = 256'x
Parameter \INIT_A = 256'x
Parameter \INIT_B = 256'x
Parameter \INIT_C = 256'x
Parameter \INIT_D = 256'x
Parameter \INIT_E = 256'x
Parameter \INIT_F = 256'x

2.25.7. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
Parameter \READ_MODE = 3
Parameter \WRITE_MODE = 3
Parameter \NEGCLK_R = 1'0
Parameter \NEGCLK_W = 1'0
Parameter \INIT_0 = 256'x
Parameter \INIT_1 = 256'x
Parameter \INIT_2 = 256'x
Parameter \INIT_3 = 256'x
Parameter \INIT_4 = 256'x
Parameter \INIT_5 = 256'x
Parameter \INIT_6 = 256'x
Parameter \INIT_7 = 256'x
Parameter \INIT_8 = 256'x
Parameter \INIT_9 = 256'x
Parameter \INIT_A = 256'x
Parameter \INIT_B = 256'x
Parameter \INIT_C = 256'x
Parameter \INIT_D = 256'x
Parameter \INIT_E = 256'x
Parameter \INIT_F = 256'x
Generating RTLIL representation for module `$paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K'.

2.25.8. Continuing TECHMAP pass.
Using template $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K.
Mapping main.capRam.mem1.0.2.0 ($__ICE40_RAM4K) using $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K.
Parameter \READ_MODE = 3
Parameter \WRITE_MODE = 3
Parameter \NEGCLK_R = 1'0
Parameter \NEGCLK_W = 1'0
Parameter \INIT_0 = 256'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1xxxxxxx1
Parameter \INIT_1 = 256'x
Parameter \INIT_2 = 256'x
Parameter \INIT_3 = 256'x
Parameter \INIT_4 = 256'x
Parameter \INIT_5 = 256'x
Parameter \INIT_6 = 256'x
Parameter \INIT_7 = 256'x
Parameter \INIT_8 = 256'x
Parameter \INIT_9 = 256'x
Parameter \INIT_A = 256'x
Parameter \INIT_B = 256'x
Parameter \INIT_C = 256'x
Parameter \INIT_D = 256'x
Parameter \INIT_E = 256'x
Parameter \INIT_F = 256'x

2.25.9. Executing AST frontend in derive mode using pre-parsed AST for module `\$__ICE40_RAM4K'.
Parameter \READ_MODE = 3
Parameter \WRITE_MODE = 3
Parameter \NEGCLK_R = 1'0
Parameter \NEGCLK_W = 1'0
Parameter \INIT_0 = 256'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1xxxxxxx1
Parameter \INIT_1 = 256'x
Parameter \INIT_2 = 256'x
Parameter \INIT_3 = 256'x
Parameter \INIT_4 = 256'x
Parameter \INIT_5 = 256'x
Parameter \INIT_6 = 256'x
Parameter \INIT_7 = 256'x
Parameter \INIT_8 = 256'x
Parameter \INIT_9 = 256'x
Parameter \INIT_A = 256'x
Parameter \INIT_B = 256'x
Parameter \INIT_C = 256'x
Parameter \INIT_D = 256'x
Parameter \INIT_E = 256'x
Parameter \INIT_F = 256'x
Generating RTLIL representation for module `$paramod$1f8067780d1d867db01384302581930db7cedc45\$__ICE40_RAM4K'.

2.25.10. Continuing TECHMAP pass.
Using template $paramod$1f8067780d1d867db01384302581930db7cedc45\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K.
Mapping main.capRam.mem1.2.0.0 ($__ICE40_RAM4K) using $paramod$1f8067780d1d867db01384302581930db7cedc45\$__ICE40_RAM4K.
Mapping main.capRam.mem1.2.2.0 ($__ICE40_RAM4K) using $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K.
Mapping main.capRam.mem1.3.0.0 ($__ICE40_RAM4K) using $paramod$1f8067780d1d867db01384302581930db7cedc45\$__ICE40_RAM4K.
Mapping main.capRam.mem1.1.2.0 ($__ICE40_RAM4K) using $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K.
Mapping main.capRam.mem1.3.1.0 ($__ICE40_RAM4K) using $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K.
Mapping main.capRam.mem1.1.0.0 ($__ICE40_RAM4K) using $paramod$1f8067780d1d867db01384302581930db7cedc45\$__ICE40_RAM4K.
Mapping main.capRam.mem1.3.3.0 ($__ICE40_RAM4K) using $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K.
Mapping main.capRam.mem1.0.1.0 ($__ICE40_RAM4K) using $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K.
Mapping main.capRam.mem1.1.1.0 ($__ICE40_RAM4K) using $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K.
Mapping main.capRam.mem1.0.0.0 ($__ICE40_RAM4K) using $paramod$1f8067780d1d867db01384302581930db7cedc45\$__ICE40_RAM4K.
Mapping main.capRam.mem1.0.3.0 ($__ICE40_RAM4K) using $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K.
Mapping main.capRam.mem1.2.3.0 ($__ICE40_RAM4K) using $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K.
Mapping main.capRam.mem1.3.2.0 ($__ICE40_RAM4K) using $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K.
Mapping main.capRam.mem1.2.1.0 ($__ICE40_RAM4K) using $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K.
Mapping main.capRam.mem1.1.3.0 ($__ICE40_RAM4K) using $paramod$b1ffe55f5fa8329a5f133f9d30887752dd43bf48\$__ICE40_RAM4K.
No more expansions possible.

2.26. Executing ICE40_BRAMINIT pass.

2.27. Executing OPT pass (performing simple optimizations).

2.27.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.
Setting undriven signal in main to constant: $techmap1032\capRam.mem1.1.3.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1031\capRam.mem1.2.1.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1030\capRam.mem1.3.2.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1029\capRam.mem1.2.3.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1028\capRam.mem1.0.3.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1027\capRam.mem1.0.0.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1026\capRam.mem1.1.1.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1025\capRam.mem1.0.1.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1024\capRam.mem1.3.3.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1023\capRam.mem1.1.0.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1022\capRam.mem1.3.1.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1021\capRam.mem1.1.2.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1020\capRam.mem1.3.0.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1019\capRam.mem1.2.2.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1018\capRam.mem1.2.0.0.MASK = 16'x
Setting undriven signal in main to constant: $techmap1017\capRam.mem1.0.2.0.MASK = 16'x
Setting undriven signal in main to constant: \SPIPHY.BYTE_2HOST [7:1] = 7'x
Setting undriven signal in main to constant: $techmap1016\capRam.mem1.3.0.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1016\capRam.mem1.3.0.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1016\capRam.mem1.3.0.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1015\capRam.mem1.1.2.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1015\capRam.mem1.1.2.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1015\capRam.mem1.1.2.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1000\capRam.mem1.2.3.0.B1DATA_16 [10] = 1'x
Setting undriven signal in main to constant: $techmap1014\capRam.mem1.3.1.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1014\capRam.mem1.3.1.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1014\capRam.mem1.3.1.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1000\capRam.mem1.2.3.0.B1DATA_16 [5] = 1'x
Setting undriven signal in main to constant: $techmap1003\capRam.mem1.1.1.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1003\capRam.mem1.1.1.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1003\capRam.mem1.1.1.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1013\capRam.mem1.3.2.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1013\capRam.mem1.3.2.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1013\capRam.mem1.3.2.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1012\capRam.mem1.2.0.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1012\capRam.mem1.2.0.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1012\capRam.mem1.2.0.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1000\capRam.mem1.2.3.0.B1DATA_16 [14] = 1'x
Setting undriven signal in main to constant: $techmap1004\capRam.mem1.0.1.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1000\capRam.mem1.2.3.0.B1DATA_16 [15] = 1'x
Setting undriven signal in main to constant: $techmap1011\capRam.mem1.0.2.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1011\capRam.mem1.0.2.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1011\capRam.mem1.0.2.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1005\capRam.mem1.3.3.0.B1DATA_16 [10:8] = 3'x
Setting undriven signal in main to constant: $techmap1005\capRam.mem1.3.3.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1010\capRam.mem1.2.2.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1010\capRam.mem1.2.2.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1010\capRam.mem1.2.2.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1000\capRam.mem1.2.3.0.B1DATA_16 [7] = 1'x
Setting undriven signal in main to constant: $techmap1004\capRam.mem1.0.1.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1004\capRam.mem1.0.1.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1000\capRam.mem1.2.3.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1000\capRam.mem1.2.3.0.B1DATA_16 [4] = 1'x
Setting undriven signal in main to constant: $techmap1009\capRam.mem1.0.3.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1009\capRam.mem1.0.3.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1009\capRam.mem1.0.3.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1000\capRam.mem1.2.3.0.B1DATA_16 [13] = 1'x
Setting undriven signal in main to constant: $techmap1000\capRam.mem1.2.3.0.B1DATA_16 [12] = 1'x
Setting undriven signal in main to constant: $techmap1008\capRam.mem1.2.1.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1008\capRam.mem1.2.1.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1008\capRam.mem1.2.1.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1002\capRam.mem1.0.0.0.B1DATA_16 [10:9] = 2'x
Setting undriven signal in main to constant: $techmap1002\capRam.mem1.0.0.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1000\capRam.mem1.2.3.0.B1DATA_16 [8] = 1'x
Setting undriven signal in main to constant: $techmap1005\capRam.mem1.3.3.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1005\capRam.mem1.3.3.0.B1DATA_16 [7:4] = 4'x
Setting undriven signal in main to constant: $techmap1007\capRam.mem1.1.3.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1007\capRam.mem1.1.3.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1007\capRam.mem1.1.3.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1000\capRam.mem1.2.3.0.B1DATA_16 [9] = 1'x
Setting undriven signal in main to constant: $techmap1002\capRam.mem1.0.0.0.B1DATA_16 [0] = 1'x
Setting undriven signal in main to constant: $techmap1006\capRam.mem1.1.0.0.B1DATA_16 [2:0] = 3'x
Setting undriven signal in main to constant: $techmap1006\capRam.mem1.1.0.0.B1DATA_16 [10:4] = 7'x
Setting undriven signal in main to constant: $techmap1006\capRam.mem1.1.0.0.B1DATA_16 [15:12] = 4'x
Setting undriven signal in main to constant: $techmap1000\capRam.mem1.2.3.0.B1DATA_16 [6] = 1'x
Setting undriven signal in main to constant: $techmap1002\capRam.mem1.0.0.0.B1DATA_16 [2:1] = 2'x
Setting undriven signal in main to constant: $techmap1002\capRam.mem1.0.0.0.B1DATA_16 [8:4] = 5'x
Replacing $mux cell `$flatten\capRam.$procmux$678' (mux_sel01) in module `\main' with constant driver `$flatten\capRam.$0$memwr$\mem1$main.v:32$2_EN[7:0]$8 [7] = \cap_wr_ce'.
Replacing $reduce_or cell `$techmap$techmap1011\capRam.mem1.0.2.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1011\capRam.mem1.0.2.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y = $auto$rtlil.cc:2443:Mux$848'.
Replacing $eq cell `$auto$memory_bram.cc:931:replace_memory$955' in module `main' with $logic_not.
Replacing $reduce_or cell `$techmap$techmap1016\capRam.mem1.3.0.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$1001' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1016\capRam.mem1.3.0.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$1001_Y = $auto$rtlil.cc:2443:Mux$958'.
Replacing $reduce_or cell `$techmap$techmap1015\capRam.mem1.1.2.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1015\capRam.mem1.1.2.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y = $auto$rtlil.cc:2443:Mux$892'.
Replacing $reduce_or cell `$techmap$techmap1014\capRam.mem1.3.1.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1014\capRam.mem1.3.1.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y = $auto$rtlil.cc:2443:Mux$969'.
Replacing $eq cell `$auto$memory_bram.cc:931:replace_memory$816' in module `main' with $logic_not.
Replacing $eq cell `$procmux$602_CMP0' (8'x, 1'1) in module `\main' with constant driver `$procmux$602_CMP = 1'x'.
Replacing $eq cell `$procmux$627_CMP0' (8'x, 4'1100) in module `\main' with constant driver `$procmux$627_CMP = 1'x'.
Replacing $eq cell `$auto$memory_bram.cc:931:replace_memory$823' in module `main' with $logic_not.
Replacing $eq cell `$auto$memory_bram.cc:931:replace_memory$867' in module `main' with $logic_not.
Replacing $reduce_or cell `$techmap$techmap1006\capRam.mem1.1.0.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$1001' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1006\capRam.mem1.1.0.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$1001_Y = $auto$rtlil.cc:2443:Mux$870'.
Optimized away 1 select inputs of $pmux cell `$auto$memory_bram.cc:1005:replace_memory$992' in module `main'.
Optimized away 1 select inputs of $pmux cell `$auto$memory_bram.cc:1005:replace_memory$993' in module `main'.
Optimized away 1 select inputs of $pmux cell `$auto$memory_bram.cc:1005:replace_memory$994' in module `main'.
Optimized away 1 select inputs of $pmux cell `$auto$memory_bram.cc:1005:replace_memory$995' in module `main'.
Replacing $eq cell `$auto$memory_bram.cc:931:replace_memory$904' in module `main' with $logic_not.
Replacing $reduce_or cell `$techmap$techmap1005\capRam.mem1.3.3.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1005\capRam.mem1.3.3.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y = $auto$rtlil.cc:2443:Mux$991'.
Replacing $eq cell `$auto$memory_bram.cc:931:replace_memory$860' in module `main' with $logic_not.
Replacing $reduce_or cell `$techmap$techmap1004\capRam.mem1.0.1.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1004\capRam.mem1.0.1.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y = $auto$rtlil.cc:2443:Mux$837'.
Replacing $reduce_or cell `$techmap$techmap1003\capRam.mem1.1.1.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1003\capRam.mem1.1.1.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y = $auto$rtlil.cc:2443:Mux$881'.
Replacing $reduce_or cell `$techmap$techmap1002\capRam.mem1.0.0.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$1001' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1002\capRam.mem1.0.0.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$1001_Y = $auto$rtlil.cc:2443:Mux$826'.
Replacing $reduce_or cell `$techmap$techmap1009\capRam.mem1.0.3.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1009\capRam.mem1.0.3.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y = $auto$rtlil.cc:2443:Mux$859'.
Replacing $reduce_or cell `$techmap$techmap1000\capRam.mem1.2.3.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1000\capRam.mem1.2.3.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y = $auto$rtlil.cc:2443:Mux$947'.
Replacing $eq cell `$procmux$600_CMP0' (8'x, 1'1) in module `\main' with constant driver `$procmux$600_CMP = 1'x'.
Replacing $eq cell `$procmux$608_CMP0' (8'x, 2'11) in module `\main' with constant driver `$procmux$608_CMP = 1'x'.
Replacing $eq cell `$procmux$617_CMP0' (8'x, 3'110) in module `\main' with constant driver `$procmux$617_CMP = 1'x'.
Replacing $eq cell `$procmux$642_CMP0' (8'x, 5'11000) in module `\main' with constant driver `$procmux$642_CMP = 1'x'.
Replacing $mux cell `$procmux$641' (x) in module `\main' with constant driver `$procmux$641_Y = $procmux$634_Y'.
Replacing $mux cell `$procmux$643' (x) in module `\main' with constant driver `$procmux$643_Y = $procmux$634_Y'.
Replacing $mux cell `$procmux$645' (?) in module `\main' with constant driver `$0\cap24m[0:0] = $procmux$634_Y'.
Replacing $reduce_or cell `$techmap$techmap1013\capRam.mem1.3.2.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1013\capRam.mem1.3.2.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y = $auto$rtlil.cc:2443:Mux$980'.
Replacing $reduce_or cell `$techmap$techmap1010\capRam.mem1.2.2.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1010\capRam.mem1.2.2.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y = $auto$rtlil.cc:2443:Mux$936'.
Replacing $eq cell `$auto$memory_bram.cc:931:replace_memory$911' in module `main' with $logic_not.
Replacing $reduce_or cell `$techmap$techmap1012\capRam.mem1.2.0.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$1001' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1012\capRam.mem1.2.0.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$1001_Y = $auto$rtlil.cc:2443:Mux$914'.
Replacing $eq cell `$auto$memory_bram.cc:931:replace_memory$948' in module `main' with $logic_not.
Replacing $reduce_or cell `$techmap$techmap1008\capRam.mem1.2.1.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1008\capRam.mem1.2.1.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y = $auto$rtlil.cc:2443:Mux$925'.
Replacing $reduce_or cell `$techmap$techmap1007\capRam.mem1.1.3.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999' (and_or_buffer) in module `\main' with constant driver `$techmap$techmap1007\capRam.mem1.1.3.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y = $auto$rtlil.cc:2443:Mux$903'.
Replacing $reduce_and cell `$auto$opt_dff.cc:223:make_patterns_logic$779' (const_and) in module `\main' with constant driver `$auto$opt_dff.cc:222:make_patterns_logic$778 = 1'0'.
Replacing $reduce_and cell `$auto$opt_dff.cc:223:make_patterns_logic$770' (const_and) in module `\main' with constant driver `$auto$opt_dff.cc:222:make_patterns_logic$769 = 1'0'.
Replacing $reduce_and cell `$auto$opt_dff.cc:223:make_patterns_logic$776' (const_and) in module `\main' with constant driver `$auto$opt_dff.cc:222:make_patterns_logic$775 = 1'0'.
Replacing $reduce_and cell `$auto$opt_dff.cc:223:make_patterns_logic$773' (const_and) in module `\main' with constant driver `$auto$opt_dff.cc:222:make_patterns_logic$772 = 1'0'.

2.27.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$937' is identical to cell `$auto$memory_bram.cc:931:replace_memory$981'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$938 = $auto$rtlil.cc:2384:Eq$982
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$937' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$922' is identical to cell `$auto$memory_bram.cc:931:replace_memory$966'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$923 = $auto$rtlil.cc:2384:Eq$967
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$922' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$915' is identical to cell `$auto$memory_bram.cc:931:replace_memory$959'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$916 = $auto$rtlil.cc:2384:Eq$960
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$915' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$911' is identical to cell `$auto$memory_bram.cc:931:replace_memory$955'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$912 = $auto$rtlil.cc:2384:Eq$956
    Removing $logic_not cell `$auto$memory_bram.cc:931:replace_memory$911' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$904' is identical to cell `$auto$memory_bram.cc:931:replace_memory$948'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$905 = $auto$rtlil.cc:2384:Eq$949
    Removing $logic_not cell `$auto$memory_bram.cc:931:replace_memory$904' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$900' is identical to cell `$auto$memory_bram.cc:931:replace_memory$944'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$901 = $auto$rtlil.cc:2384:Eq$945
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$900' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$893' is identical to cell `$auto$memory_bram.cc:931:replace_memory$981'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$894 = $auto$rtlil.cc:2384:Eq$982
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$893' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$889' is identical to cell `$auto$memory_bram.cc:931:replace_memory$933'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$890 = $auto$rtlil.cc:2384:Eq$934
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$889' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$882' is identical to cell `$auto$memory_bram.cc:931:replace_memory$926'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$883 = $auto$rtlil.cc:2384:Eq$927
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$882' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$878' is identical to cell `$auto$memory_bram.cc:931:replace_memory$966'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$879 = $auto$rtlil.cc:2384:Eq$967
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$878' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$871' is identical to cell `$auto$memory_bram.cc:931:replace_memory$959'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$872 = $auto$rtlil.cc:2384:Eq$960
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$871' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$867' is identical to cell `$auto$memory_bram.cc:931:replace_memory$955'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$868 = $auto$rtlil.cc:2384:Eq$956
    Removing $logic_not cell `$auto$memory_bram.cc:931:replace_memory$867' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$860' is identical to cell `$auto$memory_bram.cc:931:replace_memory$948'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$861 = $auto$rtlil.cc:2384:Eq$949
    Removing $logic_not cell `$auto$memory_bram.cc:931:replace_memory$860' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$856' is identical to cell `$auto$memory_bram.cc:931:replace_memory$944'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$857 = $auto$rtlil.cc:2384:Eq$945
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$856' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$849' is identical to cell `$auto$memory_bram.cc:931:replace_memory$981'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$850 = $auto$rtlil.cc:2384:Eq$982
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$849' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$845' is identical to cell `$auto$memory_bram.cc:931:replace_memory$933'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$846 = $auto$rtlil.cc:2384:Eq$934
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$845' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$838' is identical to cell `$auto$memory_bram.cc:931:replace_memory$926'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$839 = $auto$rtlil.cc:2384:Eq$927
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$838' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$834' is identical to cell `$auto$memory_bram.cc:931:replace_memory$966'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$835 = $auto$rtlil.cc:2384:Eq$967
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$834' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$827' is identical to cell `$auto$memory_bram.cc:931:replace_memory$959'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$828 = $auto$rtlil.cc:2384:Eq$960
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$827' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$823' is identical to cell `$auto$memory_bram.cc:931:replace_memory$955'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$824 = $auto$rtlil.cc:2384:Eq$956
    Removing $logic_not cell `$auto$memory_bram.cc:931:replace_memory$823' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$816' is identical to cell `$auto$memory_bram.cc:931:replace_memory$948'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$817 = $auto$rtlil.cc:2384:Eq$949
    Removing $logic_not cell `$auto$memory_bram.cc:931:replace_memory$816' from module `\main'.
  Cell `$auto$ff.cc:262:slice$771' is identical to cell `$auto$ff.cc:262:slice$768'.
    Redirecting output \Q: \cap3m = \cap1m
    Removing $dffe cell `$auto$ff.cc:262:slice$771' from module `\main'.
  Cell `$auto$ff.cc:262:slice$774' is identical to cell `$auto$ff.cc:262:slice$768'.
    Redirecting output \Q: \cap6m = \cap1m
    Removing $dffe cell `$auto$ff.cc:262:slice$774' from module `\main'.
  Cell `$auto$ff.cc:262:slice$777' is identical to cell `$auto$ff.cc:262:slice$768'.
    Redirecting output \Q: \cap12m = \cap1m
    Removing $dffe cell `$auto$ff.cc:262:slice$777' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$970' is identical to cell `$auto$memory_bram.cc:931:replace_memory$926'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$971 = $auto$rtlil.cc:2384:Eq$927
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$970' from module `\main'.
  Cell `$auto$memory_bram.cc:978:replace_memory$974' is identical to cell `$auto$memory_bram.cc:978:replace_memory$930'.
    Redirecting output \Q: $auto$memory_bram.cc:977:replace_memory$973 = $auto$memory_bram.cc:977:replace_memory$929
    Removing $dffe cell `$auto$memory_bram.cc:978:replace_memory$974' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$977' is identical to cell `$auto$memory_bram.cc:931:replace_memory$933'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$978 = $auto$rtlil.cc:2384:Eq$934
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$977' from module `\main'.
  Cell `$auto$memory_bram.cc:931:replace_memory$988' is identical to cell `$auto$memory_bram.cc:931:replace_memory$944'.
    Redirecting output \Y: $auto$rtlil.cc:2384:Eq$989 = $auto$rtlil.cc:2384:Eq$945
    Removing $eq cell `$auto$memory_bram.cc:931:replace_memory$988' from module `\main'.
  Cell `$auto$memory_bram.cc:978:replace_memory$963' is identical to cell `$auto$memory_bram.cc:978:replace_memory$919'.
    Redirecting output \Q: $auto$memory_bram.cc:977:replace_memory$962 = $auto$memory_bram.cc:977:replace_memory$918
    Removing $dffe cell `$auto$memory_bram.cc:978:replace_memory$963' from module `\main'.
  Cell `$auto$memory_bram.cc:987:replace_memory$986' is identical to cell `$auto$memory_bram.cc:987:replace_memory$898'.
    Redirecting output \Y: $auto$rtlil.cc:2376:And$987 = $auto$rtlil.cc:2376:And$899
    Removing $and cell `$auto$memory_bram.cc:987:replace_memory$986' from module `\main'.
  Cell `$auto$memory_bram.cc:957:replace_memory$891' is identical to cell `$auto$memory_bram.cc:957:replace_memory$979'.
    Redirecting output \Y: $auto$rtlil.cc:2443:Mux$892 = $auto$rtlil.cc:2443:Mux$980
    Removing $mux cell `$auto$memory_bram.cc:957:replace_memory$891' from module `\main'.
  Cell `$auto$memory_bram.cc:957:replace_memory$957' is identical to cell `$auto$memory_bram.cc:957:replace_memory$913'.
    Redirecting output \Y: $auto$rtlil.cc:2443:Mux$958 = $auto$rtlil.cc:2443:Mux$914
    Removing $mux cell `$auto$memory_bram.cc:957:replace_memory$957' from module `\main'.
  Cell `$auto$memory_bram.cc:987:replace_memory$953' is identical to cell `$auto$memory_bram.cc:987:replace_memory$909'.
    Redirecting output \Y: $auto$rtlil.cc:2376:And$954 = $auto$rtlil.cc:2376:And$910
    Removing $and cell `$auto$memory_bram.cc:987:replace_memory$953' from module `\main'.
  Cell `$auto$memory_bram.cc:987:replace_memory$876' is identical to cell `$auto$memory_bram.cc:987:replace_memory$964'.
    Redirecting output \Y: $auto$rtlil.cc:2376:And$877 = $auto$rtlil.cc:2376:And$965
    Removing $and cell `$auto$memory_bram.cc:987:replace_memory$876' from module `\main'.
  Cell `$auto$memory_bram.cc:978:replace_memory$875' is identical to cell `$auto$memory_bram.cc:978:replace_memory$919'.
    Redirecting output \Q: $auto$memory_bram.cc:977:replace_memory$874 = $auto$memory_bram.cc:977:replace_memory$918
    Removing $dffe cell `$auto$memory_bram.cc:978:replace_memory$875' from module `\main'.
  Cell `$auto$memory_bram.cc:978:replace_memory$952' is identical to cell `$auto$memory_bram.cc:978:replace_memory$908'.
    Redirecting output \Q: $auto$memory_bram.cc:977:replace_memory$951 = $auto$memory_bram.cc:977:replace_memory$907
    Removing $dffe cell `$auto$memory_bram.cc:978:replace_memory$952' from module `\main'.
  Cell `$auto$memory_bram.cc:957:replace_memory$869' is identical to cell `$auto$memory_bram.cc:957:replace_memory$913'.
    Redirecting output \Y: $auto$rtlil.cc:2443:Mux$870 = $auto$rtlil.cc:2443:Mux$914
    Removing $mux cell `$auto$memory_bram.cc:957:replace_memory$869' from module `\main'.
  Cell `$auto$memory_bram.cc:987:replace_memory$865' is identical to cell `$auto$memory_bram.cc:987:replace_memory$909'.
    Redirecting output \Y: $auto$rtlil.cc:2376:And$866 = $auto$rtlil.cc:2376:And$910
    Removing $and cell `$auto$memory_bram.cc:987:replace_memory$865' from module `\main'.
  Cell `$auto$memory_bram.cc:978:replace_memory$864' is identical to cell `$auto$memory_bram.cc:978:replace_memory$908'.
    Redirecting output \Q: $auto$memory_bram.cc:977:replace_memory$863 = $auto$memory_bram.cc:977:replace_memory$907
    Removing $dffe cell `$auto$memory_bram.cc:978:replace_memory$864' from module `\main'.
  Cell `$auto$memory_bram.cc:957:replace_memory$858' is identical to cell `$auto$memory_bram.cc:957:replace_memory$902'.
    Redirecting output \Y: $auto$rtlil.cc:2443:Mux$859 = $auto$rtlil.cc:2443:Mux$903
    Removing $mux cell `$auto$memory_bram.cc:957:replace_memory$858' from module `\main'.
  Cell `$auto$memory_bram.cc:957:replace_memory$946' is identical to cell `$auto$memory_bram.cc:957:replace_memory$902'.
    Redirecting output \Y: $auto$rtlil.cc:2443:Mux$947 = $auto$rtlil.cc:2443:Mux$903
    Removing $mux cell `$auto$memory_bram.cc:957:replace_memory$946' from module `\main'.
  Cell `$auto$memory_bram.cc:987:replace_memory$854' is identical to cell `$auto$memory_bram.cc:987:replace_memory$898'.
    Redirecting output \Y: $auto$rtlil.cc:2376:And$855 = $auto$rtlil.cc:2376:And$899
    Removing $and cell `$auto$memory_bram.cc:987:replace_memory$854' from module `\main'.
  Cell `$auto$memory_bram.cc:978:replace_memory$853' is identical to cell `$auto$memory_bram.cc:978:replace_memory$897'.
    Redirecting output \Q: $auto$memory_bram.cc:977:replace_memory$852 = $auto$memory_bram.cc:977:replace_memory$896
    Removing $dffe cell `$auto$memory_bram.cc:978:replace_memory$853' from module `\main'.
  Cell `$auto$memory_bram.cc:957:replace_memory$847' is identical to cell `$auto$memory_bram.cc:957:replace_memory$979'.
    Redirecting output \Y: $auto$rtlil.cc:2443:Mux$848 = $auto$rtlil.cc:2443:Mux$980
    Removing $mux cell `$auto$memory_bram.cc:957:replace_memory$847' from module `\main'.
  Cell `$auto$memory_bram.cc:987:replace_memory$942' is identical to cell `$auto$memory_bram.cc:987:replace_memory$898'.
    Redirecting output \Y: $auto$rtlil.cc:2376:And$943 = $auto$rtlil.cc:2376:And$899
    Removing $and cell `$auto$memory_bram.cc:987:replace_memory$942' from module `\main'.
  Cell `$auto$memory_bram.cc:987:replace_memory$843' is identical to cell `$auto$memory_bram.cc:987:replace_memory$887'.
    Redirecting output \Y: $auto$rtlil.cc:2376:And$844 = $auto$rtlil.cc:2376:And$888
    Removing $and cell `$auto$memory_bram.cc:987:replace_memory$843' from module `\main'.
  Cell `$auto$memory_bram.cc:978:replace_memory$842' is identical to cell `$auto$memory_bram.cc:978:replace_memory$886'.
    Redirecting output \Q: $auto$memory_bram.cc:977:replace_memory$841 = $auto$memory_bram.cc:977:replace_memory$885
    Removing $dffe cell `$auto$memory_bram.cc:978:replace_memory$842' from module `\main'.
  Cell `$auto$memory_bram.cc:978:replace_memory$941' is identical to cell `$auto$memory_bram.cc:978:replace_memory$897'.
    Redirecting output \Q: $auto$memory_bram.cc:977:replace_memory$940 = $auto$memory_bram.cc:977:replace_memory$896
    Removing $dffe cell `$auto$memory_bram.cc:978:replace_memory$941' from module `\main'.
  Cell `$auto$memory_bram.cc:978:replace_memory$985' is identical to cell `$auto$memory_bram.cc:978:replace_memory$897'.
    Redirecting output \Q: $auto$memory_bram.cc:977:replace_memory$984 = $auto$memory_bram.cc:977:replace_memory$896
    Removing $dffe cell `$auto$memory_bram.cc:978:replace_memory$985' from module `\main'.
  Cell `$auto$memory_bram.cc:957:replace_memory$836' is identical to cell `$auto$memory_bram.cc:957:replace_memory$880'.
    Redirecting output \Y: $auto$rtlil.cc:2443:Mux$837 = $auto$rtlil.cc:2443:Mux$881
    Removing $mux cell `$auto$memory_bram.cc:957:replace_memory$836' from module `\main'.
  Cell `$auto$memory_bram.cc:987:replace_memory$832' is identical to cell `$auto$memory_bram.cc:987:replace_memory$964'.
    Redirecting output \Y: $auto$rtlil.cc:2376:And$833 = $auto$rtlil.cc:2376:And$965
    Removing $and cell `$auto$memory_bram.cc:987:replace_memory$832' from module `\main'.
  Cell `$auto$memory_bram.cc:978:replace_memory$831' is identical to cell `$auto$memory_bram.cc:978:replace_memory$919'.
    Redirecting output \Q: $auto$memory_bram.cc:977:replace_memory$830 = $auto$memory_bram.cc:977:replace_memory$918
    Removing $dffe cell `$auto$memory_bram.cc:978:replace_memory$831' from module `\main'.
  Cell `$auto$memory_bram.cc:957:replace_memory$825' is identical to cell `$auto$memory_bram.cc:957:replace_memory$913'.
    Redirecting output \Y: $auto$rtlil.cc:2443:Mux$826 = $auto$rtlil.cc:2443:Mux$914
    Removing $mux cell `$auto$memory_bram.cc:957:replace_memory$825' from module `\main'.
  Cell `$auto$memory_bram.cc:957:replace_memory$935' is identical to cell `$auto$memory_bram.cc:957:replace_memory$979'.
    Redirecting output \Y: $auto$rtlil.cc:2443:Mux$936 = $auto$rtlil.cc:2443:Mux$980
    Removing $mux cell `$auto$memory_bram.cc:957:replace_memory$935' from module `\main'.
  Cell `$auto$memory_bram.cc:987:replace_memory$821' is identical to cell `$auto$memory_bram.cc:987:replace_memory$909'.
    Redirecting output \Y: $auto$rtlil.cc:2376:And$822 = $auto$rtlil.cc:2376:And$910
    Removing $and cell `$auto$memory_bram.cc:987:replace_memory$821' from module `\main'.
  Cell `$auto$memory_bram.cc:978:replace_memory$820' is identical to cell `$auto$memory_bram.cc:978:replace_memory$908'.
    Redirecting output \Q: $auto$memory_bram.cc:977:replace_memory$819 = $auto$memory_bram.cc:977:replace_memory$907
    Removing $dffe cell `$auto$memory_bram.cc:978:replace_memory$820' from module `\main'.
  Cell `$auto$memory_bram.cc:987:replace_memory$931' is identical to cell `$auto$memory_bram.cc:987:replace_memory$887'.
    Redirecting output \Y: $auto$rtlil.cc:2376:And$932 = $auto$rtlil.cc:2376:And$888
    Removing $and cell `$auto$memory_bram.cc:987:replace_memory$931' from module `\main'.
  Cell `$auto$memory_bram.cc:978:replace_memory$930' is identical to cell `$auto$memory_bram.cc:978:replace_memory$886'.
    Redirecting output \Q: $auto$memory_bram.cc:977:replace_memory$929 = $auto$memory_bram.cc:977:replace_memory$885
    Removing $dffe cell `$auto$memory_bram.cc:978:replace_memory$930' from module `\main'.
  Cell `$auto$memory_bram.cc:987:replace_memory$975' is identical to cell `$auto$memory_bram.cc:987:replace_memory$887'.
    Redirecting output \Y: $auto$rtlil.cc:2376:And$976 = $auto$rtlil.cc:2376:And$888
    Removing $and cell `$auto$memory_bram.cc:987:replace_memory$975' from module `\main'.
  Cell `$auto$memory_bram.cc:957:replace_memory$924' is identical to cell `$auto$memory_bram.cc:957:replace_memory$880'.
    Redirecting output \Y: $auto$rtlil.cc:2443:Mux$925 = $auto$rtlil.cc:2443:Mux$881
    Removing $mux cell `$auto$memory_bram.cc:957:replace_memory$924' from module `\main'.
  Cell `$auto$memory_bram.cc:957:replace_memory$968' is identical to cell `$auto$memory_bram.cc:957:replace_memory$880'.
    Redirecting output \Y: $auto$rtlil.cc:2443:Mux$969 = $auto$rtlil.cc:2443:Mux$881
    Removing $mux cell `$auto$memory_bram.cc:957:replace_memory$968' from module `\main'.
  Cell `$auto$memory_bram.cc:957:replace_memory$990' is identical to cell `$auto$memory_bram.cc:957:replace_memory$902'.
    Redirecting output \Y: $auto$rtlil.cc:2443:Mux$991 = $auto$rtlil.cc:2443:Mux$903
    Removing $mux cell `$auto$memory_bram.cc:957:replace_memory$990' from module `\main'.
  Cell `$auto$memory_bram.cc:987:replace_memory$920' is identical to cell `$auto$memory_bram.cc:987:replace_memory$964'.
    Redirecting output \Y: $auto$rtlil.cc:2376:And$921 = $auto$rtlil.cc:2376:And$965
    Removing $and cell `$auto$memory_bram.cc:987:replace_memory$920' from module `\main'.
Removed a total of 63 cells.

2.27.3. Executing OPT_DFF pass (perform DFF optimizations).
Handling never-active EN on $auto$ff.cc:262:slice$768 ($dffe) from module main (removing D path).
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$768 ($dffe) from module main.

2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
  removing unused `\SB_RAM40_4K' cell `\capRam.mem1.2.0.0'.
  removing unused `\SB_RAM40_4K' cell `\capRam.mem1.3.1.0'.
  removing unused `\SB_RAM40_4K' cell `\capRam.mem1.1.2.0'.
  removing unused `$pmux' cell `$auto$memory_bram.cc:1005:replace_memory$992'.
  removing unused `$pmux' cell `$auto$memory_bram.cc:1005:replace_memory$993'.
  removing unused `$pmux' cell `$auto$memory_bram.cc:1005:replace_memory$994'.
  removing unused `$dffe' cell `$auto$memory_bram.cc:978:replace_memory$897'.
  removing unused `\SB_RAM40_4K' cell `\capRam.mem1.3.0.0'.
  removing unused `$sdff' cell `$auto$ff.cc:262:slice$797'.
  removing unused `$sdff' cell `$auto$ff.cc:262:slice$793'.
  removing unused `$sdff' cell `$auto$ff.cc:262:slice$789'.
  removing unused `$sdff' cell `$auto$ff.cc:262:slice$785'.
  removing unused `\SB_RAM40_4K' cell `\capRam.mem1.2.2.0'.
  removing unused `\SB_RAM40_4K' cell `\capRam.mem1.1.0.0'.
  removing unused `\SB_RAM40_4K' cell `\capRam.mem1.3.3.0'.
  removing unused `\SB_RAM40_4K' cell `\capRam.mem1.1.1.0'.
  removing unused `\SB_RAM40_4K' cell `\capRam.mem1.2.3.0'.
  removing unused `\SB_RAM40_4K' cell `\capRam.mem1.3.2.0'.
  removing unused `\SB_RAM40_4K' cell `\capRam.mem1.2.1.0'.
  removing unused `\SB_RAM40_4K' cell `\capRam.mem1.1.3.0'.
Warning: Driver-driver conflict for \cap12m between cell $auto$ff.cc:262:slice$785.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap6m between cell $auto$ff.cc:262:slice$789.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap3m between cell $auto$ff.cc:262:slice$793.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap1m between cell $auto$ff.cc:262:slice$797.Q and constant 1'0 in main: Resolved using constant.
  removing unused non-port wire $procmux$643_Y.
  removing unused non-port wire $procmux$642_CMP.
  removing unused non-port wire $procmux$641_Y.
  removing unused non-port wire $procmux$634_Y.
  removing unused non-port wire $procmux$627_CMP.
  removing unused non-port wire $procmux$617_CMP.
  removing unused non-port wire $procmux$608_CMP.
  removing unused non-port wire $procmux$602_CMP.
  removing unused non-port wire $procmux$600_CMP.
  removing unused non-port wire $flatten\capRam.$memrd$\mem1$main.v:26$4_DATA.
  removing unused non-port wire $flatten\capRam.$0$memwr$\mem1$main.v:32$2_EN[7:0]$8.
  removing unused non-port wire $auto$opt_dff.cc:222:make_patterns_logic$778.
  removing unused non-port wire $auto$opt_dff.cc:222:make_patterns_logic$775.
  removing unused non-port wire $auto$opt_dff.cc:222:make_patterns_logic$772.
  removing unused non-port wire $auto$opt_dff.cc:222:make_patterns_logic$769.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$852.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$861.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$862.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$863.
  removing unused non-port wire $auto$rtlil.cc:2376:And$866.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$868.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$870.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$872.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$873.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$874.
  removing unused non-port wire $auto$rtlil.cc:2376:And$877.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$879.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$881.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$883.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$884.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$885.
  removing unused non-port wire $auto$rtlil.cc:2376:And$888.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$890.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$892.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$894.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$895.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$896.
  removing unused non-port wire $auto$rtlil.cc:2376:And$899.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$901.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$903.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$905.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$906.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$907.
  removing unused non-port wire $auto$rtlil.cc:2376:And$910.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$912.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$914.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$916.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$917.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$918.
  removing unused non-port wire $auto$rtlil.cc:2376:And$921.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$923.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$925.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$927.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$928.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$929.
  removing unused non-port wire $auto$rtlil.cc:2376:And$932.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$934.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$936.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$938.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$939.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$940.
  removing unused non-port wire $auto$rtlil.cc:2376:And$943.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$945.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$947.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$949.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$950.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$951.
  removing unused non-port wire $auto$rtlil.cc:2376:And$954.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$956.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$958.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$960.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$961.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$962.
  removing unused non-port wire $auto$rtlil.cc:2376:And$965.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$967.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$969.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$971.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$972.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$973.
  removing unused non-port wire $auto$rtlil.cc:2376:And$976.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$978.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$980.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$982.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$983.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$984.
  removing unused non-port wire $auto$rtlil.cc:2376:And$987.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$989.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$991.
  removing unused non-port wire $techmap$techmap1000\capRam.mem1.2.3.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y.
  removing unused non-port wire $techmap1000\capRam.mem1.2.3.0.B1DATA_16.
  removing unused non-port wire $techmap1000\capRam.mem1.2.3.0.A1DATA_16.
  removing unused non-port wire $techmap1000\capRam.mem1.2.3.0.B1ADDR_11.
  removing unused non-port wire $techmap1000\capRam.mem1.2.3.0.A1ADDR_11.
  removing unused non-port wire $techmap1000\capRam.mem1.2.3.0.B1EN.
  removing unused non-port wire $techmap1000\capRam.mem1.2.3.0.B1DATA.
  removing unused non-port wire $techmap1000\capRam.mem1.2.3.0.B1ADDR.
  removing unused non-port wire $techmap1000\capRam.mem1.2.3.0.A1EN.
  removing unused non-port wire $techmap1000\capRam.mem1.2.3.0.A1DATA.
  removing unused non-port wire $techmap1000\capRam.mem1.2.3.0.A1ADDR.
  removing unused non-port wire $techmap1000\capRam.mem1.2.3.0.CLK3.
  removing unused non-port wire $techmap1000\capRam.mem1.2.3.0.CLK2.
  removing unused non-port wire $techmap$techmap1002\capRam.mem1.0.0.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$1001_Y.
  removing unused non-port wire $techmap1002\capRam.mem1.0.0.0.B1DATA_16.
  removing unused non-port wire $techmap1002\capRam.mem1.0.0.0.B1ADDR_11.
  removing unused non-port wire $techmap1002\capRam.mem1.0.0.0.A1ADDR_11.
  removing unused non-port wire $techmap1002\capRam.mem1.0.0.0.B1EN.
  removing unused non-port wire $techmap1002\capRam.mem1.0.0.0.B1DATA.
  removing unused non-port wire $techmap1002\capRam.mem1.0.0.0.B1ADDR.
  removing unused non-port wire $techmap1002\capRam.mem1.0.0.0.A1EN.
  removing unused non-port wire $techmap1002\capRam.mem1.0.0.0.A1DATA.
  removing unused non-port wire $techmap1002\capRam.mem1.0.0.0.A1ADDR.
  removing unused non-port wire $techmap1002\capRam.mem1.0.0.0.CLK3.
  removing unused non-port wire $techmap1002\capRam.mem1.0.0.0.CLK2.
  removing unused non-port wire $techmap$techmap1003\capRam.mem1.1.1.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y.
  removing unused non-port wire $techmap1003\capRam.mem1.1.1.0.B1DATA_16.
  removing unused non-port wire $techmap1003\capRam.mem1.1.1.0.A1DATA_16.
  removing unused non-port wire $techmap1003\capRam.mem1.1.1.0.B1ADDR_11.
  removing unused non-port wire $techmap1003\capRam.mem1.1.1.0.A1ADDR_11.
  removing unused non-port wire $techmap1003\capRam.mem1.1.1.0.B1EN.
  removing unused non-port wire $techmap1003\capRam.mem1.1.1.0.B1DATA.
  removing unused non-port wire $techmap1003\capRam.mem1.1.1.0.B1ADDR.
  removing unused non-port wire $techmap1003\capRam.mem1.1.1.0.A1EN.
  removing unused non-port wire $techmap1003\capRam.mem1.1.1.0.A1DATA.
  removing unused non-port wire $techmap1003\capRam.mem1.1.1.0.A1ADDR.
  removing unused non-port wire $techmap1003\capRam.mem1.1.1.0.CLK3.
  removing unused non-port wire $techmap1003\capRam.mem1.1.1.0.CLK2.
  removing unused non-port wire $techmap$techmap1004\capRam.mem1.0.1.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y.
  removing unused non-port wire $techmap1004\capRam.mem1.0.1.0.B1DATA_16.
  removing unused non-port wire $techmap1004\capRam.mem1.0.1.0.B1ADDR_11.
  removing unused non-port wire $techmap1004\capRam.mem1.0.1.0.A1ADDR_11.
  removing unused non-port wire $techmap1004\capRam.mem1.0.1.0.B1EN.
  removing unused non-port wire $techmap1004\capRam.mem1.0.1.0.B1DATA.
  removing unused non-port wire $techmap1004\capRam.mem1.0.1.0.B1ADDR.
  removing unused non-port wire $techmap1004\capRam.mem1.0.1.0.A1EN.
  removing unused non-port wire $techmap1004\capRam.mem1.0.1.0.A1DATA.
  removing unused non-port wire $techmap1004\capRam.mem1.0.1.0.A1ADDR.
  removing unused non-port wire $techmap1004\capRam.mem1.0.1.0.CLK3.
  removing unused non-port wire $techmap1004\capRam.mem1.0.1.0.CLK2.
  removing unused non-port wire $techmap$techmap1005\capRam.mem1.3.3.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y.
  removing unused non-port wire $techmap1005\capRam.mem1.3.3.0.B1DATA_16.
  removing unused non-port wire $techmap1005\capRam.mem1.3.3.0.A1DATA_16.
  removing unused non-port wire $techmap1005\capRam.mem1.3.3.0.B1ADDR_11.
  removing unused non-port wire $techmap1005\capRam.mem1.3.3.0.A1ADDR_11.
  removing unused non-port wire $techmap1005\capRam.mem1.3.3.0.B1EN.
  removing unused non-port wire $techmap1005\capRam.mem1.3.3.0.B1DATA.
  removing unused non-port wire $techmap1005\capRam.mem1.3.3.0.B1ADDR.
  removing unused non-port wire $techmap1005\capRam.mem1.3.3.0.A1EN.
  removing unused non-port wire $techmap1005\capRam.mem1.3.3.0.A1DATA.
  removing unused non-port wire $techmap1005\capRam.mem1.3.3.0.A1ADDR.
  removing unused non-port wire $techmap1005\capRam.mem1.3.3.0.CLK3.
  removing unused non-port wire $techmap1005\capRam.mem1.3.3.0.CLK2.
  removing unused non-port wire $techmap$techmap1006\capRam.mem1.1.0.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$1001_Y.
  removing unused non-port wire $techmap1006\capRam.mem1.1.0.0.B1DATA_16.
  removing unused non-port wire $techmap1006\capRam.mem1.1.0.0.A1DATA_16.
  removing unused non-port wire $techmap1006\capRam.mem1.1.0.0.B1ADDR_11.
  removing unused non-port wire $techmap1006\capRam.mem1.1.0.0.A1ADDR_11.
  removing unused non-port wire $techmap1006\capRam.mem1.1.0.0.B1EN.
  removing unused non-port wire $techmap1006\capRam.mem1.1.0.0.B1DATA.
  removing unused non-port wire $techmap1006\capRam.mem1.1.0.0.B1ADDR.
  removing unused non-port wire $techmap1006\capRam.mem1.1.0.0.A1EN.
  removing unused non-port wire $techmap1006\capRam.mem1.1.0.0.A1DATA.
  removing unused non-port wire $techmap1006\capRam.mem1.1.0.0.A1ADDR.
  removing unused non-port wire $techmap1006\capRam.mem1.1.0.0.CLK3.
  removing unused non-port wire $techmap1006\capRam.mem1.1.0.0.CLK2.
  removing unused non-port wire $techmap$techmap1007\capRam.mem1.1.3.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y.
  removing unused non-port wire $techmap1007\capRam.mem1.1.3.0.B1DATA_16.
  removing unused non-port wire $techmap1007\capRam.mem1.1.3.0.A1DATA_16.
  removing unused non-port wire $techmap1007\capRam.mem1.1.3.0.B1ADDR_11.
  removing unused non-port wire $techmap1007\capRam.mem1.1.3.0.A1ADDR_11.
  removing unused non-port wire $techmap1007\capRam.mem1.1.3.0.B1EN.
  removing unused non-port wire $techmap1007\capRam.mem1.1.3.0.B1DATA.
  removing unused non-port wire $techmap1007\capRam.mem1.1.3.0.B1ADDR.
  removing unused non-port wire $techmap1007\capRam.mem1.1.3.0.A1EN.
  removing unused non-port wire $techmap1007\capRam.mem1.1.3.0.A1DATA.
  removing unused non-port wire $techmap1007\capRam.mem1.1.3.0.A1ADDR.
  removing unused non-port wire $techmap1007\capRam.mem1.1.3.0.CLK3.
  removing unused non-port wire $techmap1007\capRam.mem1.1.3.0.CLK2.
  removing unused non-port wire $techmap$techmap1008\capRam.mem1.2.1.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y.
  removing unused non-port wire $techmap1008\capRam.mem1.2.1.0.B1DATA_16.
  removing unused non-port wire $techmap1008\capRam.mem1.2.1.0.A1DATA_16.
  removing unused non-port wire $techmap1008\capRam.mem1.2.1.0.B1ADDR_11.
  removing unused non-port wire $techmap1008\capRam.mem1.2.1.0.A1ADDR_11.
  removing unused non-port wire $techmap1008\capRam.mem1.2.1.0.B1EN.
  removing unused non-port wire $techmap1008\capRam.mem1.2.1.0.B1DATA.
  removing unused non-port wire $techmap1008\capRam.mem1.2.1.0.B1ADDR.
  removing unused non-port wire $techmap1008\capRam.mem1.2.1.0.A1EN.
  removing unused non-port wire $techmap1008\capRam.mem1.2.1.0.A1DATA.
  removing unused non-port wire $techmap1008\capRam.mem1.2.1.0.A1ADDR.
  removing unused non-port wire $techmap1008\capRam.mem1.2.1.0.CLK3.
  removing unused non-port wire $techmap1008\capRam.mem1.2.1.0.CLK2.
  removing unused non-port wire $techmap$techmap1009\capRam.mem1.0.3.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y.
  removing unused non-port wire $techmap1009\capRam.mem1.0.3.0.B1DATA_16.
  removing unused non-port wire $techmap1009\capRam.mem1.0.3.0.B1ADDR_11.
  removing unused non-port wire $techmap1009\capRam.mem1.0.3.0.A1ADDR_11.
  removing unused non-port wire $techmap1009\capRam.mem1.0.3.0.B1EN.
  removing unused non-port wire $techmap1009\capRam.mem1.0.3.0.B1DATA.
  removing unused non-port wire $techmap1009\capRam.mem1.0.3.0.B1ADDR.
  removing unused non-port wire $techmap1009\capRam.mem1.0.3.0.A1EN.
  removing unused non-port wire $techmap1009\capRam.mem1.0.3.0.A1DATA.
  removing unused non-port wire $techmap1009\capRam.mem1.0.3.0.A1ADDR.
  removing unused non-port wire $techmap1009\capRam.mem1.0.3.0.CLK3.
  removing unused non-port wire $techmap1009\capRam.mem1.0.3.0.CLK2.
  removing unused non-port wire $techmap$techmap1010\capRam.mem1.2.2.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y.
  removing unused non-port wire $techmap1010\capRam.mem1.2.2.0.B1DATA_16.
  removing unused non-port wire $techmap1010\capRam.mem1.2.2.0.A1DATA_16.
  removing unused non-port wire $techmap1010\capRam.mem1.2.2.0.B1ADDR_11.
  removing unused non-port wire $techmap1010\capRam.mem1.2.2.0.A1ADDR_11.
  removing unused non-port wire $techmap1010\capRam.mem1.2.2.0.B1EN.
  removing unused non-port wire $techmap1010\capRam.mem1.2.2.0.B1DATA.
  removing unused non-port wire $techmap1010\capRam.mem1.2.2.0.B1ADDR.
  removing unused non-port wire $techmap1010\capRam.mem1.2.2.0.A1EN.
  removing unused non-port wire $techmap1010\capRam.mem1.2.2.0.A1DATA.
  removing unused non-port wire $techmap1010\capRam.mem1.2.2.0.A1ADDR.
  removing unused non-port wire $techmap1010\capRam.mem1.2.2.0.CLK3.
  removing unused non-port wire $techmap1010\capRam.mem1.2.2.0.CLK2.
  removing unused non-port wire $techmap$techmap1011\capRam.mem1.0.2.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y.
  removing unused non-port wire $techmap1011\capRam.mem1.0.2.0.B1DATA_16.
  removing unused non-port wire $techmap1011\capRam.mem1.0.2.0.B1ADDR_11.
  removing unused non-port wire $techmap1011\capRam.mem1.0.2.0.A1ADDR_11.
  removing unused non-port wire $techmap1011\capRam.mem1.0.2.0.B1EN.
  removing unused non-port wire $techmap1011\capRam.mem1.0.2.0.B1DATA.
  removing unused non-port wire $techmap1011\capRam.mem1.0.2.0.B1ADDR.
  removing unused non-port wire $techmap1011\capRam.mem1.0.2.0.A1EN.
  removing unused non-port wire $techmap1011\capRam.mem1.0.2.0.A1DATA.
  removing unused non-port wire $techmap1011\capRam.mem1.0.2.0.A1ADDR.
  removing unused non-port wire $techmap1011\capRam.mem1.0.2.0.CLK3.
  removing unused non-port wire $techmap1011\capRam.mem1.0.2.0.CLK2.
  removing unused non-port wire $techmap$techmap1012\capRam.mem1.2.0.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$1001_Y.
  removing unused non-port wire $techmap1012\capRam.mem1.2.0.0.B1DATA_16.
  removing unused non-port wire $techmap1012\capRam.mem1.2.0.0.A1DATA_16.
  removing unused non-port wire $techmap1012\capRam.mem1.2.0.0.B1ADDR_11.
  removing unused non-port wire $techmap1012\capRam.mem1.2.0.0.A1ADDR_11.
  removing unused non-port wire $techmap1012\capRam.mem1.2.0.0.B1EN.
  removing unused non-port wire $techmap1012\capRam.mem1.2.0.0.B1DATA.
  removing unused non-port wire $techmap1012\capRam.mem1.2.0.0.B1ADDR.
  removing unused non-port wire $techmap1012\capRam.mem1.2.0.0.A1EN.
  removing unused non-port wire $techmap1012\capRam.mem1.2.0.0.A1DATA.
  removing unused non-port wire $techmap1012\capRam.mem1.2.0.0.A1ADDR.
  removing unused non-port wire $techmap1012\capRam.mem1.2.0.0.CLK3.
  removing unused non-port wire $techmap1012\capRam.mem1.2.0.0.CLK2.
  removing unused non-port wire $techmap$techmap1013\capRam.mem1.3.2.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y.
  removing unused non-port wire $techmap1013\capRam.mem1.3.2.0.B1DATA_16.
  removing unused non-port wire $techmap1013\capRam.mem1.3.2.0.A1DATA_16.
  removing unused non-port wire $techmap1013\capRam.mem1.3.2.0.B1ADDR_11.
  removing unused non-port wire $techmap1013\capRam.mem1.3.2.0.A1ADDR_11.
  removing unused non-port wire $techmap1013\capRam.mem1.3.2.0.B1EN.
  removing unused non-port wire $techmap1013\capRam.mem1.3.2.0.B1DATA.
  removing unused non-port wire $techmap1013\capRam.mem1.3.2.0.B1ADDR.
  removing unused non-port wire $techmap1013\capRam.mem1.3.2.0.A1EN.
  removing unused non-port wire $techmap1013\capRam.mem1.3.2.0.A1DATA.
  removing unused non-port wire $techmap1013\capRam.mem1.3.2.0.A1ADDR.
  removing unused non-port wire $techmap1013\capRam.mem1.3.2.0.CLK3.
  removing unused non-port wire $techmap1013\capRam.mem1.3.2.0.CLK2.
  removing unused non-port wire $techmap$techmap1014\capRam.mem1.3.1.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y.
  removing unused non-port wire $techmap1014\capRam.mem1.3.1.0.B1DATA_16.
  removing unused non-port wire $techmap1014\capRam.mem1.3.1.0.A1DATA_16.
  removing unused non-port wire $techmap1014\capRam.mem1.3.1.0.B1ADDR_11.
  removing unused non-port wire $techmap1014\capRam.mem1.3.1.0.A1ADDR_11.
  removing unused non-port wire $techmap1014\capRam.mem1.3.1.0.B1EN.
  removing unused non-port wire $techmap1014\capRam.mem1.3.1.0.B1DATA.
  removing unused non-port wire $techmap1014\capRam.mem1.3.1.0.B1ADDR.
  removing unused non-port wire $techmap1014\capRam.mem1.3.1.0.A1EN.
  removing unused non-port wire $techmap1014\capRam.mem1.3.1.0.A1DATA.
  removing unused non-port wire $techmap1014\capRam.mem1.3.1.0.A1ADDR.
  removing unused non-port wire $techmap1014\capRam.mem1.3.1.0.CLK3.
  removing unused non-port wire $techmap1014\capRam.mem1.3.1.0.CLK2.
  removing unused non-port wire $techmap$techmap1015\capRam.mem1.1.2.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$999_Y.
  removing unused non-port wire $techmap1015\capRam.mem1.1.2.0.B1DATA_16.
  removing unused non-port wire $techmap1015\capRam.mem1.1.2.0.A1DATA_16.
  removing unused non-port wire $techmap1015\capRam.mem1.1.2.0.B1ADDR_11.
  removing unused non-port wire $techmap1015\capRam.mem1.1.2.0.A1ADDR_11.
  removing unused non-port wire $techmap1015\capRam.mem1.1.2.0.B1EN.
  removing unused non-port wire $techmap1015\capRam.mem1.1.2.0.B1DATA.
  removing unused non-port wire $techmap1015\capRam.mem1.1.2.0.B1ADDR.
  removing unused non-port wire $techmap1015\capRam.mem1.1.2.0.A1EN.
  removing unused non-port wire $techmap1015\capRam.mem1.1.2.0.A1DATA.
  removing unused non-port wire $techmap1015\capRam.mem1.1.2.0.A1ADDR.
  removing unused non-port wire $techmap1015\capRam.mem1.1.2.0.CLK3.
  removing unused non-port wire $techmap1015\capRam.mem1.1.2.0.CLK2.
  removing unused non-port wire $techmap$techmap1016\capRam.mem1.3.0.0.$reduce_or$/usr/local/bin/../share/yosys/ice40/brams_map.v:311$1001_Y.
  removing unused non-port wire $techmap1016\capRam.mem1.3.0.0.B1DATA_16.
  removing unused non-port wire $techmap1016\capRam.mem1.3.0.0.A1DATA_16.
  removing unused non-port wire $techmap1016\capRam.mem1.3.0.0.B1ADDR_11.
  removing unused non-port wire $techmap1016\capRam.mem1.3.0.0.A1ADDR_11.
  removing unused non-port wire $techmap1016\capRam.mem1.3.0.0.B1EN.
  removing unused non-port wire $techmap1016\capRam.mem1.3.0.0.B1DATA.
  removing unused non-port wire $techmap1016\capRam.mem1.3.0.0.B1ADDR.
  removing unused non-port wire $techmap1016\capRam.mem1.3.0.0.A1EN.
  removing unused non-port wire $techmap1016\capRam.mem1.3.0.0.A1DATA.
  removing unused non-port wire $techmap1016\capRam.mem1.3.0.0.A1ADDR.
  removing unused non-port wire $techmap1016\capRam.mem1.3.0.0.CLK3.
  removing unused non-port wire $techmap1016\capRam.mem1.3.0.0.CLK2.
  removing unused non-port wire $techmap1017\capRam.mem1.0.2.0.WDATA.
  removing unused non-port wire $techmap1017\capRam.mem1.0.2.0.MASK.
  removing unused non-port wire $techmap1017\capRam.mem1.0.2.0.WADDR.
  removing unused non-port wire $techmap1017\capRam.mem1.0.2.0.WE.
  removing unused non-port wire $techmap1017\capRam.mem1.0.2.0.WCLKE.
  removing unused non-port wire $techmap1017\capRam.mem1.0.2.0.WCLK.
  removing unused non-port wire $techmap1017\capRam.mem1.0.2.0.RADDR.
  removing unused non-port wire $techmap1017\capRam.mem1.0.2.0.RE.
  removing unused non-port wire $techmap1017\capRam.mem1.0.2.0.RCLKE.
  removing unused non-port wire $techmap1017\capRam.mem1.0.2.0.RCLK.
  removing unused non-port wire $techmap1017\capRam.mem1.0.2.0.RDATA.
  removing unused non-port wire $techmap1018\capRam.mem1.2.0.0.WDATA.
  removing unused non-port wire $techmap1018\capRam.mem1.2.0.0.MASK.
  removing unused non-port wire $techmap1018\capRam.mem1.2.0.0.WADDR.
  removing unused non-port wire $techmap1018\capRam.mem1.2.0.0.WE.
  removing unused non-port wire $techmap1018\capRam.mem1.2.0.0.WCLKE.
  removing unused non-port wire $techmap1018\capRam.mem1.2.0.0.WCLK.
  removing unused non-port wire $techmap1018\capRam.mem1.2.0.0.RADDR.
  removing unused non-port wire $techmap1018\capRam.mem1.2.0.0.RE.
  removing unused non-port wire $techmap1018\capRam.mem1.2.0.0.RCLKE.
  removing unused non-port wire $techmap1018\capRam.mem1.2.0.0.RCLK.
  removing unused non-port wire $techmap1018\capRam.mem1.2.0.0.RDATA.
  removing unused non-port wire $techmap1019\capRam.mem1.2.2.0.WDATA.
  removing unused non-port wire $techmap1019\capRam.mem1.2.2.0.MASK.
  removing unused non-port wire $techmap1019\capRam.mem1.2.2.0.WADDR.
  removing unused non-port wire $techmap1019\capRam.mem1.2.2.0.WE.
  removing unused non-port wire $techmap1019\capRam.mem1.2.2.0.WCLKE.
  removing unused non-port wire $techmap1019\capRam.mem1.2.2.0.WCLK.
  removing unused non-port wire $techmap1019\capRam.mem1.2.2.0.RADDR.
  removing unused non-port wire $techmap1019\capRam.mem1.2.2.0.RE.
  removing unused non-port wire $techmap1019\capRam.mem1.2.2.0.RCLKE.
  removing unused non-port wire $techmap1019\capRam.mem1.2.2.0.RCLK.
  removing unused non-port wire $techmap1019\capRam.mem1.2.2.0.RDATA.
  removing unused non-port wire $techmap1020\capRam.mem1.3.0.0.WDATA.
  removing unused non-port wire $techmap1020\capRam.mem1.3.0.0.MASK.
  removing unused non-port wire $techmap1020\capRam.mem1.3.0.0.WADDR.
  removing unused non-port wire $techmap1020\capRam.mem1.3.0.0.WE.
  removing unused non-port wire $techmap1020\capRam.mem1.3.0.0.WCLKE.
  removing unused non-port wire $techmap1020\capRam.mem1.3.0.0.WCLK.
  removing unused non-port wire $techmap1020\capRam.mem1.3.0.0.RADDR.
  removing unused non-port wire $techmap1020\capRam.mem1.3.0.0.RE.
  removing unused non-port wire $techmap1020\capRam.mem1.3.0.0.RCLKE.
  removing unused non-port wire $techmap1020\capRam.mem1.3.0.0.RCLK.
  removing unused non-port wire $techmap1020\capRam.mem1.3.0.0.RDATA.
  removing unused non-port wire $techmap1021\capRam.mem1.1.2.0.WDATA.
  removing unused non-port wire $techmap1021\capRam.mem1.1.2.0.MASK.
  removing unused non-port wire $techmap1021\capRam.mem1.1.2.0.WADDR.
  removing unused non-port wire $techmap1021\capRam.mem1.1.2.0.WE.
  removing unused non-port wire $techmap1021\capRam.mem1.1.2.0.WCLKE.
  removing unused non-port wire $techmap1021\capRam.mem1.1.2.0.WCLK.
  removing unused non-port wire $techmap1021\capRam.mem1.1.2.0.RADDR.
  removing unused non-port wire $techmap1021\capRam.mem1.1.2.0.RE.
  removing unused non-port wire $techmap1021\capRam.mem1.1.2.0.RCLKE.
  removing unused non-port wire $techmap1021\capRam.mem1.1.2.0.RCLK.
  removing unused non-port wire $techmap1021\capRam.mem1.1.2.0.RDATA.
  removing unused non-port wire $techmap1022\capRam.mem1.3.1.0.WDATA.
  removing unused non-port wire $techmap1022\capRam.mem1.3.1.0.MASK.
  removing unused non-port wire $techmap1022\capRam.mem1.3.1.0.WADDR.
  removing unused non-port wire $techmap1022\capRam.mem1.3.1.0.WE.
  removing unused non-port wire $techmap1022\capRam.mem1.3.1.0.WCLKE.
  removing unused non-port wire $techmap1022\capRam.mem1.3.1.0.WCLK.
  removing unused non-port wire $techmap1022\capRam.mem1.3.1.0.RADDR.
  removing unused non-port wire $techmap1022\capRam.mem1.3.1.0.RE.
  removing unused non-port wire $techmap1022\capRam.mem1.3.1.0.RCLKE.
  removing unused non-port wire $techmap1022\capRam.mem1.3.1.0.RCLK.
  removing unused non-port wire $techmap1022\capRam.mem1.3.1.0.RDATA.
  removing unused non-port wire $techmap1023\capRam.mem1.1.0.0.WDATA.
  removing unused non-port wire $techmap1023\capRam.mem1.1.0.0.MASK.
  removing unused non-port wire $techmap1023\capRam.mem1.1.0.0.WADDR.
  removing unused non-port wire $techmap1023\capRam.mem1.1.0.0.WE.
  removing unused non-port wire $techmap1023\capRam.mem1.1.0.0.WCLKE.
  removing unused non-port wire $techmap1023\capRam.mem1.1.0.0.WCLK.
  removing unused non-port wire $techmap1023\capRam.mem1.1.0.0.RADDR.
  removing unused non-port wire $techmap1023\capRam.mem1.1.0.0.RE.
  removing unused non-port wire $techmap1023\capRam.mem1.1.0.0.RCLKE.
  removing unused non-port wire $techmap1023\capRam.mem1.1.0.0.RCLK.
  removing unused non-port wire $techmap1023\capRam.mem1.1.0.0.RDATA.
  removing unused non-port wire $techmap1024\capRam.mem1.3.3.0.WDATA.
  removing unused non-port wire $techmap1024\capRam.mem1.3.3.0.MASK.
  removing unused non-port wire $techmap1024\capRam.mem1.3.3.0.WADDR.
  removing unused non-port wire $techmap1024\capRam.mem1.3.3.0.WE.
  removing unused non-port wire $techmap1024\capRam.mem1.3.3.0.WCLKE.
  removing unused non-port wire $techmap1024\capRam.mem1.3.3.0.WCLK.
  removing unused non-port wire $techmap1024\capRam.mem1.3.3.0.RADDR.
  removing unused non-port wire $techmap1024\capRam.mem1.3.3.0.RE.
  removing unused non-port wire $techmap1024\capRam.mem1.3.3.0.RCLKE.
  removing unused non-port wire $techmap1024\capRam.mem1.3.3.0.RCLK.
  removing unused non-port wire $techmap1024\capRam.mem1.3.3.0.RDATA.
  removing unused non-port wire $techmap1025\capRam.mem1.0.1.0.WDATA.
  removing unused non-port wire $techmap1025\capRam.mem1.0.1.0.MASK.
  removing unused non-port wire $techmap1025\capRam.mem1.0.1.0.WADDR.
  removing unused non-port wire $techmap1025\capRam.mem1.0.1.0.WE.
  removing unused non-port wire $techmap1025\capRam.mem1.0.1.0.WCLKE.
  removing unused non-port wire $techmap1025\capRam.mem1.0.1.0.WCLK.
  removing unused non-port wire $techmap1025\capRam.mem1.0.1.0.RADDR.
  removing unused non-port wire $techmap1025\capRam.mem1.0.1.0.RE.
  removing unused non-port wire $techmap1025\capRam.mem1.0.1.0.RCLKE.
  removing unused non-port wire $techmap1025\capRam.mem1.0.1.0.RCLK.
  removing unused non-port wire $techmap1025\capRam.mem1.0.1.0.RDATA.
  removing unused non-port wire $techmap1026\capRam.mem1.1.1.0.WDATA.
  removing unused non-port wire $techmap1026\capRam.mem1.1.1.0.MASK.
  removing unused non-port wire $techmap1026\capRam.mem1.1.1.0.WADDR.
  removing unused non-port wire $techmap1026\capRam.mem1.1.1.0.WE.
  removing unused non-port wire $techmap1026\capRam.mem1.1.1.0.WCLKE.
  removing unused non-port wire $techmap1026\capRam.mem1.1.1.0.WCLK.
  removing unused non-port wire $techmap1026\capRam.mem1.1.1.0.RADDR.
  removing unused non-port wire $techmap1026\capRam.mem1.1.1.0.RE.
  removing unused non-port wire $techmap1026\capRam.mem1.1.1.0.RCLKE.
  removing unused non-port wire $techmap1026\capRam.mem1.1.1.0.RCLK.
  removing unused non-port wire $techmap1026\capRam.mem1.1.1.0.RDATA.
  removing unused non-port wire $techmap1027\capRam.mem1.0.0.0.WDATA.
  removing unused non-port wire $techmap1027\capRam.mem1.0.0.0.MASK.
  removing unused non-port wire $techmap1027\capRam.mem1.0.0.0.WADDR.
  removing unused non-port wire $techmap1027\capRam.mem1.0.0.0.WE.
  removing unused non-port wire $techmap1027\capRam.mem1.0.0.0.WCLKE.
  removing unused non-port wire $techmap1027\capRam.mem1.0.0.0.WCLK.
  removing unused non-port wire $techmap1027\capRam.mem1.0.0.0.RADDR.
  removing unused non-port wire $techmap1027\capRam.mem1.0.0.0.RE.
  removing unused non-port wire $techmap1027\capRam.mem1.0.0.0.RCLKE.
  removing unused non-port wire $techmap1027\capRam.mem1.0.0.0.RCLK.
  removing unused non-port wire $techmap1027\capRam.mem1.0.0.0.RDATA.
  removing unused non-port wire $techmap1028\capRam.mem1.0.3.0.WDATA.
  removing unused non-port wire $techmap1028\capRam.mem1.0.3.0.MASK.
  removing unused non-port wire $techmap1028\capRam.mem1.0.3.0.WADDR.
  removing unused non-port wire $techmap1028\capRam.mem1.0.3.0.WE.
  removing unused non-port wire $techmap1028\capRam.mem1.0.3.0.WCLKE.
  removing unused non-port wire $techmap1028\capRam.mem1.0.3.0.WCLK.
  removing unused non-port wire $techmap1028\capRam.mem1.0.3.0.RADDR.
  removing unused non-port wire $techmap1028\capRam.mem1.0.3.0.RE.
  removing unused non-port wire $techmap1028\capRam.mem1.0.3.0.RCLKE.
  removing unused non-port wire $techmap1028\capRam.mem1.0.3.0.RCLK.
  removing unused non-port wire $techmap1028\capRam.mem1.0.3.0.RDATA.
  removing unused non-port wire $techmap1029\capRam.mem1.2.3.0.WDATA.
  removing unused non-port wire $techmap1029\capRam.mem1.2.3.0.MASK.
  removing unused non-port wire $techmap1029\capRam.mem1.2.3.0.WADDR.
  removing unused non-port wire $techmap1029\capRam.mem1.2.3.0.WE.
  removing unused non-port wire $techmap1029\capRam.mem1.2.3.0.WCLKE.
  removing unused non-port wire $techmap1029\capRam.mem1.2.3.0.WCLK.
  removing unused non-port wire $techmap1029\capRam.mem1.2.3.0.RADDR.
  removing unused non-port wire $techmap1029\capRam.mem1.2.3.0.RE.
  removing unused non-port wire $techmap1029\capRam.mem1.2.3.0.RCLKE.
  removing unused non-port wire $techmap1029\capRam.mem1.2.3.0.RCLK.
  removing unused non-port wire $techmap1029\capRam.mem1.2.3.0.RDATA.
  removing unused non-port wire $techmap1030\capRam.mem1.3.2.0.WDATA.
  removing unused non-port wire $techmap1030\capRam.mem1.3.2.0.MASK.
  removing unused non-port wire $techmap1030\capRam.mem1.3.2.0.WADDR.
  removing unused non-port wire $techmap1030\capRam.mem1.3.2.0.WE.
  removing unused non-port wire $techmap1030\capRam.mem1.3.2.0.WCLKE.
  removing unused non-port wire $techmap1030\capRam.mem1.3.2.0.WCLK.
  removing unused non-port wire $techmap1030\capRam.mem1.3.2.0.RADDR.
  removing unused non-port wire $techmap1030\capRam.mem1.3.2.0.RE.
  removing unused non-port wire $techmap1030\capRam.mem1.3.2.0.RCLKE.
  removing unused non-port wire $techmap1030\capRam.mem1.3.2.0.RCLK.
  removing unused non-port wire $techmap1030\capRam.mem1.3.2.0.RDATA.
  removing unused non-port wire $techmap1031\capRam.mem1.2.1.0.WDATA.
  removing unused non-port wire $techmap1031\capRam.mem1.2.1.0.MASK.
  removing unused non-port wire $techmap1031\capRam.mem1.2.1.0.WADDR.
  removing unused non-port wire $techmap1031\capRam.mem1.2.1.0.WE.
  removing unused non-port wire $techmap1031\capRam.mem1.2.1.0.WCLKE.
  removing unused non-port wire $techmap1031\capRam.mem1.2.1.0.WCLK.
  removing unused non-port wire $techmap1031\capRam.mem1.2.1.0.RADDR.
  removing unused non-port wire $techmap1031\capRam.mem1.2.1.0.RE.
  removing unused non-port wire $techmap1031\capRam.mem1.2.1.0.RCLKE.
  removing unused non-port wire $techmap1031\capRam.mem1.2.1.0.RCLK.
  removing unused non-port wire $techmap1031\capRam.mem1.2.1.0.RDATA.
  removing unused non-port wire $techmap1032\capRam.mem1.1.3.0.WDATA.
  removing unused non-port wire $techmap1032\capRam.mem1.1.3.0.MASK.
  removing unused non-port wire $techmap1032\capRam.mem1.1.3.0.WADDR.
  removing unused non-port wire $techmap1032\capRam.mem1.1.3.0.WE.
  removing unused non-port wire $techmap1032\capRam.mem1.1.3.0.WCLKE.
  removing unused non-port wire $techmap1032\capRam.mem1.1.3.0.WCLK.
  removing unused non-port wire $techmap1032\capRam.mem1.1.3.0.RADDR.
  removing unused non-port wire $techmap1032\capRam.mem1.1.3.0.RE.
  removing unused non-port wire $techmap1032\capRam.mem1.1.3.0.RCLKE.
  removing unused non-port wire $techmap1032\capRam.mem1.1.3.0.RCLK.
  removing unused non-port wire $techmap1032\capRam.mem1.1.3.0.RDATA.
Removed 20 unused cells and 468 unused wires.

2.27.5. Rerunning OPT passes. (Removed registers in this run.)

2.27.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.27.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.27.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $procdff$737 ($dff) from module main (D = $procmux$520_Y, Q = \cap24m, rval = 1'0).
Handling never-active EN on $auto$ff.cc:262:slice$800 ($dffe) from module main (removing D path).
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Setting constant 0-bit at position 2 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Setting constant 0-bit at position 3 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Setting constant 0-bit at position 4 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Setting constant 0-bit at position 5 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Setting constant 0-bit at position 6 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Setting constant 0-bit at position 7 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Setting constant 0-bit at position 8 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Setting constant 0-bit at position 9 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Setting constant 0-bit at position 10 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Setting constant 0-bit at position 11 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Setting constant 0-bit at position 12 on $auto$ff.cc:262:slice$800 ($dffe) from module main.
Handling never-active EN on $auto$ff.cc:262:slice$799 ($dffe) from module main (removing D path).
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Setting constant 0-bit at position 2 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Setting constant 0-bit at position 3 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Setting constant 0-bit at position 4 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Setting constant 0-bit at position 5 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Setting constant 0-bit at position 6 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Setting constant 0-bit at position 7 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Setting constant 0-bit at position 8 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Setting constant 0-bit at position 9 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Setting constant 0-bit at position 10 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Setting constant 0-bit at position 11 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Setting constant 0-bit at position 12 on $auto$ff.cc:262:slice$799 ($dffe) from module main.
Handling never-active EN on $auto$ff.cc:262:slice$798 ($dffe) from module main (removing D path).
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$798 ($dffe) from module main.
Handling never-active EN on $auto$ff.cc:262:slice$796 ($dffe) from module main (removing D path).
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Setting constant 1-bit at position 1 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Setting constant 1-bit at position 2 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Setting constant 1-bit at position 3 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Setting constant 1-bit at position 4 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Setting constant 1-bit at position 5 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Setting constant 1-bit at position 6 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Setting constant 1-bit at position 7 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Setting constant 1-bit at position 8 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Setting constant 1-bit at position 9 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Setting constant 1-bit at position 10 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Setting constant 1-bit at position 11 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Setting constant 1-bit at position 12 on $auto$ff.cc:262:slice$796 ($dffe) from module main.
Handling never-active EN on $auto$ff.cc:262:slice$795 ($dffe) from module main (removing D path).
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Setting constant 1-bit at position 1 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Setting constant 1-bit at position 2 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Setting constant 1-bit at position 3 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Setting constant 1-bit at position 4 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Setting constant 1-bit at position 5 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Setting constant 1-bit at position 6 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Setting constant 1-bit at position 7 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Setting constant 1-bit at position 8 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Setting constant 1-bit at position 9 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Setting constant 1-bit at position 10 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Setting constant 1-bit at position 11 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Setting constant 1-bit at position 12 on $auto$ff.cc:262:slice$795 ($dffe) from module main.
Handling never-active EN on $auto$ff.cc:262:slice$794 ($dffe) from module main (removing D path).
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$794 ($dffe) from module main.
Handling never-active EN on $auto$ff.cc:262:slice$792 ($dffe) from module main (removing D path).
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Setting constant 1-bit at position 1 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Setting constant 1-bit at position 2 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Setting constant 1-bit at position 3 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Setting constant 1-bit at position 4 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Setting constant 1-bit at position 5 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Setting constant 1-bit at position 6 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Setting constant 1-bit at position 7 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Setting constant 1-bit at position 8 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Setting constant 1-bit at position 9 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Setting constant 1-bit at position 10 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Setting constant 1-bit at position 11 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Setting constant 1-bit at position 12 on $auto$ff.cc:262:slice$792 ($dffe) from module main.
Handling never-active EN on $auto$ff.cc:262:slice$791 ($dffe) from module main (removing D path).
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Setting constant 1-bit at position 1 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Setting constant 1-bit at position 2 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Setting constant 1-bit at position 3 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Setting constant 1-bit at position 4 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Setting constant 1-bit at position 5 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Setting constant 1-bit at position 6 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Setting constant 1-bit at position 7 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Setting constant 1-bit at position 8 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Setting constant 1-bit at position 9 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Setting constant 1-bit at position 10 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Setting constant 1-bit at position 11 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Setting constant 1-bit at position 12 on $auto$ff.cc:262:slice$791 ($dffe) from module main.
Handling never-active EN on $auto$ff.cc:262:slice$790 ($dffe) from module main (removing D path).
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$790 ($dffe) from module main.
Handling never-active EN on $auto$ff.cc:262:slice$788 ($dffe) from module main (removing D path).
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Setting constant 1-bit at position 1 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Setting constant 1-bit at position 2 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Setting constant 1-bit at position 3 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Setting constant 1-bit at position 4 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Setting constant 1-bit at position 5 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Setting constant 1-bit at position 6 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Setting constant 1-bit at position 7 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Setting constant 1-bit at position 8 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Setting constant 1-bit at position 9 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Setting constant 1-bit at position 10 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Setting constant 1-bit at position 11 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Setting constant 1-bit at position 12 on $auto$ff.cc:262:slice$788 ($dffe) from module main.
Handling never-active EN on $auto$ff.cc:262:slice$787 ($dffe) from module main (removing D path).
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Setting constant 1-bit at position 1 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Setting constant 1-bit at position 2 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Setting constant 1-bit at position 3 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Setting constant 1-bit at position 4 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Setting constant 1-bit at position 5 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Setting constant 1-bit at position 6 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Setting constant 1-bit at position 7 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Setting constant 1-bit at position 8 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Setting constant 1-bit at position 9 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Setting constant 1-bit at position 10 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Setting constant 1-bit at position 11 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Setting constant 1-bit at position 12 on $auto$ff.cc:262:slice$787 ($dffe) from module main.
Handling never-active EN on $auto$ff.cc:262:slice$786 ($dffe) from module main (removing D path).
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$786 ($dffe) from module main.
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$780 ($dffe) from module main.

2.27.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
  removing unused `$alu' cell `$auto$alumacc.cc:485:replace_alu$807'.
  removing unused `$eq' cell `$eq$main.v:221$56'.
  removing unused `$not' cell `$not$main.v:269$61'.
  removing unused `$eq' cell `$eq$main.v:273$63'.
  removing unused `$not' cell `$not$main.v:274$64'.
  removing unused `$not' cell `$not$main.v:283$66'.
  removing unused `$not' cell `$not$main.v:305$70'.
  removing unused `$alu' cell `$auto$alumacc.cc:485:replace_alu$804'.
  removing unused `$mux' cell `$procmux$520'.
  removing unused `$mux' cell `$procmux$527'.
  removing unused `$mux' cell `$procmux$634'.
  removing unused `$dff' cell `$procdff$719'.
  removing unused `$dff' cell `$procdff$725'.
  removing unused `$dff' cell `$procdff$731'.
  removing unused `$dffe' cell `$auto$ff.cc:262:slice$784'.
  removing unused `$sdff' cell `$auto$ff.cc:262:slice$783'.
  removing unused `$dffe' cell `$auto$ff.cc:262:slice$782'.
  removing unused `$dffe' cell `$auto$ff.cc:262:slice$781'.
  removing unused `$sdff' cell `$auto$ff.cc:262:slice$1033'.
Warning: Driver-driver conflict for \cap_wr_addr [12] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap_wr_addr [11] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap_wr_addr [10] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap_wr_addr [9] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap_wr_addr [8] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap_wr_addr [7] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap_wr_addr [6] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap_wr_addr [5] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap_wr_addr [4] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap_wr_addr [3] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap_wr_addr [2] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap_wr_addr [1] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
Warning: Driver-driver conflict for \cap_wr_addr [0] between cell $auto$ff.cc:262:slice$781.Q and constant 1'0 in main: Resolved using constant.
  removing unused non-port wire \clk_6M.
  removing unused non-port wire \clk_3M.
  removing unused non-port wire \clk_1M.
  removing unused non-port wire \clk_12M.
  removing unused non-port wire \clk1m_cnt.
  removing unused non-port wire \cap24m.
  removing unused non-port wire $procmux$527_Y.
  removing unused non-port wire $procmux$520_Y.
  removing unused non-port wire $not$main.v:274$64_Y.
  removing unused non-port wire $eq$main.v:273$63_Y.
  removing unused non-port wire $eq$main.v:221$56_Y.
  removing unused non-port wire $auto$alumacc.cc:502:replace_alu$809.
  removing unused non-port wire $auto$alumacc.cc:502:replace_alu$806.
  removing unused non-port wire $auto$alumacc.cc:501:replace_alu$808.
  removing unused non-port wire $auto$alumacc.cc:501:replace_alu$805.
  removing unused non-port wire $add$main.v:272$62_Y.
  removing unused non-port wire $add$main.v:220$55_Y.
  removing unused non-port wire $0\clk_6M[0:0].
  removing unused non-port wire $0\clk_3M[0:0].
  removing unused non-port wire $0\clk_12M[0:0].
  removing unused non-port wire $0\cap24m[0:0].
Removed 19 unused cells and 21 unused wires.

2.27.10. Rerunning OPT passes. (Removed registers in this run.)

2.27.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.
Replacing $eq cell `$auto$memory_bram.cc:931:replace_memory$933' (isneq) in module `\main' with constant driver `$auto$rtlil.cc:2384:Eq$846 = 1'0'.
Replacing $eq cell `$auto$memory_bram.cc:931:replace_memory$966' (isneq) in module `\main' with constant driver `$auto$rtlil.cc:2384:Eq$835 = 1'0'.
Replacing $mux cell `$auto$memory_bram.cc:957:replace_memory$880' (0) in module `\main' with constant driver `$auto$rtlil.cc:2443:Mux$837 = 1'0'.
Replacing $mux cell `$auto$memory_bram.cc:957:replace_memory$979' (0) in module `\main' with constant driver `$auto$rtlil.cc:2443:Mux$848 = 1'0'.
Replacing $eq cell `$auto$memory_bram.cc:931:replace_memory$944' (isneq) in module `\main' with constant driver `$auto$rtlil.cc:2384:Eq$857 = 1'0'.
Replacing $mux cell `$auto$memory_bram.cc:957:replace_memory$902' (0) in module `\main' with constant driver `$auto$rtlil.cc:2443:Mux$859 = 1'0'.
Replacing port A of $logic_not cell `$auto$memory_bram.cc:931:replace_memory$955' in module `\main' with shorter expression: 2'00 -> 1'0
Replacing $logic_not cell `$auto$memory_bram.cc:931:replace_memory$955' (1'0) in module `\main' with constant driver `$auto$rtlil.cc:2384:Eq$824 = 1'1'.
Replacing $mux cell `$auto$memory_bram.cc:957:replace_memory$913' (1) in module `\main' with constant driver `$auto$rtlil.cc:2443:Mux$826 = 1'0'.

2.27.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.27.13. Executing OPT_DFF pass (perform DFF optimizations).

2.27.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$859.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$848.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$837.
  removing unused non-port wire $auto$rtlil.cc:2443:Mux$826.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$857.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$846.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$835.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$824.
Removed 0 unused cells and 8 unused wires.

2.27.15. Finished fast OPT passes.

2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

2.29. Executing OPT pass (performing simple optimizations).

2.29.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.29.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \main..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $auto$memory_bram.cc:1005:replace_memory$995 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \main.
Performed a total of 0 changes.

2.29.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.29.6. Executing OPT_DFF pass (perform DFF optimizations).

2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..

2.29.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.29.9. Finished OPT passes. (There is nothing left to do.)

2.30. Executing ICE40_WRAPCARRY pass (wrap carries).

2.31. Executing TECHMAP pass (map to technology primitives).

2.31.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.31.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.

2.31.3. Continuing TECHMAP pass.
Cell type mappings to use:
    $xnor: _90_simplemap_bool_ops
    $xor: _90_simplemap_bool_ops
    $or: _90_simplemap_bool_ops
    $and: _90_simplemap_bool_ops
    $not: _90_simplemap_bool_ops
    $reduce_bool: _90_simplemap_reduce_ops
    $reduce_xnor: _90_simplemap_reduce_ops
    $reduce_xor: _90_simplemap_reduce_ops
    $reduce_or: _90_simplemap_reduce_ops
    $reduce_and: _90_simplemap_reduce_ops
    $logic_or: _90_simplemap_logic_ops
    $logic_and: _90_simplemap_logic_ops
    $logic_not: _90_simplemap_logic_ops
    $nex: _90_simplemap_compare_ops
    $ne: _90_simplemap_compare_ops
    $eqx: _90_simplemap_compare_ops
    $eq: _90_simplemap_compare_ops
    $tribuf: _90_simplemap_various
    $mux: _90_simplemap_various
    $concat: _90_simplemap_various
    $slice: _90_simplemap_various
    $pos: _90_simplemap_various
    $dlatchsr: _90_simplemap_registers
    $adlatch: _90_simplemap_registers
    $dlatch: _90_simplemap_registers
    $dffsre: _90_simplemap_registers
    $dffsr: _90_simplemap_registers
    $sdffce: _90_simplemap_registers
    $sdffe: _90_simplemap_registers
    $sdff: _90_simplemap_registers
    $aldffe: _90_simplemap_registers
    $aldff: _90_simplemap_registers
    $adffe: _90_simplemap_registers
    $adff: _90_simplemap_registers
    $dffe: _90_simplemap_registers
    $dff: _90_simplemap_registers
    $ff: _90_simplemap_registers
    $sr: _90_simplemap_registers
    $sshr: _90_shift_ops_shr_shl_sshl_sshr
    $sshl: _90_shift_ops_shr_shl_sshl_sshr
    $shl: _90_shift_ops_shr_shl_sshl_sshr
    $shr: _90_shift_ops_shr_shl_sshl_sshr
    $shiftx: _90_shift_shiftx
    $shift: _90_shift_shiftx
    $fa: _90_fa
    $lcu: _90_lcu
    $macc: _90_macc
    $mul: _90_alumacc
    $neg: _90_alumacc
    $sub: _90_alumacc
    $add: _90_alumacc
    $gt: _90_alumacc
    $ge: _90_alumacc
    $le: _90_alumacc
    $lt: _90_alumacc
    $__div_mod_u: \$__div_mod_u
    $__div_mod_trunc: \$__div_mod_trunc
    $div: _90_div
    $mod: _90_mod
    $__div_mod_floor: \$__div_mod_floor
    $divfloor: _90_divfloor
    $modfloor: _90_modfloor
    $pow: _90_pow
    $pmux: _90_pmux
    $sop: _90_lut
    $lut: _90_lut
    $alu: _80_ice40_alu _90_alu

Parameter \A_SIGNED = 0
Parameter \B_SIGNED = 0
Parameter \A_WIDTH = 1
Parameter \B_WIDTH = 13
Parameter \Y_WIDTH = 13

2.31.4. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'.
Parameter \A_SIGNED = 0
Parameter \B_SIGNED = 0
Parameter \A_WIDTH = 1
Parameter \B_WIDTH = 13
Parameter \Y_WIDTH = 13
Generating RTLIL representation for module `$paramod$215440792383f7884e57d9c95f84e9552d0bf4ac\_80_ice40_alu'.

2.31.5. Continuing TECHMAP pass.
Using template $paramod$215440792383f7884e57d9c95f84e9552d0bf4ac\_80_ice40_alu for cells of type $alu.
Mapping main.$auto$alumacc.cc:485:replace_alu$810 ($alu) using $paramod$215440792383f7884e57d9c95f84e9552d0bf4ac\_80_ice40_alu.
Parameter \WIDTH = 2
Parameter \S_WIDTH = 3

2.31.6. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_pmux'.
Parameter \WIDTH = 2
Parameter \S_WIDTH = 3
Generating RTLIL representation for module `$paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux'.

2.31.7. Continuing TECHMAP pass.
Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux.
Mapping main.$auto$memory_bram.cc:1005:replace_memory$995 ($pmux) using $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux.
Using extmapper simplemap for cells of type $eq.
Mapping main.$auto$memory_bram.cc:931:replace_memory$981 ($eq) with simplemap.
Using extmapper simplemap for cells of type $and.
Mapping main.$auto$memory_bram.cc:987:replace_memory$909 ($and) with simplemap.
Using extmapper simplemap for cells of type $dffe.
Mapping main.$auto$memory_bram.cc:978:replace_memory$886 ($dffe) with simplemap.
Mapping main.$auto$memory_bram.cc:978:replace_memory$908 ($dffe) with simplemap.
Mapping main.$auto$memory_bram.cc:987:replace_memory$887 ($and) with simplemap.
Mapping main.$auto$memory_bram.cc:978:replace_memory$919 ($dffe) with simplemap.
Mapping main.$auto$memory_bram.cc:931:replace_memory$926 ($eq) with simplemap.
Mapping main.$auto$memory_bram.cc:987:replace_memory$964 ($and) with simplemap.
Mapping main.$auto$memory_bram.cc:931:replace_memory$959 ($eq) with simplemap.
Using extmapper simplemap for cells of type $logic_not.
Mapping main.$auto$memory_bram.cc:931:replace_memory$948 ($logic_not) with simplemap.
Using extmapper simplemap for cells of type $dff.
Mapping main.$flatten\SPIPHY.$procdff$750 ($dff) with simplemap.
Mapping main.$flatten\SPIPHY.$procdff$749 ($dff) with simplemap.
Mapping main.$flatten\SPIPHY.$procdff$748 ($dff) with simplemap.
Mapping main.$auto$memory_bram.cc:987:replace_memory$898 ($and) with simplemap.
Mapping main.$flatten\SPIPHY.$and$main.v:73$29 ($and) with simplemap.
Using extmapper simplemap for cells of type $not.
Mapping main.$flatten\SPIPHY.$not$main.v:73$28 ($not) with simplemap.
Mapping main.$techmap$auto$memory_bram.cc:1005:replace_memory$995.$and$/usr/local/bin/../share/yosys/techmap.v:585$1116 ($and) with simplemap.
Mapping main.$techmap$auto$memory_bram.cc:1005:replace_memory$995.$and$/usr/local/bin/../share/yosys/techmap.v:585$1115 ($and) with simplemap.
Using extmapper simplemap for cells of type $pos.
Mapping main.$auto$alumacc.cc:485:replace_alu$810.B_conv ($pos) with simplemap.
Mapping main.$techmap$auto$alumacc.cc:485:replace_alu$810.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1110 ($not) with simplemap.
Using extmapper simplemap for cells of type $mux.
Mapping main.$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111 ($mux) with simplemap.
Using extmapper simplemap for cells of type $xor.
Mapping main.$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112 ($xor) with simplemap.
Mapping main.$techmap$auto$memory_bram.cc:1005:replace_memory$995.$ternary$/usr/local/bin/../share/yosys/techmap.v:597$1114 ($mux) with simplemap.
Using extmapper simplemap for cells of type $reduce_or.
Mapping main.$techmap$auto$memory_bram.cc:1005:replace_memory$995.$reduce_or$/usr/local/bin/../share/yosys/techmap.v:593$1119 ($reduce_or) with simplemap.
Mapping main.$techmap$auto$memory_bram.cc:1005:replace_memory$995.$reduce_or$/usr/local/bin/../share/yosys/techmap.v:593$1118 ($reduce_or) with simplemap.
Mapping main.$techmap$auto$memory_bram.cc:1005:replace_memory$995.$and$/usr/local/bin/../share/yosys/techmap.v:585$1117 ($and) with simplemap.
Mapping main.$auto$alumacc.cc:485:replace_alu$810.A_conv ($pos) with simplemap.
Mapping main.$techmap$auto$memory_bram.cc:1005:replace_memory$995.$reduce_or$/usr/local/bin/../share/yosys/techmap.v:597$1113 ($reduce_or) with simplemap.
No more expansions possible.

2.32. Executing OPT pass (performing simple optimizations).

2.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1122' (xor_buffer) in module `\main' with constant driver `$auto$simplemap.cc:251:simplemap_eqne$1120 [0] = $auto$rtlil.cc:2506:NotGate$1237'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1123' (xor_buffer) in module `\main' with constant driver `$auto$simplemap.cc:251:simplemap_eqne$1120 [1] = $auto$rtlil.cc:2506:NotGate$1239'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1137' (xor_buffer) in module `\main' with constant driver `$auto$simplemap.cc:251:simplemap_eqne$1135 [0] = \SPIPHY.B2H_ADDR [11]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1138' (xor_buffer) in module `\main' with constant driver `$auto$simplemap.cc:251:simplemap_eqne$1135 [1] = $auto$rtlil.cc:2506:NotGate$1241'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1148' (xor_buffer) in module `\main' with constant driver `$auto$simplemap.cc:251:simplemap_eqne$1146 [0] = $auto$rtlil.cc:2506:NotGate$1243'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1149' (xor_buffer) in module `\main' with constant driver `$auto$simplemap.cc:251:simplemap_eqne$1146 [1] = \SPIPHY.B2H_ADDR [12]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1194' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [0] = \SPIPHY.B2H_ADDR [0]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1199' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [5] = \SPIPHY.B2H_ADDR [5]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1212' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [5] = \SPIPHY.B2H_ADDR [5]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1206' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [12] = \SPIPHY.B2H_ADDR [12]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1200' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [6] = \SPIPHY.B2H_ADDR [6]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1213' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [6] = \SPIPHY.B2H_ADDR [6]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1205' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [11] = \SPIPHY.B2H_ADDR [11]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1201' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [7] = \SPIPHY.B2H_ADDR [7]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1214' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [7] = \SPIPHY.B2H_ADDR [7]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1204' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [10] = \SPIPHY.B2H_ADDR [10]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1202' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [8] = \SPIPHY.B2H_ADDR [8]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1215' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [8] = \SPIPHY.B2H_ADDR [8]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1219' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [12] = \SPIPHY.B2H_ADDR [12]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1218' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [11] = \SPIPHY.B2H_ADDR [11]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1203' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [9] = \SPIPHY.B2H_ADDR [9]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1216' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [9] = \SPIPHY.B2H_ADDR [9]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1217' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [10] = \SPIPHY.B2H_ADDR [10]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1196' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [2] = \SPIPHY.B2H_ADDR [2]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1209' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [2] = \SPIPHY.B2H_ADDR [2]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1195' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [1] = \SPIPHY.B2H_ADDR [1]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1207' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [0] = $auto$rtlil.cc:2506:NotGate$1245'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1197' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [3] = \SPIPHY.B2H_ADDR [3]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:278:simplemap_mux$1198' (??0) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y [4] = \SPIPHY.B2H_ADDR [4]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1210' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [3] = \SPIPHY.B2H_ADDR [3]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1211' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [4] = \SPIPHY.B2H_ADDR [4]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:86:simplemap_bitop$1208' (xor_buffer) in module `\main' with constant driver `$techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y [1] = \SPIPHY.B2H_ADDR [1]'.

2.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
  Cell `$auto$opt_expr.cc:607:replace_const_cells$1242' is identical to cell `$auto$simplemap.cc:38:simplemap_not$1192'.
    Redirecting output \Y: $auto$rtlil.cc:2506:NotGate$1243 = $techmap$auto$alumacc.cc:485:replace_alu$810.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1110_Y [11]
    Removing $_NOT_ cell `$auto$opt_expr.cc:607:replace_const_cells$1242' from module `\main'.
  Cell `$auto$opt_expr.cc:607:replace_const_cells$1236' is identical to cell `$auto$simplemap.cc:38:simplemap_not$1192'.
    Redirecting output \Y: $auto$rtlil.cc:2506:NotGate$1237 = $techmap$auto$alumacc.cc:485:replace_alu$810.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1110_Y [11]
    Removing $_NOT_ cell `$auto$opt_expr.cc:607:replace_const_cells$1236' from module `\main'.
  Cell `$auto$opt_expr.cc:607:replace_const_cells$1238' is identical to cell `$auto$opt_expr.cc:607:replace_const_cells$1240'.
    Redirecting output \Y: $auto$rtlil.cc:2506:NotGate$1239 = $auto$rtlil.cc:2506:NotGate$1241
    Removing $_NOT_ cell `$auto$opt_expr.cc:607:replace_const_cells$1238' from module `\main'.
  Cell `$auto$simplemap.cc:38:simplemap_not$1193' is identical to cell `$auto$opt_expr.cc:607:replace_const_cells$1240'.
    Redirecting output \Y: $techmap$auto$alumacc.cc:485:replace_alu$810.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1110_Y [12] = $auto$rtlil.cc:2506:NotGate$1241
    Removing $_NOT_ cell `$auto$simplemap.cc:38:simplemap_not$1193' from module `\main'.
  Cell `$auto$opt_expr.cc:607:replace_const_cells$1244' is identical to cell `$auto$simplemap.cc:38:simplemap_not$1181'.
    Redirecting output \Y: $auto$rtlil.cc:2506:NotGate$1245 = $techmap$auto$alumacc.cc:485:replace_alu$810.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1110_Y [0]
    Removing $_NOT_ cell `$auto$opt_expr.cc:607:replace_const_cells$1244' from module `\main'.
Removed a total of 5 cells.

2.32.3. Executing OPT_DFF pass (perform DFF optimizations).

2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
  removing unused `$_NOT_' cell `$auto$simplemap.cc:38:simplemap_not$1182'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:38:simplemap_not$1181'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:137:simplemap_reduce$1225'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:137:simplemap_reduce$1223'.
  removing unused `$_MUX_' cell `$auto$simplemap.cc:278:simplemap_mux$1221'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:86:simplemap_bitop$1231'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:38:simplemap_not$1190'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:38:simplemap_not$1183'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:38:simplemap_not$1184'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:86:simplemap_bitop$1178'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:86:simplemap_bitop$1180'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:38:simplemap_not$1185'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:38:simplemap_not$1186'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:38:simplemap_not$1187'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:38:simplemap_not$1188'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:38:simplemap_not$1191'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:38:simplemap_not$1189'.
  removing unused non-port wire $flatten\SPIPHY.$0\B2H_ADDR[12:0].
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$841.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$830.
  removing unused non-port wire $auto$memory_bram.cc:977:replace_memory$819.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$851.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$840.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$829.
  removing unused non-port wire $auto$memory_bram.cc:972:replace_memory$818.
  removing unused non-port wire $auto$memory_bram.cc:852:replace_memory$815.
  removing unused non-port wire $auto$alumacc.cc:502:replace_alu$812.
  removing unused non-port wire $auto$alumacc.cc:501:replace_alu$811.
  removing unused non-port wire $techmap$auto$alumacc.cc:485:replace_alu$810.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:73$1112_Y.
  removing unused non-port wire $techmap$auto$alumacc.cc:485:replace_alu$810.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1111_Y.
  removing unused non-port wire $techmap$auto$alumacc.cc:485:replace_alu$810.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:49$1110_Y.
  removing unused non-port wire $auto$alumacc.cc:485:replace_alu$810.BB.
  removing unused non-port wire $auto$alumacc.cc:485:replace_alu$810.AA.
  removing unused non-port wire $auto$alumacc.cc:485:replace_alu$810.B_buf.
  removing unused non-port wire $auto$alumacc.cc:485:replace_alu$810.A_buf.
  removing unused non-port wire $auto$alumacc.cc:485:replace_alu$810._TECHMAP_FAIL_.
  removing unused non-port wire $auto$alumacc.cc:485:replace_alu$810.BI.
  removing unused non-port wire $auto$alumacc.cc:485:replace_alu$810.CI.
  removing unused non-port wire $auto$alumacc.cc:485:replace_alu$810.X.
  removing unused non-port wire $auto$alumacc.cc:485:replace_alu$810.B.
  removing unused non-port wire $auto$alumacc.cc:485:replace_alu$810.A.
  removing unused non-port wire $techmap$auto$memory_bram.cc:1005:replace_memory$995.$reduce_or$/usr/local/bin/../share/yosys/techmap.v:593$1119_Y.
  removing unused non-port wire $techmap$auto$memory_bram.cc:1005:replace_memory$995.$reduce_or$/usr/local/bin/../share/yosys/techmap.v:593$1118_Y.
  removing unused non-port wire $techmap$auto$memory_bram.cc:1005:replace_memory$995.$and$/usr/local/bin/../share/yosys/techmap.v:585$1117_Y.
  removing unused non-port wire $techmap$auto$memory_bram.cc:1005:replace_memory$995.$and$/usr/local/bin/../share/yosys/techmap.v:585$1116_Y.
  removing unused non-port wire $techmap$auto$memory_bram.cc:1005:replace_memory$995.$and$/usr/local/bin/../share/yosys/techmap.v:585$1115_Y.
  removing unused non-port wire $techmap$auto$memory_bram.cc:1005:replace_memory$995.$ternary$/usr/local/bin/../share/yosys/techmap.v:597$1114_Y.
  removing unused non-port wire $auto$memory_bram.cc:1005:replace_memory$995.B_OR[1].B_AND_BITS.
  removing unused non-port wire $auto$memory_bram.cc:1005:replace_memory$995.B_OR[0].B_AND_BITS.
  removing unused non-port wire $auto$memory_bram.cc:1005:replace_memory$995.Y.
  removing unused non-port wire $auto$simplemap.cc:251:simplemap_eqne$1120.
  removing unused non-port wire $auto$simplemap.cc:128:simplemap_reduce$1126.
  removing unused non-port wire $auto$simplemap.cc:251:simplemap_eqne$1135.
  removing unused non-port wire $auto$simplemap.cc:128:simplemap_reduce$1141.
  removing unused non-port wire $auto$simplemap.cc:251:simplemap_eqne$1146.
  removing unused non-port wire $auto$simplemap.cc:128:simplemap_reduce$1152.
  removing unused non-port wire $auto$simplemap.cc:128:simplemap_reduce$1222.
  removing unused non-port wire $auto$simplemap.cc:128:simplemap_reduce$1224.
  removing unused non-port wire $auto$simplemap.cc:128:simplemap_reduce$1228.
  removing unused non-port wire $auto$simplemap.cc:128:simplemap_reduce$1234.
  removing unused non-port wire $auto$rtlil.cc:2506:NotGate$1241.
  removing unused non-port wire $auto$rtlil.cc:2506:NotGate$1243.
  removing unused non-port wire $auto$rtlil.cc:2506:NotGate$1245.
Removed 17 unused cells and 46 unused wires.

2.32.5. Finished fast OPT passes.

2.33. Executing ICE40_OPT pass (performing simple optimizations).

2.33.1. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) main.$auto$alumacc.cc:485:replace_alu$810.slice[0].carry: CO=\SPIPHY.B2H_ADDR [0]

2.33.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.33.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.33.4. Executing OPT_DFF pass (perform DFF optimizations).

2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..

2.33.6. Rerunning OPT passes. (Removed registers in this run.)

2.33.7. Running ICE40 specific optimizations.

2.33.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.33.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.33.10. Executing OPT_DFF pass (perform DFF optimizations).

2.33.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..

2.33.12. Finished OPT passes. (There is nothing left to do.)

2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

2.35. Executing TECHMAP pass (map to technology primitives).

2.35.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

2.35.2. Continuing TECHMAP pass.
Cell type mappings to use:
    $_DFF_N_: \$_DFF_N_
    $_DFF_P_: \$_DFF_P_
    $_DFFE_NP_: \$_DFFE_NP_
    $_DFFE_PP_: \$_DFFE_PP_
    $_DFF_NP0_: \$_DFF_NP0_
    $_DFF_NP1_: \$_DFF_NP1_
    $_DFF_PP0_: \$_DFF_PP0_
    $_DFF_PP1_: \$_DFF_PP1_
    $_DFFE_NP0P_: \$_DFFE_NP0P_
    $_DFFE_NP1P_: \$_DFFE_NP1P_
    $_DFFE_PP0P_: \$_DFFE_PP0P_
    $_DFFE_PP1P_: \$_DFFE_PP1P_
    $_SDFF_NP0_: \$_SDFF_NP0_
    $_SDFF_NP1_: \$_SDFF_NP1_
    $_SDFF_PP0_: \$_SDFF_PP0_
    $_SDFF_PP1_: \$_SDFF_PP1_
    $_SDFFCE_NP0P_: \$_SDFFCE_NP0P_
    $_SDFFCE_NP1P_: \$_SDFFCE_NP1P_
    $_SDFFCE_PP0P_: \$_SDFFCE_PP0P_
    $_SDFFCE_PP1P_: \$_SDFFCE_PP1P_

Using template \$_DFF_P_ for cells of type $_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1166 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1169 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1167 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1159 ($_DFF_P_) using \$_DFF_P_.
Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
Mapping main.$auto$ff.cc:262:slice$1131 ($_DFFE_PP_) using \$_DFFE_PP_.
Mapping main.$auto$ff.cc:262:slice$1132 ($_DFFE_PP_) using \$_DFFE_PP_.
Mapping main.$auto$ff.cc:262:slice$1134 ($_DFFE_PP_) using \$_DFFE_PP_.
Mapping main.$auto$ff.cc:262:slice$1161 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1162 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1163 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1164 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1165 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1172 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1171 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1170 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1160 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1173 ($_DFF_P_) using \$_DFF_P_.
Mapping main.$auto$ff.cc:262:slice$1168 ($_DFF_P_) using \$_DFF_P_.
No more expansions possible.

2.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping main.$auto$alumacc.cc:485:replace_alu$810.slice[0].carry ($lut).

2.38. Executing ICE40_OPT pass (performing simple optimizations).

2.38.1. Running ICE40 specific optimizations.

2.38.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1271' (010) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1264 [6] = 1'0'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1267' (100) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1264 [2] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1268' (010) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1264 [3] = 1'0'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1275' (101) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1273 [1] = 1'0'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1265' (010) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1264 [0] = 1'0'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1272' (100) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1264 [7] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1266' (100) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1264 [1] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1277' (011) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1273 [3] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1270' (010) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1264 [5] = 1'0'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1269' (100) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1264 [4] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1276' (101) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1273 [2] = 1'0'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1280' (01?) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1278 [1] = \SPIPHY.B2H_ADDR [0]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1274' (011) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1273 [0] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:312:simplemap_lut$1282' (??0) in module `\main' with constant driver `$auto$simplemap.cc:310:simplemap_lut$1281 = $auto$simplemap.cc:310:simplemap_lut$1278 [0]'.

2.38.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.38.4. Executing OPT_DFF pass (perform DFF optimizations).

2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..
  removing unused non-port wire $techmap1246$auto$ff.cc:262:slice$1166._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1246$auto$ff.cc:262:slice$1166.Q.
  removing unused non-port wire $techmap1246$auto$ff.cc:262:slice$1166.C.
  removing unused non-port wire $techmap1246$auto$ff.cc:262:slice$1166.D.
  removing unused non-port wire $techmap1247$auto$ff.cc:262:slice$1169._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1247$auto$ff.cc:262:slice$1169.Q.
  removing unused non-port wire $techmap1247$auto$ff.cc:262:slice$1169.C.
  removing unused non-port wire $techmap1247$auto$ff.cc:262:slice$1169.D.
  removing unused non-port wire $techmap1248$auto$ff.cc:262:slice$1167._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1248$auto$ff.cc:262:slice$1167.Q.
  removing unused non-port wire $techmap1248$auto$ff.cc:262:slice$1167.C.
  removing unused non-port wire $techmap1248$auto$ff.cc:262:slice$1167.D.
  removing unused non-port wire $techmap1249$auto$ff.cc:262:slice$1159._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1249$auto$ff.cc:262:slice$1159.Q.
  removing unused non-port wire $techmap1249$auto$ff.cc:262:slice$1159.C.
  removing unused non-port wire $techmap1249$auto$ff.cc:262:slice$1159.D.
  removing unused non-port wire $techmap1250$auto$ff.cc:262:slice$1131._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1250$auto$ff.cc:262:slice$1131.Q.
  removing unused non-port wire $techmap1250$auto$ff.cc:262:slice$1131.E.
  removing unused non-port wire $techmap1250$auto$ff.cc:262:slice$1131.C.
  removing unused non-port wire $techmap1250$auto$ff.cc:262:slice$1131.D.
  removing unused non-port wire $techmap1251$auto$ff.cc:262:slice$1132._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1251$auto$ff.cc:262:slice$1132.Q.
  removing unused non-port wire $techmap1251$auto$ff.cc:262:slice$1132.E.
  removing unused non-port wire $techmap1251$auto$ff.cc:262:slice$1132.C.
  removing unused non-port wire $techmap1251$auto$ff.cc:262:slice$1132.D.
  removing unused non-port wire $techmap1252$auto$ff.cc:262:slice$1134._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1252$auto$ff.cc:262:slice$1134.Q.
  removing unused non-port wire $techmap1252$auto$ff.cc:262:slice$1134.E.
  removing unused non-port wire $techmap1252$auto$ff.cc:262:slice$1134.C.
  removing unused non-port wire $techmap1252$auto$ff.cc:262:slice$1134.D.
  removing unused non-port wire $techmap1253$auto$ff.cc:262:slice$1161._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1253$auto$ff.cc:262:slice$1161.Q.
  removing unused non-port wire $techmap1253$auto$ff.cc:262:slice$1161.C.
  removing unused non-port wire $techmap1253$auto$ff.cc:262:slice$1161.D.
  removing unused non-port wire $techmap1254$auto$ff.cc:262:slice$1162._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1254$auto$ff.cc:262:slice$1162.Q.
  removing unused non-port wire $techmap1254$auto$ff.cc:262:slice$1162.C.
  removing unused non-port wire $techmap1254$auto$ff.cc:262:slice$1162.D.
  removing unused non-port wire $techmap1255$auto$ff.cc:262:slice$1163._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1255$auto$ff.cc:262:slice$1163.Q.
  removing unused non-port wire $techmap1255$auto$ff.cc:262:slice$1163.C.
  removing unused non-port wire $techmap1255$auto$ff.cc:262:slice$1163.D.
  removing unused non-port wire $techmap1256$auto$ff.cc:262:slice$1164._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1256$auto$ff.cc:262:slice$1164.Q.
  removing unused non-port wire $techmap1256$auto$ff.cc:262:slice$1164.C.
  removing unused non-port wire $techmap1256$auto$ff.cc:262:slice$1164.D.
  removing unused non-port wire $techmap1257$auto$ff.cc:262:slice$1165._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1257$auto$ff.cc:262:slice$1165.Q.
  removing unused non-port wire $techmap1257$auto$ff.cc:262:slice$1165.C.
  removing unused non-port wire $techmap1257$auto$ff.cc:262:slice$1165.D.
  removing unused non-port wire $techmap1258$auto$ff.cc:262:slice$1172._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1258$auto$ff.cc:262:slice$1172.Q.
  removing unused non-port wire $techmap1258$auto$ff.cc:262:slice$1172.C.
  removing unused non-port wire $techmap1258$auto$ff.cc:262:slice$1172.D.
  removing unused non-port wire $techmap1259$auto$ff.cc:262:slice$1171._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1259$auto$ff.cc:262:slice$1171.Q.
  removing unused non-port wire $techmap1259$auto$ff.cc:262:slice$1171.C.
  removing unused non-port wire $techmap1259$auto$ff.cc:262:slice$1171.D.
  removing unused non-port wire $techmap1260$auto$ff.cc:262:slice$1170._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1260$auto$ff.cc:262:slice$1170.Q.
  removing unused non-port wire $techmap1260$auto$ff.cc:262:slice$1170.C.
  removing unused non-port wire $techmap1260$auto$ff.cc:262:slice$1170.D.
  removing unused non-port wire $techmap1261$auto$ff.cc:262:slice$1160._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1261$auto$ff.cc:262:slice$1160.Q.
  removing unused non-port wire $techmap1261$auto$ff.cc:262:slice$1160.C.
  removing unused non-port wire $techmap1261$auto$ff.cc:262:slice$1160.D.
  removing unused non-port wire $techmap1262$auto$ff.cc:262:slice$1173._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1262$auto$ff.cc:262:slice$1173.Q.
  removing unused non-port wire $techmap1262$auto$ff.cc:262:slice$1173.C.
  removing unused non-port wire $techmap1262$auto$ff.cc:262:slice$1173.D.
  removing unused non-port wire $techmap1263$auto$ff.cc:262:slice$1168._TECHMAP_REMOVEINIT_Q_.
  removing unused non-port wire $techmap1263$auto$ff.cc:262:slice$1168.Q.
  removing unused non-port wire $techmap1263$auto$ff.cc:262:slice$1168.C.
  removing unused non-port wire $techmap1263$auto$ff.cc:262:slice$1168.D.
  removing unused non-port wire $auto$simplemap.cc:310:simplemap_lut$1264.
  removing unused non-port wire $auto$simplemap.cc:310:simplemap_lut$1273.
  removing unused non-port wire $auto$simplemap.cc:310:simplemap_lut$1278.
  removing unused non-port wire $auto$simplemap.cc:310:simplemap_lut$1281.
Removed 0 unused cells and 79 unused wires.

2.38.6. Rerunning OPT passes. (Removed registers in this run.)

2.38.7. Running ICE40 specific optimizations.

2.38.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module main.

2.38.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\main'.
Removed a total of 0 cells.

2.38.10. Executing OPT_DFF pass (perform DFF optimizations).

2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \main..

2.38.12. Finished OPT passes. (There is nothing left to do.)

2.39. Executing TECHMAP pass (map to technology primitives).

2.39.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

2.39.2. Continuing TECHMAP pass.
Cell type mappings to use:
    $_DLATCH_N_: \$_DLATCH_N_
    $_DLATCH_P_: \$_DLATCH_P_

No more expansions possible.

2.40. Executing ABC pass (technology mapping using ABC).

2.40.1. Extracting gate netlist of module `\main' to `<abc-temp-dir>/input.blif'..
Extracted 25 gates and 38 wires to a netlist network with 13 inputs and 10 outputs.

2.40.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + strash 
ABC: + dch -f 
ABC: + if 
ABC: + mfs2 
ABC: + lutpack -S 1 
ABC: + dress 
ABC: Total number of equiv classes                =      12.
ABC: Participating nodes from both networks       =      25.
ABC: Participating nodes from the first network   =      11. (  84.62 % of nodes)
ABC: Participating nodes from the second network  =      14. ( 107.69 % of nodes)
ABC: Node pairs (any polarity)                    =      11. (  84.62 % of names can be moved)
ABC: Node pairs (same polarity)                   =      10. (  76.92 % of names can be moved)
ABC: Total runtime =     0.01 sec
ABC: + write_blif <abc-temp-dir>/output.blif 

2.40.1.2. Re-integrating ABC results.
ABC RESULTS:              $lut cells:       12
ABC RESULTS:        internal signals:       15
ABC RESULTS:           input signals:       13
ABC RESULTS:          output signals:       10
Removing temp directory.

2.41. Executing ICE40_WRAPCARRY pass (wrap carries).

2.42. Executing TECHMAP pass (map to technology primitives).

2.42.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

2.42.2. Continuing TECHMAP pass.
Cell type mappings to use:
    $_DFF_N_: \$_DFF_N_
    $_DFF_P_: \$_DFF_P_
    $_DFFE_NP_: \$_DFFE_NP_
    $_DFFE_PP_: \$_DFFE_PP_
    $_DFF_NP0_: \$_DFF_NP0_
    $_DFF_NP1_: \$_DFF_NP1_
    $_DFF_PP0_: \$_DFF_PP0_
    $_DFF_PP1_: \$_DFF_PP1_
    $_DFFE_NP0P_: \$_DFFE_NP0P_
    $_DFFE_NP1P_: \$_DFFE_NP1P_
    $_DFFE_PP0P_: \$_DFFE_PP0P_
    $_DFFE_PP1P_: \$_DFFE_PP1P_
    $_SDFF_NP0_: \$_SDFF_NP0_
    $_SDFF_NP1_: \$_SDFF_NP1_
    $_SDFF_PP0_: \$_SDFF_PP0_
    $_SDFF_PP1_: \$_SDFF_PP1_
    $_SDFFCE_NP0P_: \$_SDFFCE_NP0P_
    $_SDFFCE_NP1P_: \$_SDFFCE_NP1P_
    $_SDFFCE_PP0P_: \$_SDFFCE_PP0P_
    $_SDFFCE_PP1P_: \$_SDFFCE_PP1P_

No more expansions possible.
Finding unused cells or wires in module \main..
  removing unused `\SB_CARRY' cell `$auto$alumacc.cc:485:replace_alu$810.slice[12].carry'.
  removing unused non-port wire $techmap$auto$memory_bram.cc:1005:replace_memory$995.$reduce_or$/usr/local/bin/../share/yosys/techmap.v:597$1113_Y.
  removing unused non-port wire $flatten\SPIPHY.$not$main.v:73$28_Y.
  removing unused non-port wire $flatten\SPIPHY.$and$main.v:73$29_Y.
  removing unused non-port wire $auto$simplemap.cc:257:simplemap_eqne$1150.
  removing unused non-port wire $auto$simplemap.cc:257:simplemap_eqne$1139.
  removing unused non-port wire $auto$simplemap.cc:257:simplemap_eqne$1124.
  removing unused non-port wire $auto$simplemap.cc:169:logic_reduce$1156.
  removing unused non-port wire $auto$simplemap.cc:128:simplemap_reduce$1232.
  removing unused non-port wire $auto$simplemap.cc:128:simplemap_reduce$1226.
  removing unused non-port wire $auto$rtlil.cc:2506:NotGate$1239.
  removing unused non-port wire $auto$rtlil.cc:2506:NotGate$1237.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$850.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$839.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$828.
  removing unused non-port wire $auto$rtlil.cc:2384:Eq$817.
  removing unused non-port wire $auto$rtlil.cc:2376:And$855.
  removing unused non-port wire $auto$rtlil.cc:2376:And$844.
  removing unused non-port wire $auto$rtlil.cc:2376:And$833.
  removing unused non-port wire $auto$rtlil.cc:2376:And$822.
  removing unused non-port wire $auto$memory_bram.cc:1005:replace_memory$995.Y_B.
  removing unused non-port wire $auto$memory_bram.cc:1005:replace_memory$995.B_AND_S.
  removing unused non-port wire $auto$alumacc.cc:485:replace_alu$810.CO.
  removing unused non-port wire $abc$1286$auto$alumacc.cc:485:replace_alu$810.Y[0].
  removing unused non-port wire $abc$1286$capRam.BRAM_OUT[0].
  removing unused non-port wire $abc$1286$auto$memory_bram.cc:1005:replace_memory$995.B[4].
  removing unused non-port wire $abc$1286$auto$memory_bram.cc:1005:replace_memory$995.B[0].
  removing unused non-port wire $abc$1286$auto$memory_bram.cc:1005:replace_memory$995.B[2].
  removing unused non-port wire $abc$1286$SCK.
  removing unused non-port wire $abc$1286$SPIPHY.R_CE.
  removing unused non-port wire $abc$1286$CE.
  removing unused non-port wire $abc$1286$SPIPHY.B2H_ADDR[0].
  removing unused non-port wire $abc$1286$auto$memory_bram.cc:1005:replace_memory$995.A[0].
  removing unused non-port wire $abc$1286$auto$memory_bram.cc:1005:replace_memory$995.S[2].
  removing unused non-port wire $abc$1286$auto$memory_bram.cc:1005:replace_memory$995.S[1].
  removing unused non-port wire $abc$1286$auto$memory_bram.cc:1005:replace_memory$995.S[0].
  removing unused non-port wire $abc$1286$SPIPHY.B2H_ADDR[11].
  removing unused non-port wire $abc$1286$SPIPHY.B2H_ADDR[12].
Removed 1 unused cells and 37 unused wires.

2.43. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Found $lut\WIDTH=2 cell main.$abc$1286$auto$blifparse.cc:515:parse_blif$1287.
  Cell implements a 2-LUT.
Found $lut\WIDTH=2 cell main.$abc$1286$auto$blifparse.cc:515:parse_blif$1288.
  Cell implements a 2-LUT.
Found $lut\WIDTH=2 cell main.$abc$1286$auto$blifparse.cc:515:parse_blif$1289.
  Cell implements a 2-LUT.
Found $lut\WIDTH=4 cell main.$abc$1286$auto$blifparse.cc:515:parse_blif$1290.
  Cell implements a 4-LUT.
Found $lut\WIDTH=4 cell main.$abc$1286$auto$blifparse.cc:515:parse_blif$1291.
  Cell implements a 4-LUT.
Found $lut\WIDTH=4 cell main.$abc$1286$auto$blifparse.cc:515:parse_blif$1292.
  Cell implements a 4-LUT.
Found $lut\WIDTH=2 cell main.$abc$1286$auto$blifparse.cc:515:parse_blif$1293.
  Cell implements a 2-LUT.
Found $lut\WIDTH=2 cell main.$abc$1286$auto$blifparse.cc:515:parse_blif$1294.
  Cell implements a 2-LUT.
Found $lut\WIDTH=2 cell main.$abc$1286$auto$blifparse.cc:515:parse_blif$1295.
  Cell implements a 2-LUT.
Found $lut\WIDTH=3 cell main.$abc$1286$auto$blifparse.cc:515:parse_blif$1296.
  Cell implements a 3-LUT.
Found $lut\WIDTH=2 cell main.$abc$1286$auto$blifparse.cc:515:parse_blif$1297.
  Cell implements a 2-LUT.
Found $lut\WIDTH=1 cell main.$abc$1286$auto$blifparse.cc:515:parse_blif$1298.
  Cell implements a 1-LUT.
Found $lut\WIDTH=4 cell main.$auto$ice40_wrapcarry.cc:125:execute$1300.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[9].carry.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[10].carry.
  Cell implements a 3-LUT.
Found $lut\WIDTH=4 cell main.$auto$ice40_wrapcarry.cc:125:execute$1302.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[10].carry.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[11].carry.
  Cell implements a 3-LUT.
Found $lut\WIDTH=4 cell main.$auto$ice40_wrapcarry.cc:125:execute$1304.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[11].carry.
  Cell implements a 2-LUT.
Found $lut\WIDTH=4 cell main.$auto$ice40_wrapcarry.cc:125:execute$1306.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[1].carry.
  Cell implements a 3-LUT.
Found $lut\WIDTH=4 cell main.$auto$ice40_wrapcarry.cc:125:execute$1308.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[1].carry.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[2].carry.
  Cell implements a 3-LUT.
Found $lut\WIDTH=4 cell main.$auto$ice40_wrapcarry.cc:125:execute$1310.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[2].carry.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[3].carry.
  Cell implements a 3-LUT.
Found $lut\WIDTH=4 cell main.$auto$ice40_wrapcarry.cc:125:execute$1312.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[3].carry.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[4].carry.
  Cell implements a 3-LUT.
Found $lut\WIDTH=4 cell main.$auto$ice40_wrapcarry.cc:125:execute$1314.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[4].carry.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[5].carry.
  Cell implements a 3-LUT.
Found $lut\WIDTH=4 cell main.$auto$ice40_wrapcarry.cc:125:execute$1316.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[5].carry.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[6].carry.
  Cell implements a 3-LUT.
Found $lut\WIDTH=4 cell main.$auto$ice40_wrapcarry.cc:125:execute$1318.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[6].carry.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[7].carry.
  Cell implements a 3-LUT.
Found $lut\WIDTH=4 cell main.$auto$ice40_wrapcarry.cc:125:execute$1320.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[7].carry.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[8].carry.
  Cell implements a 3-LUT.
Found $lut\WIDTH=4 cell main.$auto$ice40_wrapcarry.cc:125:execute$1322.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[8].carry.
  LUT has legal connection to \SB_CARRY cell main.$auto$alumacc.cc:485:replace_alu$810.slice[9].carry.
  Cell implements a 3-LUT.
Number of LUTs:       24
  1-LUT                1
  2-LUT                8
  3-LUT               12
  4-LUT                3
  with \SB_CARRY    (#0)   11
  with \SB_CARRY    (#1)   11

Eliminating LUTs.
Number of LUTs:       24
  1-LUT                1
  2-LUT                8
  3-LUT               12
  4-LUT                3
  with \SB_CARRY    (#0)   11
  with \SB_CARRY    (#1)   11

Combining LUTs.
Found main.$abc$1286$auto$blifparse.cc:515:parse_blif$1292 (cell A) feeding main.$abc$1286$auto$blifparse.cc:515:parse_blif$1290 (cell B).
  Cell A is a 4-LUT. Cell B is a 4-LUT.
  Cells share 0 input(s) and can be merged into one 7-LUT.
  Not combining LUTs into cell A (combined LUT wider than cell A).
  Not combining LUTs into cell B (combined LUT wider than cell B).
  Cannot combine LUTs.
Found main.$abc$1286$auto$blifparse.cc:515:parse_blif$1291 (cell A) feeding main.$abc$1286$auto$blifparse.cc:515:parse_blif$1290 (cell B).
  Cell A is a 4-LUT. Cell B is a 4-LUT.
  Cells share 1 input(s) and can be merged into one 6-LUT.
  Not combining LUTs into cell A (combined LUT wider than cell A).
  Not combining LUTs into cell B (combined LUT wider than cell B).
  Cannot combine LUTs.
Number of LUTs:       24
  1-LUT                1
  2-LUT                8
  3-LUT               12
  4-LUT                3
  with \SB_CARRY    (#0)   11
  with \SB_CARRY    (#1)   11

Eliminated 0 LUTs.
Combined 0 LUTs.

2.44. Executing TECHMAP pass (map to technology primitives).

2.44.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

2.44.2. Continuing TECHMAP pass.
Cell type mappings to use:
    $lut: \$lut

Parameter \WIDTH = 2
Parameter \LUT = 4'0001

2.44.3. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 2
Parameter \LUT = 4'0001
Generating RTLIL representation for module `$paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001'.

2.44.4. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Mapping main.$abc$1286$auto$blifparse.cc:515:parse_blif$1289 ($lut) using $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001.
Parameter \WIDTH = 2
Parameter \LUT = 4'1000

2.44.5. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 2
Parameter \LUT = 4'1000
Generating RTLIL representation for module `$paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000'.

2.44.6. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Mapping main.$abc$1286$auto$blifparse.cc:515:parse_blif$1293 ($lut) using $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000.
Parameter \WIDTH = 4
Parameter \LUT = 16'0110100110010110

2.44.7. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 4
Parameter \LUT = 16'0110100110010110
Generating RTLIL representation for module `$paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut'.

2.44.8. Continuing TECHMAP pass.
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
Mapping main.$auto$ice40_wrapcarry.cc:125:execute$1302 ($lut) using $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut.
Mapping main.$auto$ice40_wrapcarry.cc:125:execute$1306 ($lut) using $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut.
Mapping main.$auto$ice40_wrapcarry.cc:125:execute$1320 ($lut) using $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut.
Mapping main.$auto$ice40_wrapcarry.cc:125:execute$1322 ($lut) using $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut.
Mapping main.$auto$ice40_wrapcarry.cc:125:execute$1304 ($lut) using $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut.
Parameter \WIDTH = 4
Parameter \LUT = 16'0000011101110111

2.44.9. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 4
Parameter \LUT = 16'0000011101110111
Generating RTLIL representation for module `$paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut'.

2.44.10. Continuing TECHMAP pass.
Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut.
Mapping main.$abc$1286$auto$blifparse.cc:515:parse_blif$1292 ($lut) using $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut.
Parameter \WIDTH = 4
Parameter \LUT = 16'0000000100000000

2.44.11. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 4
Parameter \LUT = 16'0000000100000000
Generating RTLIL representation for module `$paramod$6e238df02989b317f10820a22773676e71120644\$lut'.

2.44.12. Continuing TECHMAP pass.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Mapping main.$abc$1286$auto$blifparse.cc:515:parse_blif$1291 ($lut) using $paramod$6e238df02989b317f10820a22773676e71120644\$lut.
Parameter \WIDTH = 4
Parameter \LUT = 16'1111100011111111

2.44.13. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 4
Parameter \LUT = 16'1111100011111111
Generating RTLIL representation for module `$paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut'.

2.44.14. Continuing TECHMAP pass.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Mapping main.$abc$1286$auto$blifparse.cc:515:parse_blif$1290 ($lut) using $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut.
Parameter \WIDTH = 2
Parameter \LUT = 4'0100

2.44.15. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 2
Parameter \LUT = 4'0100
Generating RTLIL representation for module `$paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100'.

2.44.16. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Mapping main.$abc$1286$auto$blifparse.cc:515:parse_blif$1288 ($lut) using $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100.
Parameter \WIDTH = 3
Parameter \LUT = 8'10000000

2.44.17. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 3
Parameter \LUT = 8'10000000
Generating RTLIL representation for module `$paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000'.

2.44.18. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Mapping main.$abc$1286$auto$blifparse.cc:515:parse_blif$1296 ($lut) using $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000.
Mapping main.$abc$1286$auto$blifparse.cc:515:parse_blif$1297 ($lut) using $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100.
Mapping main.$abc$1286$auto$blifparse.cc:515:parse_blif$1287 ($lut) using $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100.
Mapping main.$abc$1286$auto$blifparse.cc:515:parse_blif$1294 ($lut) using $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000.
Mapping main.$auto$ice40_wrapcarry.cc:125:execute$1310 ($lut) using $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut.
Mapping main.$auto$ice40_wrapcarry.cc:125:execute$1312 ($lut) using $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut.
Mapping main.$auto$ice40_wrapcarry.cc:125:execute$1308 ($lut) using $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut.
Mapping main.$auto$ice40_wrapcarry.cc:125:execute$1316 ($lut) using $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut.
Mapping main.$auto$ice40_wrapcarry.cc:125:execute$1300 ($lut) using $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut.
Mapping main.$auto$ice40_wrapcarry.cc:125:execute$1318 ($lut) using $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut.
Parameter \WIDTH = 1
Parameter \LUT = 2'01

2.44.19. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 1
Parameter \LUT = 2'01
Generating RTLIL representation for module `$paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01'.

2.44.20. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Mapping main.$abc$1286$auto$blifparse.cc:515:parse_blif$1298 ($lut) using $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01.
Mapping main.$auto$ice40_wrapcarry.cc:125:execute$1314 ($lut) using $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut.
Mapping main.$abc$1286$auto$blifparse.cc:515:parse_blif$1295 ($lut) using $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000.
No more expansions possible.
Finding unused cells or wires in module \main..
  removing unused non-port wire $abc$1286$new_n29_.
  removing unused non-port wire $abc$1286$auto$simplemap.cc:128:simplemap_reduce$1226_new_inv_.
  removing unused non-port wire $abc$1286$auto$rtlil.cc:2384:Eq$839.
  removing unused non-port wire $abc$1286$auto$rtlil.cc:2384:Eq$828.
  removing unused non-port wire $abc$1286$auto$rtlil.cc:2384:Eq$817.
  removing unused non-port wire $techmap1323$abc$1286$auto$blifparse.cc:515:parse_blif$1289.Y.
  removing unused non-port wire $techmap1323$abc$1286$auto$blifparse.cc:515:parse_blif$1289.A.
  removing unused non-port wire $techmap1324$abc$1286$auto$blifparse.cc:515:parse_blif$1293.Y.
  removing unused non-port wire $techmap1325$auto$ice40_wrapcarry.cc:125:execute$1302.Y.
  removing unused non-port wire $techmap1325$auto$ice40_wrapcarry.cc:125:execute$1302.A.
  removing unused non-port wire $techmap1326$auto$ice40_wrapcarry.cc:125:execute$1306.Y.
  removing unused non-port wire $techmap1326$auto$ice40_wrapcarry.cc:125:execute$1306.A.
  removing unused non-port wire $techmap1327$auto$ice40_wrapcarry.cc:125:execute$1320.Y.
  removing unused non-port wire $techmap1327$auto$ice40_wrapcarry.cc:125:execute$1320.A.
  removing unused non-port wire $techmap1328$auto$ice40_wrapcarry.cc:125:execute$1322.Y.
  removing unused non-port wire $techmap1328$auto$ice40_wrapcarry.cc:125:execute$1322.A.
  removing unused non-port wire $techmap1329$auto$ice40_wrapcarry.cc:125:execute$1304.Y.
  removing unused non-port wire $techmap1329$auto$ice40_wrapcarry.cc:125:execute$1304.A.
  removing unused non-port wire $techmap1330$abc$1286$auto$blifparse.cc:515:parse_blif$1292.Y.
  removing unused non-port wire $techmap1330$abc$1286$auto$blifparse.cc:515:parse_blif$1292.A.
  removing unused non-port wire $techmap1331$abc$1286$auto$blifparse.cc:515:parse_blif$1291.Y.
  removing unused non-port wire $techmap1331$abc$1286$auto$blifparse.cc:515:parse_blif$1291.A.
  removing unused non-port wire $techmap1332$abc$1286$auto$blifparse.cc:515:parse_blif$1290.Y.
  removing unused non-port wire $techmap1333$abc$1286$auto$blifparse.cc:515:parse_blif$1288.Y.
  removing unused non-port wire $techmap1333$abc$1286$auto$blifparse.cc:515:parse_blif$1288.A.
  removing unused non-port wire $techmap1334$abc$1286$auto$blifparse.cc:515:parse_blif$1296.Y.
  removing unused non-port wire $techmap1334$abc$1286$auto$blifparse.cc:515:parse_blif$1296.A.
  removing unused non-port wire $techmap1335$abc$1286$auto$blifparse.cc:515:parse_blif$1297.Y.
  removing unused non-port wire $techmap1335$abc$1286$auto$blifparse.cc:515:parse_blif$1297.A.
  removing unused non-port wire $techmap1336$abc$1286$auto$blifparse.cc:515:parse_blif$1287.Y.
  removing unused non-port wire $techmap1336$abc$1286$auto$blifparse.cc:515:parse_blif$1287.A.
  removing unused non-port wire $techmap1337$abc$1286$auto$blifparse.cc:515:parse_blif$1294.Y.
  removing unused non-port wire $techmap1338$auto$ice40_wrapcarry.cc:125:execute$1310.Y.
  removing unused non-port wire $techmap1338$auto$ice40_wrapcarry.cc:125:execute$1310.A.
  removing unused non-port wire $techmap1339$auto$ice40_wrapcarry.cc:125:execute$1312.Y.
  removing unused non-port wire $techmap1339$auto$ice40_wrapcarry.cc:125:execute$1312.A.
  removing unused non-port wire $techmap1340$auto$ice40_wrapcarry.cc:125:execute$1308.Y.
  removing unused non-port wire $techmap1340$auto$ice40_wrapcarry.cc:125:execute$1308.A.
  removing unused non-port wire $techmap1341$auto$ice40_wrapcarry.cc:125:execute$1316.Y.
  removing unused non-port wire $techmap1341$auto$ice40_wrapcarry.cc:125:execute$1316.A.
  removing unused non-port wire $techmap1342$auto$ice40_wrapcarry.cc:125:execute$1300.Y.
  removing unused non-port wire $techmap1342$auto$ice40_wrapcarry.cc:125:execute$1300.A.
  removing unused non-port wire $techmap1343$auto$ice40_wrapcarry.cc:125:execute$1318.Y.
  removing unused non-port wire $techmap1343$auto$ice40_wrapcarry.cc:125:execute$1318.A.
  removing unused non-port wire $techmap1344$abc$1286$auto$blifparse.cc:515:parse_blif$1298.Y.
  removing unused non-port wire $techmap1344$abc$1286$auto$blifparse.cc:515:parse_blif$1298.A.
  removing unused non-port wire $techmap1345$auto$ice40_wrapcarry.cc:125:execute$1314.Y.
  removing unused non-port wire $techmap1345$auto$ice40_wrapcarry.cc:125:execute$1314.A.
  removing unused non-port wire $techmap1346$abc$1286$auto$blifparse.cc:515:parse_blif$1295.Y.
Removed 0 unused cells and 49 unused wires.

2.45. Executing AUTONAME pass.
Rename cell $auto$ff.cc:262:slice$1173 in main to SPIPHY.MISO_SB_DFF_Q.
Rename cell $auto$ff.cc:262:slice$1172 in main to SPIPHY.B2H_ADDR_SB_DFF_Q.
Rename cell $auto$ff.cc:262:slice$1171 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_1.
Rename cell $auto$ff.cc:262:slice$1170 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_2.
Rename cell $auto$ff.cc:262:slice$1169 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_3.
Rename cell $auto$ff.cc:262:slice$1168 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_4.
Rename cell $auto$ff.cc:262:slice$1167 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_5.
Rename cell $auto$ff.cc:262:slice$1166 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_6.
Rename cell $auto$ff.cc:262:slice$1165 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_7.
Rename cell $auto$ff.cc:262:slice$1164 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_8.
Rename cell $auto$ff.cc:262:slice$1163 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_9.
Rename cell $auto$ff.cc:262:slice$1162 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_10.
Rename cell $auto$ff.cc:262:slice$1161 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_11.
Rename cell $auto$ff.cc:262:slice$1160 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_12.
Rename cell $auto$ff.cc:262:slice$1159 in main to SPIPHY.R_CE_SB_DFF_Q.
Rename cell $abc$1286$auto$blifparse.cc:515:parse_blif$1290 in main to capRam.BRAM_OUT_SB_LUT4_O.
Rename wire $auto$memory_bram.cc:1005:replace_memory$995.A in main to capRam.mem1.0.3.0_RDATA.
Rename wire $techmap1009\capRam.mem1.0.3.0.A1DATA_16 in main to capRam.mem1.0.3.0_RDATA_1.
Rename wire $techmap1011\capRam.mem1.0.2.0.A1DATA_16 in main to capRam.mem1.0.2.0_RDATA.
Rename wire $techmap1004\capRam.mem1.0.1.0.A1DATA_16 in main to capRam.mem1.0.1.0_RDATA.
Rename wire $auto$memory_bram.cc:1005:replace_memory$995.B in main to capRam.mem1.0.0.0_RDATA.
Rename wire $techmap1002\capRam.mem1.0.0.0.A1DATA_16 in main to capRam.mem1.0.0.0_RDATA_1.
Rename cell $abc$1286$auto$blifparse.cc:515:parse_blif$1297 in main to CE_SB_LUT4_I2.
Rename wire $abc$1286$auto$rtlil.cc:2376:And$855 in main to capRam.mem1.0.3.0_RCLKE.
Rename wire $abc$1286$auto$rtlil.cc:2376:And$844 in main to capRam.mem1.0.2.0_RCLKE.
Rename wire $abc$1286$auto$rtlil.cc:2376:And$833 in main to capRam.mem1.0.1.0_RCLKE.
Rename wire $abc$1286$auto$rtlil.cc:2376:And$822 in main to capRam.mem1.0.0.0_RCLKE.
Rename wire $abc$1286$flatten\SPIPHY.$and$main.v:73$29_Y in main to CE_SB_LUT4_I2_O.
Rename cell $abc$1286$auto$blifparse.cc:515:parse_blif$1296 in main to capRam.mem1.0.3.0_RCLKE_SB_LUT4_O.
Rename cell $abc$1286$auto$blifparse.cc:515:parse_blif$1295 in main to capRam.mem1.0.1.0_RCLKE_SB_LUT4_O.
Rename cell $abc$1286$auto$blifparse.cc:515:parse_blif$1294 in main to capRam.mem1.0.2.0_RCLKE_SB_LUT4_O.
Rename cell $abc$1286$auto$blifparse.cc:515:parse_blif$1293 in main to capRam.mem1.0.0.0_RCLKE_SB_LUT4_O.
Rename cell $abc$1286$auto$blifparse.cc:515:parse_blif$1291 in main to capRam.mem1.0.3.0_RDATA_SB_LUT4_I3.
Rename wire $techmap1332$abc$1286$auto$blifparse.cc:515:parse_blif$1290.A in main to capRam.BRAM_OUT_SB_LUT4_O_I2.
Rename wire $techmap1346$abc$1286$auto$blifparse.cc:515:parse_blif$1295.A in main to capRam.mem1.0.1.0_RCLKE_SB_LUT4_O_I2.
Rename wire $techmap1337$abc$1286$auto$blifparse.cc:515:parse_blif$1294.A in main to capRam.mem1.0.2.0_RCLKE_SB_LUT4_O_I2.
Rename wire $techmap1324$abc$1286$auto$blifparse.cc:515:parse_blif$1293.A in main to capRam.mem1.0.0.0_RCLKE_SB_LUT4_O_I2.
Rename cell $abc$1286$auto$blifparse.cc:515:parse_blif$1287 in main to capRam.mem1.0.2.0_RCLKE_SB_LUT4_O_I2_SB_LUT4_O.
Rename cell $abc$1286$auto$blifparse.cc:515:parse_blif$1292 in main to capRam.BRAM_OUT_SB_LUT4_O_I2_SB_LUT4_O.
Rename cell $abc$1286$auto$blifparse.cc:515:parse_blif$1289 in main to capRam.mem1.0.0.0_RCLKE_SB_LUT4_O_I2_SB_LUT4_O.
Rename cell $abc$1286$auto$blifparse.cc:515:parse_blif$1288 in main to capRam.mem1.0.1.0_RCLKE_SB_LUT4_O_I2_SB_LUT4_O.
Rename cell $auto$ff.cc:262:slice$1134 in main to capRam.mem1.0.1.0_RCLKE_SB_LUT4_O_I2_SB_DFFE_D.
Rename cell $auto$ff.cc:262:slice$1132 in main to capRam.mem1.0.0.0_RCLKE_SB_LUT4_O_I2_SB_DFFE_D.
Rename cell $auto$ff.cc:262:slice$1131 in main to capRam.mem1.0.2.0_RCLKE_SB_LUT4_O_I2_SB_DFFE_D.
Rename wire $auto$memory_bram.cc:1005:replace_memory$995.S in main to capRam.mem1.0.2.0_RCLKE_SB_LUT4_O_I2_SB_DFFE_D_Q.
Rename wire $auto$alumacc.cc:485:replace_alu$810.Y in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D.
Rename cell $auto$ice40_wrapcarry.cc:125:execute$1322 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O.
Rename cell $auto$ice40_wrapcarry.cc:125:execute$1320 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_1.
Rename cell $auto$ice40_wrapcarry.cc:125:execute$1318 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_2.
Rename cell $auto$ice40_wrapcarry.cc:125:execute$1316 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_3.
Rename cell $auto$ice40_wrapcarry.cc:125:execute$1314 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_4.
Rename cell $auto$ice40_wrapcarry.cc:125:execute$1312 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_5.
Rename cell $auto$ice40_wrapcarry.cc:125:execute$1310 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_6.
Rename cell $auto$ice40_wrapcarry.cc:125:execute$1308 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_7.
Rename cell $auto$ice40_wrapcarry.cc:125:execute$1306 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_8.
Rename cell $auto$ice40_wrapcarry.cc:125:execute$1304 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_9.
Rename cell $auto$ice40_wrapcarry.cc:125:execute$1302 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_10.
Rename cell $auto$ice40_wrapcarry.cc:125:execute$1300 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_11.
Rename cell $abc$1286$auto$blifparse.cc:515:parse_blif$1298 in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_12.
Rename wire $auto$alumacc.cc:485:replace_alu$810.C in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_I3.
Rename cell $auto$alumacc.cc:485:replace_alu$810.slice[9].carry in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_I3_SB_CARRY_CO.
Rename cell $auto$alumacc.cc:485:replace_alu$810.slice[8].carry in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_1.
Rename cell $auto$alumacc.cc:485:replace_alu$810.slice[7].carry in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_2.
Rename cell $auto$alumacc.cc:485:replace_alu$810.slice[6].carry in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_3.
Rename cell $auto$alumacc.cc:485:replace_alu$810.slice[5].carry in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_4.
Rename cell $auto$alumacc.cc:485:replace_alu$810.slice[4].carry in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_5.
Rename cell $auto$alumacc.cc:485:replace_alu$810.slice[3].carry in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_6.
Rename cell $auto$alumacc.cc:485:replace_alu$810.slice[2].carry in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_7.
Rename cell $auto$alumacc.cc:485:replace_alu$810.slice[1].carry in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_8.
Rename cell $auto$alumacc.cc:485:replace_alu$810.slice[11].carry in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_9.
Rename cell $auto$alumacc.cc:485:replace_alu$810.slice[10].carry in main to SPIPHY.B2H_ADDR_SB_DFF_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_10.
Renamed 383 objects in module main (13 iterations).

2.46. Executing HIERARCHY pass (managing design hierarchy).

2.46.1. Analyzing design hierarchy..
Top module:  \main

2.46.2. Analyzing design hierarchy..
Top module:  \main
Removed 0 unused modules.

2.47. Printing statistics.

=== main ===

   Number of wires:                 55
   Number of wire bits:            264
   Number of public wires:          55
   Number of public wire bits:     264
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 57
     SB_CARRY                       11
     SB_DFF                         15
     SB_DFFE                         3
     SB_LUT4                        24
     SB_RAM40_4K                     4

2.48. Executing CHECK pass (checking for obvious problems).
Checking module main...
Found and reported 0 problems.

2.49. Executing BLIF backend.

2.50. Executing JSON backend.

Warnings: 63 unique messages, 63 total
End of script. Logfile hash: 667758a9ca, CPU: user 0.41s system 0.02s, MEM: 86.17 MB peak
Yosys 0.11+50 (git sha1 707d98b06, clang 11.0.1-2 -fPIC -Os)
Time spent: 19% 11x read_verilog (0 sec), 18% 7x techmap (0 sec), ...
nextpnr-ice40 --lp1k --package cm36 --json main.json --pcf io.pcf --asc main.asc --freq 48
icepack main.asc main.bin