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TrungNguyen1909/sysreg.c

Last active September 11, 2022 22:14
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A13 instructions and system registers
Raw
sysreg.c
//FIRESTORM: only FIRESTORM (A14/M1)
//LIGHTNING: only Lightning (A13)
#define FIRESTORM
int main() {
__asm__ __volatile__("isb sy\n"
".long 0x00200000\n" //mul53lo.2d v0, v0
".long 0x002003ff\n" //mul53lo.2d v31, v31
".long 0x00200400\n" //mul53hi.2d v0, v0
".long 0x002007ff\n" //mul53hi.2d v31, v31
".long 0x00200800\n" //wkdmc x0, x0
".long 0x00200bff\n" //wkdmc sp, sp
".long 0x00200c00\n" //wkdmd x0, x0
".long 0x00201420\n" //genter #0
".long 0x0020142f\n" //genter #0xf
".long 0x00201400\n" //gexit
#ifdef FIRESTORM
".long 0x00201460\n" //sdsb osh
".long 0x00201461\n" //sdsb nsh
".long 0x00201462\n" //sdsb ish
".long 0x00201463\n" //sdsb sy
#endif
".long 0x00201440\n" //at_as1elx x0
#if AVALANCHE
"mrs x0, S3_1_c15_c14_0\n" //PMCR_BVRNG4_EL1
"mrs x0, S3_1_c15_c15_0\n" //PMCR_BVRNG5_EL1
#endif
"mrs x0, S3_4_c15_c0_5\n" //IMPL_MSR_LOCK_EL1
"mrs x0, S3_4_c15_c1_3\n" //AMX_STATE_T_EL1
"mrs x0, S3_4_c15_c1_4\n" //AMX_CONFIG_EL1
"mrs x0, s3_4_c15_c2_6\n"
"mrs x0, s3_4_c15_c2_7\n"
#ifdef FIRESTORM
"mrs x0, S3_4_c15_c1_5\n" //VMSA_LOCK_EL2
#endif
"mrs x0, S3_6_c15_c1_0\n" //SPRR_CONFIG_EL1
"mrs x0, S3_6_c15_c1_1\n" //SPRR_GTR_EL1
"mrs x0, S3_6_c15_c1_2\n" //GXF_CONFIG_EL1
#ifdef FIRESTORM
"mrs x0, S3_6_c15_c1_4\n" //GXF_CONFIG_EL2
#endif
"mrs x0, S3_6_c15_c1_5\n" //SPRR_EL0BR0_EL1
"mrs x0, S3_6_c15_c1_6\n" //SPRR_EL0BR1_EL1
"mrs x0, S3_6_c15_c1_7\n" //SPRR_EL1BR0_EL1
"mrs x0, S3_6_c15_c3_0\n" //SPRR_EL1BR1_EL1
"mrs x0, S3_6_c15_c3_1\n" //MPRR_EL0BR0_EL1
"mrs x0, S3_6_c15_c3_2\n" //MPRR_EL0BR1_EL1
"mrs x0, S3_6_c15_c3_3\n" //MPRR_EL1BR0_EL1
"mrs x0, S3_6_c15_c3_4\n" //MPRR_EL1BR1_EL1
"mrs x0, S3_6_c15_c3_5\n" //SPRR_SH01_EL1
"mrs x0, S3_6_c15_c3_6\n" //SPRR_SH02_EL1
"mrs x0, S3_6_c15_c3_7\n" //SPRR_SH03_EL1
"mrs x0, S3_6_c15_c8_0\n" //CURRENT_G
"mrs x0, S3_6_c15_c8_1\n" //GXF_ENTRY_EL1
"mrs x0, S3_6_c15_c8_2\n" //GXF_PABENTRY_EL1
#ifdef LIGHTNING
"mrs x0, S3_6_c15_c8_3\n" //ASPSR_GL1
#endif
#ifdef FIRESTORM
"mrs x0, S3_6_c15_c8_3\n" //ASPSR_EL21
"mrs x0, S3_6_c15_c8_4\n" //ADSPSR_EL0
#endif
#ifdef LIGHTNING
"mrs x0, S3_6_c15_c9_0\n" //SP_GL11
"mrs x0, S3_6_c15_c9_1\n" //TPIDR_GL11
"mrs x0, S3_6_c15_c9_2\n" //VBAR_GL11
"mrs x0, S3_6_c15_c9_3\n" //SPSR_GL11
"mrs x0, S3_6_c15_c9_4\n" //ASPSR_GL11
"mrs x0, S3_6_c15_c9_5\n" //ESR_GL11
"mrs x0, S3_6_c15_c9_6\n" //ELR_GL11
"mrs x0, S3_6_c15_c9_7\n" //FAR_GL11
#endif
#ifdef FIRESTORM
"mrs x0, S3_6_c15_c9_0\n" //SP_GL12
"mrs x0, S3_6_c15_c9_1\n" //TPIDR_GL12
"mrs x0, S3_6_c15_c9_2\n" //VBAR_GL12
"mrs x0, S3_6_c15_c9_3\n" //SPSR_GL12
"mrs x0, S3_6_c15_c9_4\n" //ASPSR_GL12
"mrs x0, S3_6_c15_c9_5\n" //ESR_GL12
"mrs x0, S3_6_c15_c9_6\n" //ELR_GL12
"mrs x0, S3_6_c15_c9_7\n" //FAR_GL12
#endif
#ifdef LIGHTNING
"mrs x0, S3_6_c15_c10_0\n" //SP_GL1
"mrs x0, S3_6_c15_c10_1\n" //TPIDR_GL1
"mrs x0, S3_6_c15_c10_2\n" //VBAR_GL1
"mrs x0, S3_6_c15_c10_3\n" //SPSR_GL1
"mrs x0, S3_6_c15_c10_4\n" //ASPSR_GL1
"mrs x0, S3_6_c15_c10_5\n" //ESR_GL1
"mrs x0, S3_6_c15_c10_6\n" //ELR_GL1
"mrs x0, S3_6_c15_c10_7\n" //FAR_GL1
#endif
#ifdef FIRESTORM
"mrs x0, S3_6_c15_c10_0\n" //SP_GL21
"mrs x0, S3_6_c15_c10_1\n" //TPIDR_GL21
"mrs x0, S3_6_c15_c10_2\n" //VBAR_GL21
"mrs x0, S3_6_c15_c10_3\n" //SPSR_GL21
"mrs x0, S3_6_c15_c10_4\n" //ASPSR_GL21
"mrs x0, S3_6_c15_c10_5\n" //ESR_GL21
"mrs x0, S3_6_c15_c10_6\n" //ELR_GL21
"mrs x0, S3_6_c15_c10_7\n" //FAR_GL21
#endif
"mrs x0, s3_5_c15_c4_0\n"
"mrs x0, s3_5_c15_c4_1\n"
#ifdef FIRESTORM
"mrs x0, S3_6_c15_c14_2\n" //SPRR_CONFIG_EL2
"mrs x0, S3_6_c15_c15_0\n" //APCTL_EL12
"mrs x0, S3_6_c15_c15_1\n" //GXF_CONFIG_EL12
"mrs x0, S3_6_c15_c15_2\n" //GXF_ENTRY_EL12
"mrs x0, S3_6_c15_c15_3\n" //GXF_PABENTRY_EL12
"mrs x0, S3_6_c15_c15_4\n" //SPRR_CONFIG_EL12
"mrs x0, S3_6_c15_c15_5\n" //SPRR_AMRANGE_EL12
"mrs x0, S3_6_c15_c15_7\n" //SPRR_PPERM_EL12
"mrs x0, S3_6_c15_c11_0\n" //SP_GL2
"mrs x0, S3_6_c15_c11_1\n" //TPIDR_GL2
"mrs x0, S3_6_c15_c11_2\n" //VBAR_GL2
"mrs x0, S3_6_c15_c11_3\n" //SPSR_GL2
"mrs x0, S3_6_c15_c11_4\n" //ASPSR_GL2
"mrs x0, S3_6_c15_c11_5\n" //ESR_GL2
"mrs x0, S3_6_c15_c11_6\n" //ELR_GL2
"mrs x0, S3_6_c15_c11_7\n" //FAR_GL2
"mrs x0, S3_6_c15_c12_0\n" //GXF_ENTRY_EL2
"mrs x0, S3_6_c15_c12_1\n" //GXF_PABENTRY_EL2
"mrs x0, S3_6_c15_c12_2\n" //APCTL_EL2
"mrs x0, S3_6_c15_c12_3\n" //APSTS_EL2
"mrs x0, S3_6_c15_c12_4\n" //APSTS_EL1
"mrs x0, S3_6_c15_c12_5\n" //KernKeyLo_EL2
"mrs x0, S3_6_c15_c12_6\n" //KernKeyHi_EL2
"mrs x0, S3_6_c15_c12_7\n" //ASPSR_EL12
#endif
"mrs x0, S3_6_c15_c1_3\n" //SPRR_AMRANGE_EL1
#ifdef FIRESTORM
"mrs x0, S3_6_c15_c14_3\n" //SPRR_AMRANGE_EL2
"mrs x0, S3_6_c15_c15_5\n" //SPRR_AMRANGE_EL12
#endif
"mrs x0, S3_6_c15_c4_1\n" //SPRR_SH05_EL1
"mrs x0, S3_6_c15_c4_2\n" //SPRR_SH06_EL1
"mrs x0, S3_6_c15_c4_3\n" //SPRR_SH07_EL1
#ifdef FIRESTORM
"mrs x0, S3_6_c15_c4_4\n" //SPRR_PPERM_SH03_EL1
"mrs x0, S3_6_c15_c4_5\n" //SPRR_PPERM_SH04_EL1
"mrs x0, S3_6_c15_c4_6\n" //SPRR_PPERM_SH05_EL1
"mrs x0, S3_6_c15_c4_7\n" //SPRR_PPERM_SH06_EL1
"mrs x0, S3_6_c15_c5_1\n" //SPRR_PPERM_SH01_EL2
"mrs x0, S3_6_c15_c5_2\n" //SPRR_PPERM_SH02_EL2
"mrs x0, S3_6_c15_c5_3\n" //SPRR_PPERM_SH03_EL2
"mrs x0, S3_6_c15_c5_4\n" //SPRR_PPERM_SH04_EL2
"mrs x0, S3_6_c15_c5_5\n" //SPRR_PPERM_SH05_EL2
"mrs x0, S3_6_c15_c5_6\n" //SPRR_PPERM_SH06_EL2
"mrs x0, S3_6_c15_c5_7\n" //SPRR_PPERM_SH07_EL2
"mrs x0, S3_6_c15_c6_1\n" //SPRR_PPERM_SH01_EL12
"mrs x0, S3_6_c15_c6_2\n" //SPRR_PPERM_SH02_EL12
"mrs x0, S3_6_c15_c6_3\n" //SPRR_PPERM_SH03_EL12
"mrs x0, S3_6_c15_c6_4\n" //SPRR_PPERM_SH04_EL12
"mrs x0, S3_6_c15_c6_5\n" //SPRR_PPERM_SH05_EL12
"mrs x0, S3_6_c15_c6_6\n" //SPRR_PPERM_SH06_EL12
"mrs x0, S3_6_c15_c6_7\n" //SPRR_PPERM_SH07_EL12
"mrs x0, S3_4_c15_c6_0\n"
"mrs x0, S3_4_c15_c6_1\n"
"mrs x0, S3_4_c15_c6_2\n" //CTRR_CTL_EL2
"mrs x0, S3_4_c15_c6_3\n" //CTRR_LOCK_EL2
"mrs x0, S3_4_c15_c7_0\n" //SPRR_HUMPRR_EL1
"mrs x0, S3_4_c15_c7_1\n" //SPRR_HUPERM_SH01_EL2
"mrs x0, S3_4_c15_c7_2\n" //SPRR_HUPERM_SH02_EL2
"mrs x0, S3_4_c15_c7_3\n" //SPRR_HUPERM_SH03_EL2
"mrs x0, S3_4_c15_c7_4\n" //SPRR_HUPERM_SH04_EL2
"mrs x0, S3_4_c15_c7_5\n" //SPRR_HUPERM_SH05_EL2
"mrs x0, S3_4_c15_c7_6\n" //SPRR_HUPERM_SH06_EL2
"mrs x0, S3_4_c15_c7_7\n" //SPRR_HUPERM_SH07_EL2
"mrs x0, S3_4_c15_c8_0\n" //SPRR_VUMPRR_EL1
"mrs x0, S3_4_c15_c8_1\n" //SPRR_VUPERM_SH01_EL1
"mrs x0, S3_4_c15_c8_2\n" //SPRR_VUPERM_SH02_EL1
"mrs x0, S3_4_c15_c8_3\n" //SPRR_VUPERM_SH03_EL1
"mrs x0, S3_4_c15_c8_4\n" //SPRR_VUPERM_SH04_EL1
"mrs x0, S3_4_c15_c8_5\n" //SPRR_VUPERM_SH05_EL1
"mrs x0, S3_4_c15_c8_6\n" //SPRR_VUPERM_SH06_EL1
"mrs x0, S3_4_c15_c8_7\n" //SPRR_VUPERM_SH07_EL1
#endif
".long 0x00201040\n" //amxstx x0
".long 0x00201060\n" //amxsty x0
".long 0x002010a0\n" //amxstz x0
".long 0x00201000\n" //amxldx x0
".long 0x00201020\n" //amxldy x0
".long 0x00201080\n" //amxldz x0
: ::"memory");
}
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