flip-flop-jk.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity ffjk is
	port(
		J, K: in std_logic; 
		clk : in std_logic;
		clear, preset : in std_logic;	
		Q, Qbar: out std_logic
	);
end ffjk;

ARCHITECTURE comportamento OF ffjk IS
	signal qsignal : std_logic;
BEGIN
	process(clk, preset, clear)
	begin
		if(clear = '0') then
			qsignal <= '0';
		elsif(preset = '0') then
			qsignal <= '1';
		elsif(clk'event and clk='0') then
			if(J = '0' and K='1') then
				qsignal <= '1';
			elsif(J = '1' and K='0') then
				qsignal <= '0';
			elsif(J = '0' and K='0') then
				qsignal <= not qsignal;
			end if;
		end if;
	end process;
	
	Q <= qsignal;
	QBar <= not qsignal;
END comportamento;