Emerson Costa Trunkol

## contador.vhdl
library ieee;
use ieee.std_logic_1164.all;

entity contador is
port(
	clockCont : in std_logic;
	Qc : out std_logic_vector(3 downto 0)
);
end contador;

## flip-flop-jk.vhdl
library ieee;
use ieee.std_logic_1164.all;

entity ffjk is
	port(
		J, K: in std_logic;
		clk : in std_logic;
		clear, preset : in std_logic;
		Q, Qbar: out std_logic
	);

## aula03-demux.vhdl

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY demultiplexador IS
	PORT (
		x : IN std_logic;
		s : IN std_logic_vector(3 DOWNTO 0);

## aula03.vhdl
library ieee;
use ieee.std_logic_1164.all;

entity multiplex is
	port(A, B, S3, S2, S1, S0, enable: in std_logic; Y: out std_logic);
end multiplex;

ARCHITECTURE comportamento OF multiplex IS
	signal f : std_logic_vector(15 downto 0);
	signal s : std_logic_vector(15 downto 0);

## laudo.txt
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## exame.txt
WvIMqyk+xfrFz+lUUA6JDVbmGdDjh7Ia+QCTh7V4g5J6Qlo0a6tYx2vpQjz1zux4/ymMqvGzJ3lvjKgH1pfO1xTTT/aPNTTDzcOiqxSu8ZMf9jxUK/jpsylz7mYHzV0MwqS8ZaFiW6/VaEi36iiP0TamXCPEASE7v/+fKIUhSmyzKe+Z128rvCvaVp24p1S0GFoBZOWyyXi+nAoapCaeubbjfAsvOHon0WswJyKQGHi1eBTlNBJIQzDr9GWqWCl+39AHNv4/XvczS5uSzvc8AnetdSpe7aIeKuPpvHlxSpOXoG9gRCLlG9iH62sVfxv7rIybkrZUB3lCxkI0SwuOnpNPmlZyNbyzgP5e2E6UmyHBkkkKQ/Fv0y6Gb16oOdX7WPn7ydu+whSBQ7i7AiCkzo63Ncisi5Jlrt0Pgn9jqhZJ/nn8aPOiFmVHjDrX46RJdGivQ8zdjaU+LfrY51k2F1gKSDmBo2ev6G5QPEJ92ggwWZ5IOpk5tGoGSdz/7U6Q+SvW/xXwIT/GDhaGrBvbRlJOUzBmfjK5IsRk7nvF7bm+WdP5KQya92JdWfYbpylkpaw5K8OlBOmF0L4egj/JR1SLlXnk90yXIAhyTTfThW8F9dEEsh1TCDR006GAAW4bfvIPoa103jSMhiXayLgVbcrbGi5Ra3wDjL9tebwsjBoyjmmRwhMhjaJJFGPqkMcZkWDbklaOn1svGcsH5aCz6sjvDGZXnJaagLEoy9nv3tn3SYRumpaTUW6H4V4/T0sSMJKte/o7lWQTKTggbjCJtlBW7i69t2QCTfhMvCh+Az01nkhu+/P5aYRsQOkWTFY59P6L1bvHvy9HGhEr6OYELlIpTin4EL1mrAlGxKfhPVq02KOBj6KBeqlPYhJ9RA67sKq2JObdFpWYOgURhZpWgXQt0aLAe98sBzKhcr31Bh/qi6TN3f/XtfmRRYgo9LSyCjW2Yq9stTxmreDdaLh/WDR7GiJ9UyR0W8lvKgmlzsjwq92za8hkecnNpDkwJAfG
	library ieee;
	use ieee.std_logic_1164.all;

	entity contador is
	port(
	clockCont : in std_logic;
	Qc : out std_logic_vector(3 downto 0)
	);
	end contador;
	library ieee;
	use ieee.std_logic_1164.all;

	entity ffjk is
	port(
	J, K: in std_logic;
	clk : in std_logic;
	clear, preset : in std_logic;
	Q, Qbar: out std_logic
	);

	LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_ARITH.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

	ENTITY demultiplexador IS
	PORT (
	x : IN std_logic;
	s : IN std_logic_vector(3 DOWNTO 0);
	library ieee;
	use ieee.std_logic_1164.all;

	entity multiplex is
	port(A, B, S3, S2, S1, S0, enable: in std_logic; Y: out std_logic);
	end multiplex;

	ARCHITECTURE comportamento OF multiplex IS
	signal f : std_logic_vector(15 downto 0);
	signal s : std_logic_vector(15 downto 0);