decdata.v

module ic74x138(G1, G2A_L,G2B_L,C,B,A,Y_L);
input G1, G2A_L,G2B_L,C,B,A;
output [0:7] Y_L;
wire E;
assign E = G1 & ~G2A_L & ~G2B_L;
assign Y_L[0] = ~(~C & ~B & ~A & E),
Y_L[1] = ~(~C & ~B & A & E),
Y_L[2] = ~(~C & B & ~A & E),
Y_L[3] = ~(~C & B & A & E),
Y_L[4] = ~(C & ~B & ~A & E),
Y_L[5] = ~(C & ~B & A & E),
Y_L[6] = ~(C & B & ~A & E),
Y_L[7] = ~(C & B & A & E);
endmodule