kvmppc_vcpu_run.S

/* Registers:
 *  r3: kvm_run pointer
 *  r4: vcpu pointer
 */
_GLOBAL(__kvmppc_vcpu_run)
	stwu	r1, -HOST_STACK_SIZE(r1)
	PPC_STL	r1, VCPU_HOST_STACK(r4)	/* Save stack pointer to vcpu. */

	/* Save host state to stack. */
	PPC_STL	r3, HOST_RUN(r1)
	mflr	r3
	mfcr	r5
	PPC_STL	r3, HOST_STACK_LR(r1)

	stw	r5, HOST_CR(r1)

	/* Save host non-volatile register state to stack. */
	PPC_STL	r14, HOST_NV_GPR(R14)(r1)
	PPC_STL	r15, HOST_NV_GPR(R15)(r1)
	PPC_STL	r16, HOST_NV_GPR(R16)(r1)
	PPC_STL	r17, HOST_NV_GPR(R17)(r1)
	PPC_STL	r18, HOST_NV_GPR(R18)(r1)
	PPC_STL	r19, HOST_NV_GPR(R19)(r1)
	PPC_STL	r20, HOST_NV_GPR(R20)(r1)
	PPC_STL	r21, HOST_NV_GPR(R21)(r1)
	PPC_STL	r22, HOST_NV_GPR(R22)(r1)
	PPC_STL	r23, HOST_NV_GPR(R23)(r1)
	PPC_STL	r24, HOST_NV_GPR(R24)(r1)
	PPC_STL	r25, HOST_NV_GPR(R25)(r1)
	PPC_STL	r26, HOST_NV_GPR(R26)(r1)
	PPC_STL	r27, HOST_NV_GPR(R27)(r1)
	PPC_STL	r28, HOST_NV_GPR(R28)(r1)
	PPC_STL	r29, HOST_NV_GPR(R29)(r1)
	PPC_STL	r30, HOST_NV_GPR(R30)(r1)
	PPC_STL	r31, HOST_NV_GPR(R31)(r1)

	/* Load guest non-volatiles. */
	PPC_LL	r14, VCPU_GPR(R14)(r4)
	PPC_LL	r15, VCPU_GPR(R15)(r4)
	PPC_LL	r16, VCPU_GPR(R16)(r4)
	PPC_LL	r17, VCPU_GPR(R17)(r4)
	PPC_LL	r18, VCPU_GPR(R18)(r4)
	PPC_LL	r19, VCPU_GPR(R19)(r4)
	PPC_LL	r20, VCPU_GPR(R20)(r4)
	PPC_LL	r21, VCPU_GPR(R21)(r4)
	PPC_LL	r22, VCPU_GPR(R22)(r4)
	PPC_LL	r23, VCPU_GPR(R23)(r4)
	PPC_LL	r24, VCPU_GPR(R24)(r4)
	PPC_LL	r25, VCPU_GPR(R25)(r4)
	PPC_LL	r26, VCPU_GPR(R26)(r4)
	PPC_LL	r27, VCPU_GPR(R27)(r4)
	PPC_LL	r28, VCPU_GPR(R28)(r4)
	PPC_LL	r29, VCPU_GPR(R29)(r4)
	PPC_LL	r30, VCPU_GPR(R30)(r4)
	PPC_LL	r31, VCPU_GPR(R31)(r4)


lightweight_exit:
	PPC_STL	r2, HOST_R2(r1)

	mfspr	r3, SPRN_PID
	stw	r3, VCPU_HOST_PID(r4)
	lwz	r3, VCPU_GUEST_PID(r4)
	mtspr	SPRN_PID, r3

	PPC_LL	r11, VCPU_SHARED(r4)
	/* Disable MAS register updates via exception */
	mfspr	r3, SPRN_EPCR
	oris	r3, r3, SPRN_EPCR_DMIUH@h
	mtspr	SPRN_EPCR, r3
	isync
	/* Save host mas4 and mas6 and load guest MAS registers */
	mfspr	r3, SPRN_MAS4
	stw	r3, VCPU_HOST_MAS4(r4)
	mfspr	r3, SPRN_MAS6
	stw	r3, VCPU_HOST_MAS6(r4)
	lwz	r3, VCPU_SHARED_MAS0(r11)
	lwz	r5, VCPU_SHARED_MAS1(r11)
	PPC_LD(r6, VCPU_SHARED_MAS2, r11)
	lwz	r7, VCPU_SHARED_MAS7_3+4(r11)
	lwz	r8, VCPU_SHARED_MAS4(r11)
	mtspr	SPRN_MAS0, r3
	mtspr	SPRN_MAS1, r5
	mtspr	SPRN_MAS2, r6
	mtspr	SPRN_MAS3, r7
	mtspr	SPRN_MAS4, r8
	lwz	r3, VCPU_SHARED_MAS6(r11)
	lwz	r5, VCPU_SHARED_MAS7_3+0(r11)
	mtspr	SPRN_MAS6, r3
	mtspr	SPRN_MAS7, r5

	/*
	 * Host interrupt handlers may have clobbered these guest-readable
	 * SPRGs, so we need to reload them here with the guest's values.
	 */
	lwz	r3, VCPU_VRSAVE(r4)
	PPC_LD(r5, VCPU_SHARED_SPRG4, r11)
	mtspr	SPRN_VRSAVE, r3
	PPC_LD(r6, VCPU_SHARED_SPRG5, r11)
	mtspr	SPRN_SPRG4W, r5
	PPC_LD(r7, VCPU_SHARED_SPRG6, r11)
	mtspr	SPRN_SPRG5W, r6
	PPC_LD(r8, VCPU_SHARED_SPRG7, r11)
	mtspr	SPRN_SPRG6W, r7
	PPC_LD(r5, VCPU_SPRG9, r4)
	mtspr	SPRN_SPRG7W, r8
	mtspr	SPRN_SPRG9, r5

	/* Load some guest volatiles. */
	PPC_LL	r3, VCPU_LR(r4)
	PPC_LL	r5, VCPU_XER(r4)
	PPC_LL	r6, VCPU_CTR(r4)
	lwz	r7, VCPU_CR(r4)
	PPC_LL	r8, VCPU_PC(r4)
	PPC_LD(r9, VCPU_SHARED_MSR, r11)
	PPC_LL	r0, VCPU_GPR(R0)(r4)
	PPC_LL	r1, VCPU_GPR(R1)(r4)
	PPC_LL	r2, VCPU_GPR(R2)(r4)
	PPC_LL	r10, VCPU_GPR(R10)(r4)
	PPC_LL	r11, VCPU_GPR(R11)(r4)
	PPC_LL	r12, VCPU_GPR(R12)(r4)
	PPC_LL	r13, VCPU_GPR(R13)(r4)
	mtlr	r3
	mtxer	r5
	mtctr	r6
	mtsrr0	r8
	mtsrr1	r9

#ifdef CONFIG_KVM_EXIT_TIMING
	/* save enter time */
1:
	mfspr	r6, SPRN_TBRU
	mfspr	r9, SPRN_TBRL
	mfspr	r8, SPRN_TBRU
	cmpw	r8, r6
	stw	r9, VCPU_TIMING_LAST_ENTER_TBL(r4)
	bne	1b
	stw	r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
#endif

	/*
	 * Don't execute any instruction which can change CR after
	 * below instruction.
	 */
	mtcr	r7

	/* Finish loading guest volatiles and jump to guest. */
	PPC_LL	r5, VCPU_GPR(R5)(r4)
	PPC_LL	r6, VCPU_GPR(R6)(r4)
	PPC_LL	r7, VCPU_GPR(R7)(r4)
	PPC_LL	r8, VCPU_GPR(R8)(r4)
	PPC_LL	r9, VCPU_GPR(R9)(r4)

	PPC_LL	r3, VCPU_GPR(R3)(r4)
	PPC_LL	r4, VCPU_GPR(R4)(r4)
	rfi