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Wuerfel21/gist:0e89677f0c2fafb0644cca2fdf55f783 Secret

Created June 30, 2022 10:11
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gistfile1.txt
$ loadp2 -p COM8 -t psram4_delay_test.binary
( Entering terminal mode. Press Ctrl-] to exit. )
PSRAM 4 bit memory read delay test over frequency, ESC exits
Enter the base pin number for your PSRAM (0,4,8...52) [40]: 0
Enter the chip enable pin number for your PSRAM [57]: 10
Enter the clock pin number for your PSRAM [56]: 8
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 11
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 12
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 13
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 14
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 15
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 56
Enter a starting frequency to test in MHz (100-350) : [100] 325
Enter the ending frequency to test in MHz (325-350) : [325] 345
Enter 1 to use the automatic delay value only, or 0 to test over the delay range : [0] 0
Enter 1 to display the first error encountered, or 0 to not display error details : [0] 0
Testing P2 from 325000000 - 345000000 Hz
Successful data reads from 100 block transfers of 8192 random bytes
Frequency Delay 3 4 5 6 7 8 9 10 11 12 13 14
325000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
326000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
327000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
328000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
329000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
330000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
331000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
332000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
333000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
334000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
335000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
336000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
337000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
338000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
339000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
340000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
341000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
342000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
343000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
344000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
345000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
Enter the base pin number for your PSRAM (0,4,8...52) [0]: 0
Enter the chip enable pin number for your PSRAM [10]: 11
Enter the clock pin number for your PSRAM [8]: 8
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 10
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 12
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 13
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 14
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 15
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 56
Enter a starting frequency to test in MHz (100-350) : [325] 325
Enter the ending frequency to test in MHz (325-350) : [345] 345
Enter 1 to use the automatic delay value only, or 0 to test over the delay range : [0] 0
Enter 1 to display the first error encountered, or 0 to not display error details : [0] 0
Testing P2 from 325000000 - 345000000 Hz
Successful data reads from 100 block transfers of 8192 random bytes
Frequency Delay 3 4 5 6 7 8 9 10 11 12 13 14
325000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 8% 100% 0%
326000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 1% 100% 0%
327000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
328000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
329000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
330000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
331000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
332000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
333000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
334000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
335000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
336000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
337000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
338000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
339000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 0%
340000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 0%
341000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 95% 0%
342000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 91% 0%
343000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 81% 0%
344000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 53% 0%
345000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 25% 0%
Enter the base pin number for your PSRAM (0,4,8...52) [0]: 0
Enter the chip enable pin number for your PSRAM [11]: 12
Enter the clock pin number for your PSRAM [8]: 8
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 10
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 11
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 13
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 14
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 15
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 56
Enter a starting frequency to test in MHz (100-350) : [325] 325
Enter the ending frequency to test in MHz (325-350) : [345] 345
Enter 1 to use the automatic delay value only, or 0 to test over the delay range : [0] 0
Enter 1 to display the first error encountered, or 0 to not display error details : [0] 0
Testing P2 from 325000000 - 345000000 Hz
Successful data reads from 100 block transfers of 8192 random bytes
Frequency Delay 3 4 5 6 7 8 9 10 11 12 13 14
325000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
326000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
327000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
328000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
329000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
330000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
331000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
332000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
333000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
334000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
335000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
336000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
337000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
338000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
339000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
340000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
341000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
342000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
343000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
344000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
345000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
Enter the base pin number for your PSRAM (0,4,8...52) [0]: 0
Enter the chip enable pin number for your PSRAM [12]: 13
Enter the clock pin number for your PSRAM [8]: 8
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 10
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 11
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 12
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 14
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 15
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 56
Enter a starting frequency to test in MHz (100-350) : [325] 325
Enter the ending frequency to test in MHz (325-350) : [345] 345
Enter 1 to use the automatic delay value only, or 0 to test over the delay range : [0] 0
Enter 1 to display the first error encountered, or 0 to not display error details : [0] 0
Testing P2 from 325000000 - 345000000 Hz
Successful data reads from 100 block transfers of 8192 random bytes
Frequency Delay 3 4 5 6 7 8 9 10 11 12 13 14
325000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
326000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
327000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
328000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
329000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
330000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
331000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
332000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
333000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
334000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
335000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
336000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 96% 0%
337000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 93% 0%
338000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 93% 0%
339000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 87% 0%
340000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 72% 0%
341000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 53% 0%
342000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 31% 0%
343000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 6% 0%
344000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
345000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
Enter the base pin number for your PSRAM (0,4,8...52) [0]: 0
Enter the chip enable pin number for your PSRAM [13]: 14
Enter the clock pin number for your PSRAM [8]: 8
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 10
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 11
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 12
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 13
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 15
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 56
Enter a starting frequency to test in MHz (100-350) : [325] 325
Enter the ending frequency to test in MHz (325-350) : [345] 345
Enter 1 to use the automatic delay value only, or 0 to test over the delay range : [0] 0
Enter 1 to display the first error encountered, or 0 to not display error details : [0] 0
Testing P2 from 325000000 - 345000000 Hz
Successful data reads from 100 block transfers of 8192 random bytes
Frequency Delay 3 4 5 6 7 8 9 10 11 12 13 14
325000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
326000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 0%
327000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
328000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
329000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
330000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 98% 0%
331000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
332000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 0%
333000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 0%
334000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 98% 0%
335000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 0%
336000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
337000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 96% 0%
338000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 97% 0%
339000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 90% 0%
340000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 89% 0%
341000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 84% 0%
342000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 78% 0%
343000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 76% 0%
344000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 68% 0%
345000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 63% 0%
Enter the base pin number for your PSRAM (0,4,8...52) [0]: 0
Enter the chip enable pin number for your PSRAM [14]: 15
Enter the clock pin number for your PSRAM [8]: 8
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 10
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 11
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 12
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 13
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 14
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 56
Enter a starting frequency to test in MHz (100-350) : [325] 325
Enter the ending frequency to test in MHz (325-350) : [345] 345
Enter 1 to use the automatic delay value only, or 0 to test over the delay range : [0] 0
Enter 1 to display the first error encountered, or 0 to not display error details : [0] 0
Testing P2 from 325000000 - 345000000 Hz
Successful data reads from 100 block transfers of 8192 random bytes
Frequency Delay 3 4 5 6 7 8 9 10 11 12 13 14
325000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 31% 100% 0%
326000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 3% 100% 0%
327000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
328000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
329000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
330000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
331000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
332000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
333000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
334000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
335000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
336000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 98% 0%
337000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
338000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 97% 0%
339000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 96% 0%
340000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 96% 0%
341000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 0%
342000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 93% 0%
343000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 85% 0%
344000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 79% 0%
345000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 54% 0%
Enter the base pin number for your PSRAM (0,4,8...52) [0]: 4
Enter the chip enable pin number for your PSRAM [15]: 10
Enter the clock pin number for your PSRAM [8]: 9
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 11
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 12
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 13
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 14
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 15
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 56
Enter a starting frequency to test in MHz (100-350) : [325] 325
Enter the ending frequency to test in MHz (325-350) : [345] 345
Enter 1 to use the automatic delay value only, or 0 to test over the delay range : [0] 0
Enter 1 to display the first error encountered, or 0 to not display error details : [0] 0
Testing P2 from 325000000 - 345000000 Hz
Successful data reads from 100 block transfers of 8192 random bytes
Frequency Delay 3 4 5 6 7 8 9 10 11 12 13 14
325000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 97% 100% 0%
326000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 98% 100% 0%
327000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 97% 100% 0%
328000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
329000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 94% 100% 0%
330000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 93% 100% 0%
331000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 93% 100% 0%
332000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 94% 100% 0%
333000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 90% 100% 0%
334000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 84% 100% 0%
335000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 77% 100% 0%
336000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 67% 99% 0%
337000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 43% 98% 0%
338000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 22% 99% 0%
339000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 3% 98% 0%
340000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 2% 98% 0%
341000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 0%
342000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 97% 0%
343000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 98% 0%
344000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 0%
345000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 94% 0%
Enter the base pin number for your PSRAM (0,4,8...52) [4]: 4
Enter the chip enable pin number for your PSRAM [10]: 11
Enter the clock pin number for your PSRAM [9]: 9
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 10
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 12
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 13
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 14
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 15
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 56
Enter a starting frequency to test in MHz (100-350) : [325] 325
Enter the ending frequency to test in MHz (325-350) : [345] 345
Enter 1 to use the automatic delay value only, or 0 to test over the delay range : [0] 0
Enter 1 to display the first error encountered, or 0 to not display error details : [0] 0
Testing P2 from 325000000 - 345000000 Hz
Successful data reads from 100 block transfers of 8192 random bytes
Frequency Delay 3 4 5 6 7 8 9 10 11 12 13 14
325000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
326000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
327000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
328000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
329000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 0%
330000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 95% 0%
331000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 86% 0%
332000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 54% 0%
333000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 13% 0%
334000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 2% 0%
335000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
336000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
337000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
338000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
339000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
340000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
341000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
342000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
343000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
344000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
345000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
Enter the base pin number for your PSRAM (0,4,8...52) [4]: 4
Enter the chip enable pin number for your PSRAM [11]: 12
Enter the clock pin number for your PSRAM [9]: 9
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 10
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 11
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 13
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 14
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 15
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 56
Enter a starting frequency to test in MHz (100-350) : [325] 325
Enter the ending frequency to test in MHz (325-350) : [345] 345
Enter 1 to use the automatic delay value only, or 0 to test over the delay range : [0] 0
Enter 1 to display the first error encountered, or 0 to not display error details : [0] 0
Testing P2 from 325000000 - 345000000 Hz
Successful data reads from 100 block transfers of 8192 random bytes
Frequency Delay 3 4 5 6 7 8 9 10 11 12 13 14
325000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
326000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
327000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
328000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
329000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 100% 0%
330000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
331000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 96% 100% 0%
332000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 96% 100% 0%
333000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 78% 100% 0%
334000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 73% 100% 0%
335000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 65% 100% 0%
336000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 32% 100% 0%
337000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 20% 100% 0%
338000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 4% 100% 0%
339000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
340000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
341000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
342000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
343000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
344000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
345000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
Enter the base pin number for your PSRAM (0,4,8...52) [4]: 4
Enter the chip enable pin number for your PSRAM [12]: 13
Enter the clock pin number for your PSRAM [9]: 9
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 10
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 11
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 12
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 14
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 15
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 56
Enter a starting frequency to test in MHz (100-350) : [325] 325
Enter the ending frequency to test in MHz (325-350) : [345] 345
Enter 1 to use the automatic delay value only, or 0 to test over the delay range : [0] 0
Enter 1 to display the first error encountered, or 0 to not display error details : [0] 0
Testing P2 from 325000000 - 345000000 Hz
Successful data reads from 100 block transfers of 8192 random bytes
Frequency Delay 3 4 5 6 7 8 9 10 11 12 13 14
325000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
326000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
327000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
328000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
329000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
330000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
331000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
332000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
333000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
334000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 95% 0%
335000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 94% 0%
336000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 60% 0%
337000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 14% 0%
338000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 1% 0%
339000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
340000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
341000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
342000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
343000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
344000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
345000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
Enter the base pin number for your PSRAM (0,4,8...52) [4]: 4
Enter the chip enable pin number for your PSRAM [13]: 14
Enter the clock pin number for your PSRAM [9]: 9
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 10
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 11
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 12
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 13
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 15
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 56
Enter a starting frequency to test in MHz (100-350) : [325] 325
Enter the ending frequency to test in MHz (325-350) : [345] 345
Enter 1 to use the automatic delay value only, or 0 to test over the delay range : [0] 0
Enter 1 to display the first error encountered, or 0 to not display error details : [0] 0
Testing P2 from 325000000 - 345000000 Hz
Successful data reads from 100 block transfers of 8192 random bytes
Frequency Delay 3 4 5 6 7 8 9 10 11 12 13 14
325000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
326000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
327000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 100% 0%
328000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 100% 0%
329000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 94% 100% 0%
330000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 93% 100% 0%
331000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 84% 100% 0%
332000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 66% 100% 0%
333000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 55% 100% 0%
334000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 30% 100% 0%
335000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 24% 100% 0%
336000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 16% 100% 0%
337000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 2% 100% 0%
338000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 2% 100% 0%
339000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
340000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
341000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
342000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
343000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
344000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
345000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
Enter the base pin number for your PSRAM (0,4,8...52) [4]: 4
Enter the chip enable pin number for your PSRAM [14]: 15
Enter the clock pin number for your PSRAM [9]: 9
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 10
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 11
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 12
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 13
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 14
Enter an additional CE/CLK P2 pin to drive high (0-55), or a higher value to exit [56]: 56
Enter a starting frequency to test in MHz (100-350) : [325] 325
Enter the ending frequency to test in MHz (325-350) : [345] 345
Enter 1 to use the automatic delay value only, or 0 to test over the delay range : [0] 0
Enter 1 to display the first error encountered, or 0 to not display error details : [0] 0
Testing P2 from 325000000 - 345000000 Hz
Successful data reads from 100 block transfers of 8192 random bytes
Frequency Delay 3 4 5 6 7 8 9 10 11 12 13 14
325000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
326000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
327000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
328000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
329000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
330000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
331000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 100% 0%
332000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 99% 0%
333000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 95% 0%
334000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 79% 0%
335000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 38% 0%
336000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 2% 0%
337000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
338000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
339000000 (11) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
340000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
341000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
342000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
343000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
344000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
345000000 (12) 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%
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