Skip to content

Instantly share code, notes, and snippets.

@XdoctorwhoZ

XdoctorwhoZ/jtag_reminder.md

Last active August 27, 2022 16:44
Show Gist options
  • Save XdoctorwhoZ/16ce870f64d643a9e6b06f3abc0e1cbf to your computer and use it in GitHub Desktop.
Save XdoctorwhoZ/16ce870f64d643a9e6b06f3abc0e1cbf to your computer and use it in GitHub Desktop.
Download ZIP
Reminder for JTAG practical information
Raw
jtag_reminder.md

Test Access Port (TAP) Controller

A JTAG compliant IC has a Test Access Port (TAP) controller that comprises of the four signals and the logic that connects and controls them.

The JTAG chip has four mandatory wires or pins and an optional fifth one for a reset signal. The required pins and roles are:

  • TDI: serial input pin for the instructions, test, and programming data
  • TDO: serial out pin for the instructions, test, and programming data
  • TMS: input for the signal that manages the TAP controller state machine.
  • TCK: clock signal input pin for the boundary scan circuitry
  • TRST: reset signal (optional)

The TAP controller comprises of a 16-state finite state machine. These states are controlled by the test clock (TCK) and test modes select (TMS) signals. The JTAG interface provides a means to connect the external tools to the inbuilt TAP controller.

TAP Chain

SEE tap_chain.png

Sources

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment