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_reg_agc.h
#ifndef __REG_AGC_H_
#define __REG_AGC_H_
#define REG_AGC_SIZE 172
#define REG_AGC_BASE_ADDR 0x01000000
#endif // __REG_AGC_H_
Raw
_reg_dma.h
#ifndef __REG_DMA_H_
#define __REG_DMA_H_
#define REG_DMA_SIZE 196
#define REG_DMA_BASE_ADDR 0x10A00000
#endif // __REG_DMA_H_
Raw
_reg_intc.h
#ifndef __REG_INTC_H_
#define __REG_INTC_H_
#define REG_INTC_SIZE 68
#define REG_INTC_BASE_ADDR 0x10910000
#endif // __REG_INTC_H_
Raw
_reg_la.h
#ifndef __REG_LA_H_
#define __REG_LA_H_
#define REG_LA_SIZE 64
#define REG_LA_OFFSET 0x00800000
#define REG_LA_BASE_ADDR 0x10E00000
#endif // __REG_LA_H_
Raw
_reg_mac_core.h
#ifndef __REG_MAC_CORE_H_
#define __REG_MAC_CORE_H_
#define REG_MAC_CORE_SIZE 1376
#define REG_MAC_CORE_BASE_ADDR 0xC0000000
#endif // __REG_MAC_CORE_H_
Raw
_reg_mac_pl.h
#ifndef __REG_MAC_PL_H_
#define __REG_MAC_PL_H_
#define REG_MAC_PL_SIZE 1404
#define REG_MAC_PL_BASE_ADDR 0xC0008000
#endif // __REG_MAC_PL_H_
Raw
_reg_mdm_cfg.h
#ifndef __REG_MDM_CFG_H_
#define __REG_MDM_CFG_H_
#define REG_MDM_CFG_SIZE 152
#define REG_MDM_CFG_BASE_ADDR 0x01000000
#endif // __REG_MDM_CFG_H_
Raw
_reg_mdm_stat.h
#ifndef __REG_MDM_STAT_H_
#define __REG_MDM_STAT_H_
#define REG_MDM_STAT_SIZE 108
#define REG_MDM_STAT_BASE_ADDR 0x01000000
#endif // __REG_MDM_STAT_H_
Raw
_reg_rc.h
#ifndef __REG_RC_H_
#define __REG_RC_H_
#define REG_RC_SIZE 428
#define REG_RC_BASE_ADDR 0x01050000
#endif // __REG_RC_H_
Raw
phy.h
/**
****************************************************************************************
*
* @file phy.h
*
* @brief Header file for nX Radio physical layer driver.
*
* Copyright (C) RivieraWaves 2011-2016
*
****************************************************************************************
*/
#ifndef _PHY_H_
#define _PHY_H_
/*
****************************************************************************************
* @defgroup PHY PHY
* @ingroup PLATFORM_DRIVERS
* @brief Declaration of the PHY Drivers
* @{
****************************************************************************************
*/
/*
* INCLUDE FILES
****************************************************************************************
*/
// default inclusion directives
#include "co_int.h"
#include "rwnx_config.h"
//for __INLINE
#include "compiler.h"
/*
* DEFINES
****************************************************************************************
*/
/// Invalid value for some octet parameters reserved for the future
#define PHY_UNUSED 0xFF
/// Maximum number of words in the configuration buffer
#define PHY_CFG_BUF_SIZE 16
enum
{
/// 2.4GHz Band
PHY_BAND_2G4,
/// 5GHz band
PHY_BAND_5G,
/// Number of bands
PHY_BAND_MAX,
};
enum
{
PHY_CHNL_BW_20,
PHY_CHNL_BW_40,
PHY_CHNL_BW_80,
PHY_CHNL_BW_160,
PHY_CHNL_BW_80P80,
PHY_CHNL_BW_OTHER,
};
enum
{
/// Primary radar detection chain (i.e for the operating channel)
PHY_PRIM,
/// Secondary radar detection chain
PHY_SEC,
};
/// Structure containing the information about the PHY channel that was used for this RX
struct phy_channel_info
{
/// PHY channel information 1
uint32_t info1;
/// PHY channel information 2
uint32_t info2;
};
struct phy_radar_pulse
{
/// In our PHY a radar pulse is only one 32-bit word
uint32_t pulse;
};
/// Structure containing the parameters of the PHY configuration
struct phy_cfg_tag
{
/// Buffer containing the parameters specific for the PHY used
uint32_t parameters[PHY_CFG_BUF_SIZE];
};
/*
* FUNCTION DECLARATIONS
****************************************************************************************
*/
/**
****************************************************************************************
* @brief Modem and Radio initialization function.
* This function is called at platform reset and initializes modem, then radio.
* @param[in] cfg Pointer to the PHY parameters (used radio paths, other cfg)
****************************************************************************************
*/
void phy_init(const struct phy_cfg_tag *config);
/**
****************************************************************************************
* @brief Resets some parts of the PHY.
* This function is called upon a system reset during the recovery procedure.
****************************************************************************************
*/
void phy_reset(void);
/**
****************************************************************************************
* @brief PHY version reading function.
* This function returns the PHY version on two 32-bit words. The format of these two
* words is PHY dependent.
*
* @param[out] version_1 Pointer to the 1st version word
* @param[out] version_2 Pointer to the 2nd version word
****************************************************************************************
*/
void phy_get_version(uint32_t *version_1, uint32_t *version_2);
/**
****************************************************************************************
* @brief Set channel function.
* This function is called when the MAC stack needs to change the channel on which the
* radio is locked.
* The function is blocking until the PLL has locked on the new channel frequency.
*
* @param[in] band Band for which the channel index is specified
* @param[in] type Channel type for 20/40/80/160/80+80 or other
* @param[in] prim20_freq Primary 20MHz channel frequency (in MHz)
* @param[in] center1_freq Center frequency of whole channel (when contiguous),
* =prim20_freq for a 20MHz channel. Center or primary 80MHz channel
* if 80+80 type
* @param[in] center2_freq Center frequency of secondary 80MHz channel if 80+80
* @param[in] index Index of the RF for which the channel has to be set (@PHY_PRIM:
* operating (primary RF)), 1: secondary RF (@PHY_SEC: used for
* additional radar detection). This parameter is reserved if no
* secondary RF is available in the system
****************************************************************************************
*/
void phy_set_channel(uint8_t band, uint8_t type, uint16_t prim20_freq,
uint16_t center1_freq, uint16_t center2_freq, uint8_t index);
/**
****************************************************************************************
* @brief Get channel function.
* This function is called when the MAC stack needs to get the information on the channel
* on which the radio is currently locked.
*
* @param[out] info Pointer on the phy_channel_info structure used to return the
* information
* @param[in] index Index of the RF for which the channel has to be retrieved
* (@PHY_PRIM or @PHY_SEC)
*
****************************************************************************************
*/
void phy_get_channel(struct phy_channel_info *info, uint8_t index);
/**
****************************************************************************************
* @brief PHY stop function.
* This function is called when the MAC stack needs to stop the PHY.
* It puts back the MAC HW to the IDLE state
****************************************************************************************
*/
void phy_stop(void);
/**
****************************************************************************************
* @brief Compute the channel number from its center frequency and its band
* @param[in] band RF band (must be @ref PHY_BAND_2G4 or @ref PHY_BAND_5G)
* @param[in] freq Center frequency of the channel
****************************************************************************************
*/
__INLINE int phy_freq_to_channel(uint8_t band, uint16_t freq)
{
int channel = 0;
do
{
//2.4.GHz
if (band == PHY_BAND_2G4)
{
// Check if frequency is in the expected range
if ((freq < 2412) || (freq > 2484))
break;
// Compute the channel number
if (freq == 2484)
channel = 14;
else
channel = (freq - 2407) / 5;
}
//5 GHz
else if (band == PHY_BAND_5G)
{
// Check if frequency is in the expected range
if ((freq < 5005) || (freq > 5825))
break;
// Compute the channel number
channel = (freq - 5000) / 5;
}
}
while(0);
return (channel);
}
/**
****************************************************************************************
* @brief Compute the channel frequency from its number and band
* @param[in] band RF band (must be @ref PHY_BAND_2G4 or @ref PHY_BAND_5G)
* @param[in] channel Channel number
****************************************************************************************
*/
__INLINE uint16_t phy_channel_to_freq(uint8_t band, int channel)
{
uint16_t freq = (uint16_t) - 1;
do
{
//2.4.GHz
if (band == PHY_BAND_2G4)
{
// Check if the channel number is in the expected range
if ((channel < 1) || (channel > 14))
break;
// Compute the channel number
if (channel == 14)
freq = 2484;
else
freq = 2407 + channel * 5;
}
//5 GHz
else if (band == PHY_BAND_5G)
{
// Check if frequency is in the expected range
if ((channel < 1) || (channel > 165))
break;
// Compute the channel number
freq = 5000 + channel * 5;
}
}
while(0);
return (freq);
}
/**
****************************************************************************************
* @brief Modem interrupt service routine.
* This function is called when a Modem interrupt is asserted to the interrupt controller
****************************************************************************************
*/
void phy_mdm_isr(void);
/**
****************************************************************************************
* @brief RC interrupt service routine.
* This function is called when a RC interrupt is asserted to the interrupt controller
****************************************************************************************
*/
void phy_rc_isr(void);
/**
****************************************************************************************
* @brief Indicates if the PHY has radar pulses available or not.
*
* @param[in] rd_idx Index of the radar detection chain that needs to be checked
* (@PHY_PRIM or @PHY_SEC)
*
* @return true if pulse(s) is(are) available, false otherwise
*
****************************************************************************************
*/
bool phy_has_radar_pulse(int rd_idx);
/**
****************************************************************************************
* @brief Read a radar pulse from the FIFO, and writes it to the buffer passed as parameter
*
* @param[in] rd_idx Index of the radar detection chain that needs to be read
* (@PHY_PRIM or @PHY_SEC)
* @param[out] pulse Pointer to the pulse structure where to write to
*
* @return true if a pulse has been written, false otherwise
*
****************************************************************************************
*/
bool phy_get_radar_pulse(int rd_idx, struct phy_radar_pulse *pulse);
/**
****************************************************************************************
* @brief Return the Beamformee capability of the PHY
*
* @return true if Beamformee is supported by the PHY, false otherwise
****************************************************************************************
*/
bool phy_bfmee_supported(void);
/**
****************************************************************************************
* @brief Return the Beamformer capability of the PHY
*
* @return true if Beamformer is supported by the PHY, false otherwise
****************************************************************************************
*/
bool phy_bfmer_supported(void);
/**
****************************************************************************************
* @brief Return the MU-MIMO RX capability of the PHY
*
* @return true if MU-MIMO RX is supported by the PHY, false otherwise
****************************************************************************************
*/
bool phy_mu_mimo_rx_supported(void);
/**
****************************************************************************************
* @brief Return the MU-MIMO TX capability of the PHY
*
* @return true if MU-MIMO TX is supported by the PHY, false otherwise
****************************************************************************************
*/
bool phy_mu_mimo_tx_supported(void);
#if RW_MUMIMO_RX_EN
/**
****************************************************************************************
* @brief Set the MU-MIMO RX group information as received in the VHT Group ID action frame
*
* @param[in] membership_addr Address of the membership status in the received frame
* @param[in] userpos_addr Address of the user position array in the received frame
****************************************************************************************
*/
void phy_set_group_id_info(uint32_t membership_addr, uint32_t userpos_addr);
#endif
/**
****************************************************************************************
* @brief Return the NSS of the PHY
*
* @return Number of Spatial Streams supported by the PHY (start from 0, 0 is for 1 SS)
****************************************************************************************
*/
uint8_t phy_get_nss(void);
/**
****************************************************************************************
* @brief Return the NTX of the PHY
*
* @return Number of antenna supported for TX minus 1 (i.e. 0 means 1 antenna)
****************************************************************************************
*/
uint8_t phy_get_ntx(void);
/**
****************************************************************************************
* @brief Get radio code to set a specific TX power
* Return the idx to use (set in policy table), to conigure a specific TX power. If the TX
* power requested is not possible, it should return idx to get the maximum TX power that
* do not exceed the request. In this case, power parameter should be updated tieh the
* actual TX power set.
*
* @param[in/out] power TX power (in dBm) to configure for the radio, (updated with
* the actual power set if request is not possible)
* @param[out] idx Idx to use in policy table to configure a tx power of <gain>
****************************************************************************************
*/
void phy_get_rf_gain_idx(int8_t *power, uint8_t *idx);
/**
* @brief Get radio's transmission power capabilities
*
* @param[out] max Maximum TX power for the radio (in dBm)
* @param[out] min Minimum TX power for the radio (in dBm)
*/
void phy_get_rf_gain_capab(int8_t *max, int8_t *min);
#if NX_DEBUG_DUMP
/**
****************************************************************************************
* @brief Read the state of all PHY diagnostic ports and put it in the debug dump info
* structure
*
* @param[out] dbg_info Pointer to the debug dump information structure
*
****************************************************************************************
*/
void phy_get_diag_state(struct dbg_debug_info_tag *dbg_info);
#endif
/// @}
#endif //_PHY_H_
Raw
phy_trident.c
/**
****************************************************************************************
*
* @file phy_trident.c
*
* @brief File containing the nX Trident-based physical layer driver API.
*
* Copyright (C) RivieraWaves 2011-2016
*
****************************************************************************************
*/
/**
****************************************************************************************
* @addtogroup PHY
* @{
****************************************************************************************
*/
/*
* INCLUDE FILES
****************************************************************************************
*/
#include "rwnx_config.h"
#include "phy.h"
#include "ke_timer.h"
#include "rd.h"
#include "phy_trident.h"
#include "reg_mdm_stat.h"
#include "reg_mdm_cfg.h"
#include "reg_rc.h"
#include "reg_agc.h"
#include "include.h"
#include "arm_arch.h"
#include "dd_pub.h"
#include "drv_model_pub.h"
#include "sys_ctrl_pub.h"
#include "target_util_pub.h"
#include "uart_pub.h"
#include "intc_pub.h"
#include "power_save_pub.h"
/*
* STRUCTURES
****************************************************************************************
*/
/// Structure containing the parameters of the Trident PHY configuration
struct phy_trd_cfg_tag
{
/// MDM type(nxm)(upper nibble) and MDM2RF path mapping(lower nibble)
uint8_t path_mapping;
/// TX DC offset compensation
uint32_t tx_dc_off_comp;
};
/*
* GLOBALS
****************************************************************************************
*/
/// Global PHY driver environment.
struct phy_env_tag phy_env[1];
/*
* FUNCTION DEFINITIONS
****************************************************************************************
*/
//BK,170206,solve input-power vs PER discontinuous issue.
#define NEW_AGC_PARA 1
//BK,170206,solve large input-power 0% PER issue.
#define RF_DOWN_ENABLE 0
const uint32_t agc_ram_parameter[] =
{
#if NEW_AGC_PARA //solve input-power vs PER discontinuous issue.
0x30000000,
0x01000000,
0xa800000b,
0x00000000,
0x30000000,
0x91000000,
0x04000031,
0x00000000,
0x2000008f,
0x0400005d,
0x00000000,
0x34014000,
0x10000001,
0x08000012,
0x00000000,
0x240c808f,
0x080001ac,
0x00000000,
0x30000000,
0x41000000,
0x04000016,
0x00000000,
0x30000000,
0x51000101,
0x0400001a,
0x00000000,
0x34028000,
0x12004803,
#if RF_DOWN_ENABLE
0x0870481e,
#else
0x0810481e,
#endif
0x00000000,
0x30000000,
0x01000000,
0x04000022,
0x00000000,
0x34008001,
0x64000001,
0x08000026,
0x00000000,
0x3402800f,
0x68002101,
0x0800002a,
0x00000000,
0x2000139f,
0x0412080b,
0x00000000,
0x4400438f,
0xa410497c,
0x081049a0,
0x00000000,
0x50000000,
0x51000101,
0x1851003e,
0x0c000036,
0x00000000,
0x30000000,
0x12002701,
0x1c00003a,
0x00000000,
0x30000000,
0x61020202,
0x04000042,
0x00000000,
0x30000000,
0x12000601,
0x1c000042,
0x00000000,
0x90000000,
0x52000000,
0x20900049,
0x28b00049,
0x30d00049,
0x04000008,
0x00000000,
0x24010000,
0x0800004c,
0x00000000,
0x3400400e,
0x52000000,
0x08000050,
0x00000000,
0x340204ae,
0x31191910,
0x08000054,
0x00000000,
0x30000eae,
0x51000101,
0x04000058,
0x00000000,
0x60000eae,
0x0c00006c,
0x1000006f,
0x14600072,
0x00000000,
0x340204af,
0x31191910,
0x08000061,
0x00000000,
0x30000eaf,
0x51000101,
0x04000065,
0x00000000,
0x20000eaf,
0x04000068,
0x00000000,
0x4404ceaf,
0x61704875,
0x08000075,
0x00000000,
0x240a0eae,
0x09800075,
0x00000000,
0x24050eae,
0x09800075,
0x00000000,
0x24010eae,
0x09800075,
0x00000000,
0x80000eaf,
0x6580487b,
0x6410487f,
0x60104883,
0x04104887,
0x00000000,
0x30000eaf,
0x41000300,
0x0400008b,
0x00000000,
0x30000eaf,
0x41000100,
0x0400008b,
0x00000000,
0x30000eaf,
0x41000100,
0x0400008b,
0x00000000,
0x30000eaf,
0x41000000,
0x0400008b,
0x00000000,
0x40000eaf,
0xa4000093,
0x0400008f,
0x00000000,
0x30000000,
0x14eaed03,
0x1c000093,
0x00000000,
0x60000000,
0x28b00098,
0x30d00098,
0x0400009b,
0x00000000,
0x24010000,
0x0800009b,
0x00000000,
0x34008000,
0x10000000,
0x0800009f,
0x00000000,
0x34014005,
0x63000102,
0x080000a3,
0x00000000,
0x30000007,
0x50000001,
0x040000a7,
0x00000000,
0x30000007,
0x32202071,
0x040000ab,
0x00000000,
0x30000007,
0x61030303,
0x040000af,
0x00000000,
0x340202ef,
0x31202021,
0x080000b3,
0x00000000,
0x34050aef,
0x90000000,
0x080000b7,
0x00000000,
0x30000aef,
0x12000004,
0x040000bb,
0x00000000,
0x30000aef,
0x33000001,
0x040000bf,
0x00000000,
0x60000eaf,
0x658048c4,
0x658000c8,
0x041048cc,
0x00000000,
0x30000eaf,
0x41000301,
0x040000d4,
0x00000000,
0x30000eaf,
0x41000101,
0x040000d4,
0x00000000,
0x30000eaf,
0x41000001,
0x040000d0,
0x00000000,
0x30000eaf,
0x51000001,
0x040000d4,
0x00000000,
0x34190bef,
0x52000000,
0x080000d8,
0x00000000,
0x30000aef,
0x33000101,
0x040000dc,
0x00000000,
0xe0000eaf,
0x6da048e5,
0x658048e9,
0x601048f1,
0x641048f9,
0x681048ed,
0x6c1048f5,
0x041048fd,
0x00000000,
0x30000eaf,
0x41030002,
0x04000105,
0x00000000,
0x30000eaf,
0x41000302,
0x04000125,
0x00000000,
0x30000eaf,
0x41010002,
0x04000105,
0x00000000,
0x30000eaf,
0x41000102,
0x04000125,
0x00000000,
0x30000eaf,
0x41010002,
0x04000105,
0x00000000,
0x30000eaf,
0x41000102,
0x04000125,
0x00000000,
0x30000eaf,
0x41000002,
0x04000101,
0x00000000,
0x3000028f,
0x51000001,
0x04000198,
0x00000000,
0x5000028f,
0x51000001,
0xa0000198,
0x0400010a,
0x00000000,
0x3401428f,
0x10000001,
0x0800010e,
0x00000000,
0x3401c000,
0x14eaed03,
0x08000112,
0x00000000,
0x34008000,
0x10000000,
0x08000116,
0x00000000,
0x24014005,
0x08000119,
0x00000000,
0x3400528f,
0x3400289c,
0x0400011d,
0x00000000,
0x3000128f,
0x35d4509c,
0x04000121,
0x00000000,
0x3000128f,
0x50000100,
0x04000169,
0x00000000,
0x7432028f,
0x65000003,
0x7c00012b,
0x80104961,
0x08000165,
0x00000000,
0x3000028f,
0x41000000,
0x0400012f,
0x00000000,
0x8432028f,
0x8400013d,
0x80104961,
0x08104935,
0x88104939,
0x00000000,
0x3000008f,
0x41000000,
0x881049a0,
0x00000000,
0x3000008f,
0x41000000,
0x0410482d,
0x00000000,
0x34004005,
0x61020202,
0x08104941,
0x00000000,
0x6419000f,
0x80104946,
0x08000135,
0x88104939,
0x00000000,
0x3000000f,
0x15eeea07,
0x1c00014e,
0x00000000,
0x3000000f,
0x51000001,
0x04000152,
0x00000000,
0x3000000f,
0x10000001,
0x0400014a,
0x00000000,
0x24008000,
0x08000155,
0x00000000,
0x30000000,
0x10000000,
0x04000159,
0x00000000,
0x34010005,
0x61030303,
0x0800015d,
0x00000000,
0x30000007,
0x50000001,
0x04000161,
0x00000000,
0x3000008f,
0x41000000,
0x8810482d,
0x00000000,
0x3000038f,
0x01000000,
0x04000198,
0x00000000,
0x4577138f,
0x70000171,
0x0800016d,
0x00000000,
0x3000038f,
0x51000100,
0x04000198,
0x00000000,
0x3000138f,
0x41000000,
0x04000175,
0x00000000,
0x3000138f,
0x65000003,
0x04000179,
0x00000000,
0x2000108f,
0x881049a0,
0x00000000,
0x3000018f,
0x66000001,
0x04000180,
0x00000000,
0x34018000,
0x10000001,
0x08104984,
0x00000000,
0x30000000,
0x61010101,
0x04000188,
0x00000000,
0x2403c00f,
0x0800018b,
0x00000000,
0x5405000f,
0x95000000,
0xb4000190,
0x08000194,
0x00000000,
0x3000000f,
0x52000001,
0x04000008,
0x00000000,
0x3000000f,
0x52000000,
0x0400000b,
0x00000000,
0x3401438f,
0x10000001,
0x0810499c,
0x00000000,
0x34028000,
0x12004803,
0x087049a4,
0x00000000,
0x34004000,
0x95000000,
0x0810480b,
0x00000000,
0x34028000,
0x80000000,
0x041049a8,
0x00000000,
0x34028000,
0x95000000,
0x0410481e,
0x00000000,
0x3000008f,
0x14eaed03,
0x1c0001b0,
0x00000000,
0x3401c000,
0x52000000,
0x080001b4,
0x00000000,
0x34008000,
0x10000000,
0x080001b8,
0x00000000,
0x24014005,
0x080001bb,
0x00000000,
0x3000128f,
0x3400209c,
0x040001bf,
0x00000000,
0x3000128f,
0x35d4509c,
0x040001c3,
0x00000000,
0x3000128f,
0x50000100,
0x040001c7,
0x00000000,
0x4577138f,
0x700001cb,
0x0800016d,
0x00000000,
0x3000138f,
0x41000000,
0x040001cf,
0x00000000,
0x3000138f,
0x65000003,
0x040001d3,
0x00000000,
0x2000138f,
0x881049a0,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x100c0d11
#else
0x30000000,
0x01000000,
0xa800000b,
0x00000000,
0x30000000,
0x91000000,
0x04000031,
0x00000000,
0x2000008f,
0x04000079,
0x00000000,
0x34014000,
0x10000001,
0x08000012,
0x00000000,
0x240c808f,
0x080001d3,
0x00000000,
0x30000000,
0x41000000,
0x04000016,
0x00000000,
0x30000000,
0x51000101,
0x0400001a,
0x00000000,
0x34028000,
0x12004603,
#if RF_DOWN_ENABLE
0x0870481e,
#else
0x0810481e,
#endif
0x00000000,
0x30000000,
0x01000000,
0x04000022,
0x00000000,
0x34008001,
0x64000001,
0x08000026,
0x00000000,
0x3402800f,
0x68002101,
0x0800002a,
0x00000000,
0x2000139f,
0x0412080b,
0x00000000,
0x4400438f,
0xa41049a3,
0x081049c7,
0x00000000,
0x90000000,
0x51000101,
0x18000048,
0x14000044,
0x10000040,
0x0c000038,
0x00000000,
0x30000000,
0x12002601,
0x1c00003c,
0x00000000,
0x30000000,
0x61020202,
0x0400004c,
0x00000000,
0x30000000,
0x12000f01,
0x1c00004c,
0x00000000,
0x30000000,
0x12000601,
0x1c00004c,
0x00000000,
0x30000000,
0x12000301,
0x1c00004c,
0x00000000,
0xf0000000,
0x52000000,
0x20000056,
0x24000059,
0x2800005c,
0x2c00005f,
0x30000062,
0x34000065,
0x04000008,
0x00000000,
0x24010000,
0x08000068,
0x00000000,
0x24050000,
0x08000068,
0x00000000,
0x24010000,
0x08000068,
0x00000000,
0x24008000,
0x08000068,
0x00000000,
0x24014000,
0x08000068,
0x00000000,
0x24008000,
0x08000068,
0x00000000,
0x3400400e,
0x52000000,
0x0800006c,
0x00000000,
0x340204ae,
0x31191910,
0x08000070,
0x00000000,
0x30000eae,
0x51000101,
0x04000074,
0x00000000,
0x60000eae,
0x0c000088,
0x1000008b,
0x1460008e,
0x00000000,
0x340204af,
0x31191910,
0x0800007d,
0x00000000,
0x30000eaf,
0x51000101,
0x04000081,
0x00000000,
0x20000eaf,
0x04000084,
0x00000000,
0x4404ceaf,
0x61704891,
0x08000091,
0x00000000,
0x240a0eae,
0x09800091,
0x00000000,
0x24050eae,
0x09800091,
0x00000000,
0x24010eae,
0x09800091,
0x00000000,
0x80000eaf,
0x65804897,
0x6410489b,
0x6010489f,
0x041048a3,
0x00000000,
0x30000eaf,
0x41000300,
0x040000a7,
0x00000000,
0x30000eaf,
0x41000100,
0x040000a7,
0x00000000,
0x30000eaf,
0x41000100,
0x040000a7,
0x00000000,
0x30000eaf,
0x41000000,
0x040000a7,
0x00000000,
0x40000eaf,
0xa40000af,
0x040000ab,
0x00000000,
0x30000000,
0x14eaed0b,
0x1c0000af,
0x00000000,
0xa0000000,
0x280000b6,
0x2c0000b9,
0x300000bc,
0x300000bf,
0x040000c2,
0x00000000,
0x24008000,
0x080000c2,
0x00000000,
0x24008000,
0x080000c2,
0x00000000,
0x24014000,
0x080000c2,
0x00000000,
0x24008000,
0x080000c2,
0x00000000,
0x34008000,
0x10000000,
0x080000c6,
0x00000000,
0x34014005,
0x63000102,
0x080000ca,
0x00000000,
0x30000007,
0x50000001,
0x040000ce,
0x00000000,
0x30000007,
0x32202071,
0x040000d2,
0x00000000,
0x30000007,
0x61030303,
0x040000d6,
0x00000000,
0x340202ef,
0x31202021,
0x080000da,
0x00000000,
0x34050aef,
0x90000000,
0x080000de,
0x00000000,
0x30000aef,
0x12000004,
0x040000e2,
0x00000000,
0x30000aef,
0x33000001,
0x040000e6,
0x00000000,
0x60000eaf,
0x658048eb,
0x658000ef,
0x041048f3,
0x00000000,
0x30000eaf,
0x41000301,
0x040000fb,
0x00000000,
0x30000eaf,
0x41000101,
0x040000fb,
0x00000000,
0x30000eaf,
0x41000001,
0x040000f7,
0x00000000,
0x30000eaf,
0x51000001,
0x040000fb,
0x00000000,
0x34190bef,
0x52000000,
0x080000ff,
0x00000000,
0x30000aef,
0x33000101,
0x04000103,
0x00000000,
0xe0000eaf,
0x6da0490c,
0x65804910,
0x60104918,
0x64104920,
0x68104914,
0x6c10491c,
0x04104924,
0x00000000,
0x30000eaf,
0x41030002,
0x0400012c,
0x00000000,
0x30000eaf,
0x41000302,
0x0400014c,
0x00000000,
0x30000eaf,
0x41010002,
0x0400012c,
0x00000000,
0x30000eaf,
0x41000102,
0x0400014c,
0x00000000,
0x30000eaf,
0x41010002,
0x0400012c,
0x00000000,
0x30000eaf,
0x41000102,
0x0400014c,
0x00000000,
0x30000eaf,
0x41000002,
0x04000128,
0x00000000,
0x3000028f,
0x51000001,
0x040001bf,
0x00000000,
0x5000028f,
0x51000001,
0xa00001bf,
0x04000131,
0x00000000,
0x3401428f,
0x10000001,
0x08000135,
0x00000000,
0x3401c000,
0x14eaed0b,
0x08000139,
0x00000000,
0x34008000,
0x10000000,
0x0800013d,
0x00000000,
0x24014005,
0x08000140,
0x00000000,
0x3400528f,
0x3400289c,
0x04000144,
0x00000000,
0x3000128f,
0x35d4509c,
0x04000148,
0x00000000,
0x3000128f,
0x50000100,
0x04000190,
0x00000000,
0x7432028f,
0x65000003,
0x7c000152,
0x80104988,
0x0800018c,
0x00000000,
0x3000028f,
0x41000000,
0x04000156,
0x00000000,
0x8432028f,
0x84000164,
0x80104988,
0x0810495c,
0x88104960,
0x00000000,
0x3000008f,
0x41000000,
0x881049c7,
0x00000000,
0x3000008f,
0x41000000,
0x0410482d,
0x00000000,
0x34004005,
0x61020202,
0x08104968,
0x00000000,
0x6419000f,
0x8010496d,
0x0800015c,
0x88104960,
0x00000000,
0x3000000f,
0x15eeea0f,
0x1c000175,
0x00000000,
0x3000000f,
0x51000001,
0x04000179,
0x00000000,
0x3000000f,
0x10000001,
0x04000171,
0x00000000,
0x24008000,
0x0800017c,
0x00000000,
0x30000000,
0x10000000,
0x04000180,
0x00000000,
0x34010005,
0x61030303,
0x08000184,
0x00000000,
0x30000007,
0x50000001,
0x04000188,
0x00000000,
0x3000008f,
0x41000000,
0x8810482d,
0x00000000,
0x3000038f,
0x01000000,
0x040001bf,
0x00000000,
0x4577138f,
0x70000198,
0x08000194,
0x00000000,
0x3000038f,
0x51000100,
0x040001bf,
0x00000000,
0x3000138f,
0x41000000,
0x0400019c,
0x00000000,
0x3000138f,
0x65000003,
0x040001a0,
0x00000000,
0x2000108f,
0x881049c7,
0x00000000,
0x3000018f,
0x66000001,
0x040001a7,
0x00000000,
0x34018000,
0x10000001,
0x081049ab,
0x00000000,
0x30000000,
0x61010101,
0x040001af,
0x00000000,
0x2403c00f,
0x080001b2,
0x00000000,
0x5405000f,
0x95000000,
0xb40001b7,
0x080001bb,
0x00000000,
0x3000000f,
0x52000001,
0x04000008,
0x00000000,
0x3000000f,
0x52000000,
0x0400000b,
0x00000000,
0x3401438f,
0x10000001,
0x081049c3,
0x00000000,
0x34028000,
0x12004603,
0x087049cb,
0x00000000,
0x34004000,
0x95000000,
0x0810480b,
0x00000000,
0x34028000,
0x80000000,
0x041049cf,
0x00000000,
0x34028000,
0x95000000,
0x0410481e,
0x00000000,
0x3000008f,
0x14eaed0b,
0x1c0001d7,
0x00000000,
0x3401c000,
0x52000000,
0x080001db,
0x00000000,
0x34008000,
0x10000000,
0x080001df,
0x00000000,
0x24014005,
0x080001e2,
0x00000000,
0x3000128f,
0x3400209c,
0x040001e6,
0x00000000,
0x3000128f,
0x35d4509c,
0x040001ea,
0x00000000,
0x3000128f,
0x50000100,
0x040001ee,
0x00000000,
0x4577138f,
0x700001f2,
0x08000194,
0x00000000,
0x3000138f,
0x41000000,
0x040001f6,
0x00000000,
0x3000138f,
0x65000003,
0x040001fa,
0x00000000,
0x2000138f,
0x881049c7,
0x00000000,
0x00000000,
0x00000000,
0x10080c10
#endif
};
void phy_pre_agc_init(void)
{
uint32_t i;
uint32_t len;
uint32_t *src, *dst;
uint32_t agc_cntl_reg;
uint32_t clk_ctrl_reg;
agc_cntl_reg = agc_rwnxagccntl_get();
agc_cntl_reg |= AGC_AGCFSMRESET_BIT;
agc_rwnxagccntl_set(agc_cntl_reg);
clk_ctrl_reg = mdm_memclkctrl0_get();
clk_ctrl_reg &= ~MDM_AGCMEMCLKCTRL_BIT;
mdm_memclkctrl0_set(clk_ctrl_reg);
/*init agc parameters*/
len = sizeof(agc_ram_parameter) >> 2;
dst = (uint32_t *)PHY_AGC_UCODE_ADDR;
src = (uint32_t *)agc_ram_parameter;
for(i = 0; i < len; i ++)
{
*dst ++ = *src ++;
}
mdm_agcclkforce_setf(1); /*the issue about reset agc*/
agc_cntl_reg = agc_rwnxagccntl_get();
agc_cntl_reg &= ~AGC_AGCFSMRESET_BIT;
agc_rwnxagccntl_set(agc_cntl_reg);
clk_ctrl_reg = mdm_memclkctrl0_get();
clk_ctrl_reg |= MDM_AGCMEMCLKCTRL_BIT;
mdm_memclkctrl0_set(clk_ctrl_reg);
}
/**
****************************************************************************************
* @brief Perform a write access on radio registers through the radio controller.
* The SPI command is sent only to the radios on the used RC paths (rc_path_sel).
* To limit the RC register access, the whole RC register value is set in one access
* except the START_DONE bit which will trigger the SPI transfer and also signal its end
* when cleared by HW.
*
* @param[in] addr Address of the register to write in.
* @param[in] value Value to write.
*
* @warning The function does not check the consistency of the parameters provided.
****************************************************************************************
*/
void phy_rc_rf_reg_write(uint8_t addr, uint16_t value)
{
}
/**
****************************************************************************************
* @brief Trident board IO Expander init.
* Given it is the components which routes important power down and lock detect signals,
* it should be initialized first before the components are interacted with.
****************************************************************************************
*/
void phy_iox_init(void)
{
}
/**
****************************************************************************************
* @brief Trident board 8b ADCs initialization for RSSI/Temperature/Power read back.
****************************************************************************************
*/
//todo init or cfg in case we change ADCs during run for rssi/power?
void phy_adc8b_init(void)
{
//do nothing, use reg force when we'll need fcns to gather data
}
/**
****************************************************************************************
* @brief Trident board 12b ADCs calibration.
****************************************************************************************
*/
void phy_adc12b_init(void)
{
#if (TIADC_VER == 1) //TI ADC
//disable RC auto power mode
trd_adc_autopower_setf(0);
//reset ADCs,
trd_adc_reset_setf(1);
trd_adc_reset_setf(0);
// prescaler=6: spi_freq=80/(presc+1) ; max 20MHz
trd_adc_spi_prescaler_setf(4);
//switch off all ADCs
phy_trd_adc_reg_write(0x00, 0x00D, 7);
//switch on used ADC
phy_trd_adc_reg_write(0x00, 0x000, phy_env->rf_path_sel);
//OTHER REG SETTINGS
phy_trd_adc_reg_write(0x04, 0x000, phy_env->rf_path_sel);
// 2's complement
phy_trd_adc_reg_write(0x0A, 0x000, phy_env->rf_path_sel);
phy_trd_adc_reg_write(0x0B, 0x000, phy_env->rf_path_sel);
//fine gain 6dB
phy_trd_adc_reg_write(0x0C, 0x600, phy_env->rf_path_sel);
//Override, byte wise, MSB first, coarse gain 3.5dB,12 bits serial,ddr clocking, 2 wire interface
phy_trd_adc_reg_write(0x0D, 0x421, phy_env->rf_path_sel); //401 without coarse gain
//termination, drive clk output
phy_trd_adc_reg_write(0x10, 0x000, phy_env->rf_path_sel);
//bit/byte wise, termination of data outputs
phy_trd_adc_reg_write(0x11, 0x000, phy_env->rf_path_sel);
//DESERIALIZER----------------------------
//Path A
if (phy_is_bit_set(phy_env->rf_path_sel, RF_PATH_A))
{
//deserializer reset
trd_deser_cha_rst_n_setf(0);
//lift reset
trd_deser_cha_rst_n_setf(1);
//deserializer calibration
trd_deser_cha_calib_start_setf(1);
//poll until done
while(!trd_deser_cha_calib_done_getf());
//todo does the start have to be put back to 0 by SW or auto-clear at done?
trd_deser_cha_calib_start_setf(0);
}
//Path B
if (phy_is_bit_set(phy_env->rf_path_sel, RF_PATH_B))
{
//deserializer reset
trd_deser_chb_rst_n_setf(0);
//lift reset
trd_deser_chb_rst_n_setf(1);
//deserializer calibration
trd_deser_chb_calib_start_setf(1);
//poll until done
while(!trd_deser_chb_calib_done_getf());
//todo does the start have to be put back to 0 by SW or auto-clear at done?
trd_deser_chb_calib_start_setf(0);
}
//Path C
if (phy_is_bit_set(phy_env->rf_path_sel, RF_PATH_C))
{
//deserializer reset
trd_deser_chc_rst_n_setf(0);
//lift reset
trd_deser_chc_rst_n_setf(1);
//deserializer calibration
trd_deser_chc_calib_start_setf(1);
//poll until done
while(!trd_deser_chc_calib_done_getf());
//todo does the start have to be put back to 0 by SW or auto-clear at done?
trd_deser_chc_calib_start_setf(0);
}
#else //Beken ADC
rc_adda_reg0_set(0x0801A554);
rc_adda_reg1_set(0x88924204);
rc_adda_reg2_set(0x10484806);
rc_adda_reg3_set(0x8C0C80C8);
rc_adda_reg4_set(0x03010000);
rc_adda_reg5_set(0xF80022ED);
while(rc_adda_reg_stat_getf() & 0x3f);
#endif
}
/**
****************************************************************************************
* @brief Adjust TX digital gains wrt DC offset compensation to avoid DACs saturation
****************************************************************************************
*/
static void adjust_txdiggains(uint32_t dc_cmp)
{
uint8_t i_abscmp, j_abscmp, max_abscmps;
i_abscmp = (dc_cmp & MDM_TXIDCOFFSET0_MASK) >> MDM_TXIDCOFFSET0_LSB;
j_abscmp = (dc_cmp & MDM_TXQDCOFFSET0_MASK) >> MDM_TXQDCOFFSET0_LSB;
max_abscmps = i_abscmp > j_abscmp ? i_abscmp : j_abscmp;
// 12bits range
mdm_fectrl0_pack(MDM_TX80DIGGAINLIN0_RST,
MDM_TX40DIGGAINLIN0_RST * (2047 - max_abscmps) / 2047,
MDM_TX20DIGGAINLIN0_RST * (2047 - max_abscmps) / 2047);
}
/**
****************************************************************************************
* @brief Modem initialization function.
* This function is called at reset time together with radio init, and
* prepares the modem for rx or tx.
****************************************************************************************
*/
static void phy_mdm_init(uint32_t tx_dc_off_comp)
{
intc_service_register(FIQ_MODEM, PRI_FIQ_MODEM, phy_mdm_isr);
//turn on the 3 blocks: TX, AGC-CCA, RX - they are at 1 by default in regs ...
mdm_rxtxpwrctrl_pack(1, 1, 1);
mdm_dcoffset0_set(tx_dc_off_comp);
adjust_txdiggains(tx_dc_off_comp);
// Parameters for 40MHz bandwidth by default
mdm_txctrl0_set(0x00000168);
mdm_rxctrl0_set(0x00160005);
mdm_tbectrl0_set(0x0C0F0702);
#if (NX_MDM_VER == 11)
mdm_tbectrl2_set(0x0FF07005);
#endif
mdm_waithtstf_setf(15);
mdm_delaynormalgi_setf(17);
// CPE mode
mdm_cpemode_setf(0);
// Enable CCA lock IRQ
mdm_irqctrl_set(MDM_IRQCCATIMEOUTEN_BIT);
PHY_WPRT("phy_mdm_init-->Static MDM settings done\r\n");
}
void phy_enable_lsig_intr(void)
{
uint32_t val;
val = mdm_irqctrl_get();
val |= MDM_IRQLSIGVALIDEN_BIT;
mdm_irqctrl_set(val);
os_printf("lsigEn-0x2000:%x\r\n", mdm_irqctrl_get());
}
void phy_disable_lsig_intr(void)
{
uint32_t val;
val = mdm_irqctrl_get();
val &= (~MDM_IRQLSIGVALIDEN_BIT);
mdm_irqctrl_set(val);
os_printf("lsigDis-0x2000:%x\r\n", mdm_irqctrl_get());
}
/**
****************************************************************************************
* @brief AGC initialization function.
****************************************************************************************
*/
static void phy_agc_init(void)
{
phy_pre_agc_init();
// AGC events
#if (NX_MDM_VER == 10)
agc_rwnxagcevt2_set(0x3955b004);
#else
agc_rwnxagcevtsat_set(0x05044804);
agc_rwnxagcevtdet_set(0x3D449008);
agc_rwnxagcevtdis_set(0x3955B00B);
agc_rwnxagcevtdsssdet_set(0x04F7480F);
// ADC sat thd
agc_rwnxagcsat_set(0x08393537);
#endif
//agc_rwnxagcevt2_set(0x3955b004);
// AGCCROSS (disable crossing detection)
agc_rwnxagccross_set(0x002803f0);
// AGCRAMP (reduce ramp-down detection level)
agc_rwnxagcramp_set(0x07200710);
// RWNXAGCCCA1 (CCA{FALL,RISE}THRDBM)
// for when RWNXAGCCCACTRL[CCAENERGYEN] is on
agc_rwnxagccca1_set((agc_rwnxagccca1_get() & ~0x000ff0ff) | 0x000bf0c3);
// RWNXAGCCCACTRL
agc_rwnxagcccactrl_set((agc_rwnxagcccactrl_get() & ~0x00000fff) | 0x00000377);
// Configure CCA timeout
agc_rwnxagcccatimeout_set(8000000); // 100ms
// AGCGain Range
agc_rfgainmaxdb_setf(0x4b);
// AGC Power Estimate Bias
agc_vpeakadcqdbv_setf((uint8_t) - 32);
PHY_WPRT("phy_agc_init-->cca\r\n");
}
/**
****************************************************************************************
* @brief Set band 2.4GHz/5GHz in RC and RF chips.
* @param[in] band Band value - 0=2.4GHz, 1=5GHz
* @param[in] freq Channel frequency in MHz
****************************************************************************************
*/
static void phy_set_band(uint8_t band, uint16_t freq)
{
//MDM and AGC band related settings
if (band == PHY_BAND_2G4)
{
//mdm settings
mdm_rxallowdsss_setf(1);
//agc cca
agc_ofdmonly_setf(0);
}
else
{
//mdm settings
mdm_rxallowdsss_setf(0);
//agc cca
agc_ofdmonly_setf(1);
}
}
/**
****************************************************************************************
* @brief Function used to regroup the waiting , polling and Lock Detect values
* @return Boolean value of lock state: true=locked, false=lock failed
****************************************************************************************
*/
static bool phy_locked(void)
{
return true;
}
#if !CFG_SUPPORT_CALIBRATION
#define RC_TRX_REG28_ADDR 0x08628078
__INLINE void rc_trx_reg28_set(uint32_t value)
{
REG_PL_WR(RC_TRX_REG28_ADDR, value);
}
#endif
/**
****************************************************************************************
* @brief MAXIM Radio(s) initialization function.
* This function is called at FW initialization or after phy_stop().
* It will set RC register values and also RF register value using RC SPI control. Most
* of the register values set in the radio(s) are static for the duration of SW run.
****************************************************************************************
*/
#if CFG_SUPPORT_CALIBRATION
extern INT32 rwnx_cal_load_trx_rcbekn_reg_val(void);
#endif
static void phy_rf_init(void)
{
#if !CFG_SUPPORT_CALIBRATION
//initial Beken TRX
#if (CFG_RUNNING_PLATFORM == FPGA_PLATFORM)
rc_trx_reg0_set(0x0813EF5E); //RF Config. V1.6
rc_trx_reg1_set(0x01000000);
rc_trx_reg2_set(0x00000000);
rc_trx_reg3_set(0x00000000);
rc_trx_reg4_set(0x28021D00);
rc_trx_reg5_set(0x05326C7A);
rc_trx_reg6_set(0x72ec820e); //0x00FF104C
rc_trx_reg7_set(0x0922483E); //0x0922483F 20150630
rc_trx_reg8_set(0x0768A94A);
rc_trx_reg9_set(0x000003AF);
rc_trx_reg10_set(0x82383330);
rc_trx_reg11_set(0x16A46D84);
rc_trx_reg12_set(0x01A187DD);// //0x01A184CC 722 //0x01A187FF //0x01A1F4F1 Feb 09 2015 Allen
rc_trx_reg13_set(0xFDF90238);
rc_trx_reg14_set(0xFA01BCF0);
rc_trx_reg15_set(0x40000030);
rc_trx_reg16_set(0xF0000000);
rc_trx_reg17_set(0x00000000);
rc_trx_reg18_set(0x202D5D01);//0x206D5D01
rc_trx_reg19_set(0x05164145);
rc_trx_reg20_set(0x8080FF30); //
rc_trx_reg21_set(0x80808080);
rc_trx_reg22_set(0x80808080);
rc_trx_reg23_set(0x80808080);
rc_trx_reg24_set(0x80808080);
rc_trx_reg25_set(0x80808080);
rc_trx_reg26_set(0x80808080);
rc_trx_reg27_set(0x80808080);
rc_trx_reg28_set(0x2004AFF9);
#else
rc_trx_reg0_set(0x0811EF5E);
rc_trx_reg1_set(0x01000000);
rc_trx_reg2_set(0x00000000);
rc_trx_reg3_set(0x00000000);
rc_trx_reg4_set(0x38025E88);
rc_trx_reg5_set(0x2555EC7A);
rc_trx_reg6_set(0x5FA4410C);
rc_trx_reg7_set(0x202C48F5);
rc_trx_reg8_set(0x076CA9CA);
rc_trx_reg9_set(0x000003AF);
rc_trx_reg10_set(0x82382330);
rc_trx_reg11_set(0x28444884);
rc_trx_reg12_set(0x01A183FD);
rc_trx_reg13_set(0xDDF90339);
rc_trx_reg14_set(0xDA01BCF0);
rc_trx_reg15_set(0x00018000);
rc_trx_reg16_set(0xD0000000);
rc_trx_reg17_set(0x00000000);
rc_trx_reg18_set(0xD0000C01);
rc_trx_reg19_set(0x7B305ECC);
rc_trx_reg20_set(0x827C827C);
rc_trx_reg21_set(0x86788678);
rc_trx_reg22_set(0x8C748C74);
rc_trx_reg23_set(0xA45F9868);
rc_trx_reg24_set(0xA45FA45F);
rc_trx_reg25_set(0xA55EA45F);
rc_trx_reg26_set(0xA55DA55E);
rc_trx_reg27_set(0xA55DA55D);
rc_trx_reg28_set(0x20000000);
#endif
#else
#endif
while(rc_beken_spi_get() & 0x0fffffff); //wait rf register write done
rc_ch0_rx_onoff_delay_pack( 1, 1);
rc_ch0_tx_onoff_delay_pack( 1, 1); //old on delay 0x41
rc_ch0_pa_onoff_delay_pack( 1, 0x10);//old on delay 0x41
rc_ch0_shdn_onoff_delay_pack(1, 1);
rc_ch0_en_setf(1);
rc_rc_en_setf(1);
PHY_WPRT("phy_rf_init-->RC static regs set and RC enabled\r\n");
if (!phy_locked())
{
//todo do what???
}
}
/**
****************************************************************************************
* @brief Trident board components init
****************************************************************************************
*/
void phy_rcbeken_init()
{
#if !CFG_SUPPORT_CALIBRATION
#if (CFG_RUNNING_PLATFORM == FPGA_PLATFORM)
rc_beken_spi_set(0x70000000); //set spi_prescaler. spi clock frequency set 5Mbps
rc_ch0_force_set(0x00010003);
rc_misc_force_set(0x00000001);
//rc_rx_avg_calc_set(0x2004aff9); //huaming
rc_rx_avg_calc_set(0x3004aff9);
rc_rx_calib_en_set(0x00); // 0x4004aff9
rc_rx_dc_wr_set(0x0004aff9);
rc_rx_error_wr_set(0x01ff0000);
rc_tx_mode_cfg_set(0x06000200);
rc_tx_sin_cfg_set(0x2cc0c000);
rc_tx_dc_comp_set(0x0202020b);
rc_tx_gain_comp_set(0x03ff03e0); //20150722 0x03ff03e2
rc_tx_phase_ty2_comp_set(0x021D01FE);
rc_tx_other_cfg_set(0xc8ac9d40);
rc_agc_cfg_set(0x00445460);
rc_trx_spi_intlv_set(0x00000064);
#else
rc_beken_spi_set(0xF0000000); //set spi_prescaler. spi clock frequency set 5Mbps
rc_ch0_force_set(0x00010005);
rc_misc_force_set(0x00000002);
//rc_rx_avg_calc_set(0x2004aff9); //huaming
rc_rx_avg_calc_set(0x1002DF4B);
rc_rx_calib_en_set(0x00000000); // 0x4004aff9
rc_rx_dc_wr_set(0x00000000);
rc_rx_error_wr_set(0x020003EC);
rc_tx_mode_cfg_set(0x218B018B);
rc_tx_sin_cfg_set(0x2CC02000);
rc_tx_dc_comp_set(0x020201F1);
rc_tx_gain_comp_set(0x03FF03F3); //20150722 0x03ff03e2
rc_tx_phase_ty2_comp_set(0x01F80200);
rc_tx_other_cfg_set(0x48A79D40); // soc platform, rc_beken 0x1050148<31bit> should be 0
rc_agc_cfg_set(0x0002567A);
rc_trx_spi_intlv_set(0x80000064);
#endif
#else
rwnx_cal_load_trx_rcbekn_reg_val();
#endif
rc_dsel_va_setf(0x1); /* TSSI or AGC gain setting for versiong A, output 0: TSSI 1:AGC gain setting*/
}
static void phy_trident_init(void)
{
//IO Expander first - special component
phy_iox_init();
//RF Reset
rc_spi_reset_setf(1);
rc_spi_reset_setf(0);
phy_rcbeken_init(); //rc_beken initial
PHY_WPRT("phy_trident_init-->RF register reset done\r\n");
//phy path to rf path mapping (given at phy init from nvds)
//front end delay
rc_fe_rx_del_set(0x12c);
phy_adc12b_init();
phy_adc8b_init();
}
static int force2040_toggle(uint8_t chantype)
{
uint32_t rxmodes, f2040_val, f2040_msk;
volatile uint32_t i;
f2040_msk = MDM_FORCE40_BIT | MDM_FORCE20_BIT;
if (chantype == PHY_CHNL_BW_20)
f2040_val = MDM_FORCE20_BIT;
else if (chantype == PHY_CHNL_BW_40)
f2040_val = MDM_FORCE40_BIT;
else
f2040_val = 0;
rxmodes = (mdm_rxmodes_get() & ~f2040_msk) | f2040_val;
mdm_rxmodes_set(rxmodes);
for(i = 0; i < 1000; i ++);
/*
modem reset
*/
sddev_control(SCTRL_DEV_NAME, CMD_SCTRL_MODEM_CORE_RESET, 0);
/* init some paramters of rf */
phy_trident_init();
phy_rf_init();
return 0;
}
/**
****************************************************************************************
* @brief Bandwidth change function.
* This function is called during set channel procedure if the bandwidth configuration
* has changed
*
* @param[in] bw Bandwidth type
****************************************************************************************
*/
static void phy_change_bw(uint8_t bw)
{
switch(bw)
{
case PHY_CHNL_BW_20:
mdm_txstartdelay_setf(0x00000160);
mdm_tbectrl0_set(0x0C0F0700);
#if (NX_MDM_VER == 11)
mdm_tbectrl2_set(0x00F07005);
#endif
agc_rwnxagcaci20marg0_set(0);
agc_rwnxagcaci20marg1_set(0);
agc_rwnxagcaci20marg2_set(0);
break;
case PHY_CHNL_BW_40:
mdm_txstartdelay_setf(0x00000160);
mdm_tbectrl0_set(0x0C0F0702);
#if (NX_MDM_VER == 11)
mdm_tbectrl2_set(0x0FF07005);
#endif
agc_rwnxagcaci20marg0_set(AGC_RWNXAGCACI20MARG0_RESET);
agc_rwnxagcaci20marg1_set(AGC_RWNXAGCACI20MARG1_RESET);
agc_rwnxagcaci20marg2_set(AGC_RWNXAGCACI20MARG2_RESET);
break;
case PHY_CHNL_BW_80:
case PHY_CHNL_BW_160:
case PHY_CHNL_BW_80P80:
break;
default:
break;
}
force2040_toggle(bw);
}
void phy_init(const struct phy_cfg_tag *config)
{
const struct phy_trd_cfg_tag *cfg = (const struct phy_trd_cfg_tag *)&config->parameters;
//PHY ENVIRONMENT---------------------------------------------------------------------
//mapping mdm phy paths to rf phy paths
phy_env->phy2rf = cfg->path_mapping & (0x0F);
//Extract which RC and RF paths are used, MIMO or not
phy_get_config(cfg->path_mapping);
//Band = 2.4GHz by default
phy_env->band =
phy_env->chnl_prim20_freq =
phy_env->chnl_center1_freq =
phy_env->chnl_center2_freq =
phy_env->chnl_type = PHY_UNUSED;
PHY_WPRT("phy_init-->RC_PATHs=0x%X , RF_PATHS=0x%X\n", phy_env->rc_path_sel, phy_env->rf_path_sel);
//PHY blocks initialization-----------------------------------------------------------
//TRIDENT components
phy_trident_init();
//Radios alone through RC
phy_rf_init();
//MODEM - contains AGC?
phy_mdm_init(cfg->tx_dc_off_comp);
//AGC - separate or in MDM?
phy_agc_init();
}
void rcbeken_reconfigure(void)
{
UINT32 tmp;
phy_rcbeken_init();
rc_fe_rx_del_set(0x12c);
/*restore phy channel*/
#if (CFG_SOC_NAME == SOC_BK7231)
tmp = rc_trx_reg7_getf();
tmp = (tmp & 0xff01ffff) | ((phy_env->chnl_center1_freq - 2400) << 17);
rc_trx_reg7_set(tmp);
#else
tmp = rc_trx_reg5_getf();
tmp = (tmp & 0x01ffffff) | ((phy_env->chnl_center1_freq - 2400) << 25);
rc_trx_reg5_set(tmp);
#endif // (CFG_SOC_NAME == SOC_BK7231)
rc_ch0_rx_onoff_delay_pack( 1, 1);
rc_ch0_tx_onoff_delay_pack( 1, 1); //old on delay 0x41
rc_ch0_pa_onoff_delay_pack( 1, 0x10);//old on delay 0x41
rc_ch0_shdn_onoff_delay_pack(1, 1);
rc_ch0_en_setf(1);
rc_rc_en_setf(1);
}
#define RXVECT1_ARRAY_MAX 30
void phy_unsupported_modulation_check(void)
{
uint32_t rx_vect0;
uint32_t rx_vect1[RXVECT1_ARRAY_MAX];
uint32_t rx_vect2;
int8_t rx_rssi;
uint16_t rx_length, mcs;
int i;
rx_vect0 = mdm_rxvector0_get();
do
{
// Ensure that the packet could be a non-legacy one
if ((rx_vect0 & MDM_RXLEGRATE_MASK) != (11 << MDM_RXLEGRATE_LSB))
break;
// Read the RSSI, which is already available
rx_rssi = 0xFF00 | mdm_rssi1_getf();
if (rx_rssi < -40)
break;
// Poll on the RXFORMAT until it is equal to HT, or timeout otherwise
// This loop duration, if we timeout, shall be at least 4us
for (i=0; i<100; i++)
{
rx_vect2 = mdm_rxvector2_get();
if ((rx_vect2 & MDM_RXFORMAT_MASK) == 2)
break;
}
// Check if the received format is HT
if ((rx_vect2 & MDM_RXFORMAT_MASK) != 2)
break;
//os_printf("HT Format\r\n");
// Now read the RX vector 1 several times and store each value
// The duration between the first and the last read shall be around 6us
// This reads are done sequentially and not in a loop because the RX
// vector 1 is valid only for a few hundreds of ns and we don't want to
// suffer from the overhead of the looping
i = 0;
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get();
rx_vect1[i++] = mdm_rxvector1_get(); // Don't read beyond the array size you defined !!!
// Search in the RX vector 1 array the index of the latest non-null
// length value
for (i=(RXVECT1_ARRAY_MAX - 1); i>=0; i--)
{
if ((rx_vect1[i] & MDM_RXHTLENGTH_MASK) != 0)
break;
}
// If we did not find any non-null length, don't consider the packet
if (i == -1)
break;
//REG_WRITE( (0x0802800 +(17*4)), 0);
//os_printf("HT Format Length %d (i=%d) rssi=%d\r\n",rx_vect1[i] & MDM_RXHTLENGTH_MASK,i,rx_rssi);
// Check if the modulation is supported. We know that by checking if the
// index of the latest non-null length is the last one. Indeed in case
// the modulation is supported, the value of the rx vector 1 is kept valid
// until the end of the reception. Otherwise it is reset only a few hundreds
// of ns after becoming valid. Having a valid length in the latest RX vector 1
// read therefore means that the modulation is supported and the packet will
// be uploaded in the normal RX path
if (i == (RXVECT1_ARRAY_MAX - 1))
break;
// Unsupported modulation received
// TODO Forward the length and RSSI indication of this packet to the upper layers
rx_length = rx_vect1[i] & MDM_RXHTLENGTH_MASK;
mcs = ((rx_vect1[i] & MDM_RXMCS_MASK) >> MDM_RXMCS_LSB);
//if((mcs < 8) || (mcs > 15))
{
//break;
}
#if 1
os_printf("Length %d (%d-%d), rssi %d, mcs %d, idx %i\n",
rx_length,
rx_vect1[i-1] & MDM_RXHTLENGTH_MASK,
rx_vect1[i+1] & MDM_RXHTLENGTH_MASK,
rx_rssi,
mcs,
i);
#else
hal_monitor_sig_content(100 + rx_rssi, rx_length);
#endif
} while(0);
}
void phy_mdm_isr(void)
{
uint32_t irq_status = mdm_irqstat_get();
// Acknowledge the pending interrupts
mdm_irqack_set(irq_status);
if (irq_status & MDM_IRQLSIGVALIDEN_BIT)
{
phy_unsupported_modulation_check();
}
ASSERT_REC(!(irq_status & MDM_IRQCCATIMEOUT_BIT));
}
void phy_rc_isr(void)
{
}
void phy_get_version(uint32_t *version_1, uint32_t *version_2)
{
*version_1 = mdm_nxversion_get();
// TODO Add version reading for other PHY elements than modem.
*version_2 = 0;
}
static void set_trx_regs_extern(void)
{
UINT32 reg;
REG_WRITE((0x01050080+0x12*4), 0xD0640561);
reg = REG_READ((0x01050080+0x0d*4));
reg |= (0x4|0x2);
REG_WRITE((0x01050080+0x0d*4),reg);
reg = REG_READ((0x01050080+0x0e*4));
reg |= (0x4|0x2);
REG_WRITE((0x01050080+0x0e*4),reg);
reg = REG_READ((0x01050080+0x10*4));
reg |= (0x4|0x2);
REG_WRITE((0x01050080+0x10*4),reg);
reg = REG_READ((0x01050080+0x0f*4));
reg |= (0x4|0x2);
REG_WRITE((0x01050080+0x0f*4),reg);
while(REG_READ((0x01050000+0x1*4))&(0xFFFFFFF));
}
void phy_set_channel(uint8_t band, uint8_t type, uint16_t prim20_freq,
uint16_t center1_freq, uint16_t center2_freq, uint8_t index)
{
/*todo 11ac: when 2 radio transceivers on one path, careful how many writes go to both,
and when the two need separate SPi commands*/
uint8_t psel = 0;
uint32_t tmp;
//if same channel is set just skip
if ((phy_env->band == band)
&& (phy_env->chnl_type == type)
&& (phy_env->chnl_prim20_freq == prim20_freq)
&& (phy_env->chnl_center1_freq == center1_freq)
&& (phy_env->chnl_center2_freq == center2_freq))
{
return;
}
PHY_WPRT("phy_set_channel-->center1:%d center2:%d\r\n", center1_freq, center2_freq);
//todo add check for band 5+type 80, 160 and 80+80
/* Every time a channel is changed, RC is disabled causing the entire PHY shut down.
* Once all settings are made, RC is enable and SW polls status of wake up and lock
* to know when ready to use
*/
//Disable RC to turn everything off
rc_rc_en_setf(0);
//todo poll shutdown status bits for radios of interest
if (phy_env->chnl_type != type)
{
phy_change_bw(type);
}
//keep currently set values
phy_env->band = band;
phy_env->chnl_type = type;
phy_env->chnl_prim20_freq = prim20_freq;
phy_env->chnl_center1_freq = center1_freq;
phy_env->chnl_center2_freq = center2_freq;
//BAND--------------------------------------------------------------------------------
//set band info where needed(RC, Radios, ...)
phy_set_band(band, center1_freq);
//TYPE--------------------------------------------------------------------------------
//todo what values for LPF in RF?Now it's at default
switch(type)
{
case PHY_CHNL_BW_20:
psel = 0;
break;
case PHY_CHNL_BW_40:
psel = (center1_freq + 10 - prim20_freq) / 20;
break;
case PHY_CHNL_BW_80:
psel = (prim20_freq - (center1_freq - 30)) / 20;
case PHY_CHNL_BW_160:
case PHY_CHNL_BW_80P80:
break;
}
//CHANNEL-----------------------------------------------------------------------------
//Set Channel for Beken TRX
#if (CFG_SOC_NAME == SOC_BK7231)
tmp = rc_trx_reg7_getf();
tmp = (tmp & 0xff01ffff) | ((center1_freq - 2400) << 17);
rc_trx_reg7_set(tmp);
#else
tmp = rc_trx_reg5_getf();
tmp = (tmp & 0x01ffffff) | ((center1_freq - 2400) << 25);
rc_trx_reg5_set(tmp);
#endif // (CFG_SOC_NAME == SOC_BK7231)
// Set the PSEL value in modem
mdm_psselect20_setf(psel & 0x01);
mdm_psselect40_setf((psel & 0x02) >> 1);
//Enable RC and thus trigger the configuration start
rc_rc_en_setf(1);
//Lock--------------------------------------------------------------------------------
if (!phy_locked())
{
//failure measures - reset, shut down...
}
rc_ch0_tx_onoff_delay_set(0x00010010);
rc_ch0_pa_onoff_delay_set(0x000A00E0);
if(type == PHY_CHNL_BW_40)
set_trx_regs_extern();
}
void phy_get_channel(struct phy_channel_info *info, uint8_t index)
{
// Map the band, channel type, primary channel index and center 1 index on info1
info->info1 = phy_env->band | (phy_env->chnl_type << 8) | (phy_env->chnl_prim20_freq << 16);
// Map center 2 index on info2
info->info2 = phy_env->chnl_center1_freq | (phy_env->chnl_center2_freq << 16);
}
void phy_stop(void)
{
//RC disable only - everything will be shut down
rc_rc_en_setf(0);
//todo stop modem and trident components too?
//todo anything else?
}
bool phy_has_radar_pulse(int rd_idx)
{
return (mdm_radfifoempty_getf() == 0);
}
bool phy_get_radar_pulse(int rd_idx, struct phy_radar_pulse *pulse)
{
// Check if FIFO is empty
if (mdm_radfifoempty_getf())
return (false);
// FIFO is not empty, get an element
pulse->pulse = REG_PL_RD(0x60C04000);
return (true);
}
void phy_agc_reset(void)
{
uint32_t mdm_reg;
mdm_reg = mdm_swreset_get();
mdm_reg |= MDM_MDMSWRESET_BIT;
mdm_swreset_set(mdm_reg);
delay(10);
mdm_reg = mdm_swreset_get();
mdm_reg &= ~MDM_MDMSWRESET_BIT;
mdm_swreset_set(mdm_reg);
}
bool phy_bfmee_supported(void)
{
return false;
}
bool phy_bfmer_supported(void)
{
return false;
}
bool phy_mu_mimo_rx_supported(void)
{
return false;
}
bool phy_mu_mimo_tx_supported(void)
{
return false;
}
#if RW_MUMIMO_RX_EN
void phy_set_group_id_info(uint32_t membership_addr, uint32_t userpos_addr)
{
}
#endif
uint8_t phy_get_nss(void)
{
return 0;
}
uint8_t phy_get_ntx(void)
{
return (0);
}
//cca ctrl
uint8_t phy_open_cca(void)
{
agc_rwnxagcccactrl_set((agc_rwnxagcccactrl_get() & ~0x00000fff) | 0x00000377);
}
uint8_t phy_close_cca(void)
{
agc_rwnxagcccactrl_set((agc_rwnxagcccactrl_get() & ~0x00000fff) & ~(0x00000377));
}
uint8_t phy_show_cca(void)
{
//os_printf("0x01002078:%x\r\n",agc_rwnxagcccactrl_get());
//os_printf("0x01002074:%x\r\n",agc_rwnxagccca1_get());
//os_printf("0x01002070:%x\r\n",agc_rwnxagccca0_get());
}
/**
* TX power = idx * 0.5 + TX_GAIN_MIN + PA_GAIN
*
* idx = 2 * (TX power - TX_GAIN_MIN - PA_GAIN)
*
* idx = TX power - 5;//tpc
*/
void phy_get_rf_gain_idx(int8_t *power, uint8_t *idx)
{
int8_t min, max, oft;
if (phy_env->band == PHY_BAND_2G4)
{
min = PHY_TRIDENT_MIN_PWR_24G;
#if PHY_TRIDENT_LIMIT_PWR > PHY_TRIDENT_MAX_PWR_24G
max = PHY_TRIDENT_MAX_PWR_24G;
#else
max = PHY_TRIDENT_LIMIT_PWR;
#endif
oft = (PHY_TRIDENT_TX_GAIN_MIN + PHY_TRIDENT_PA_GAIN_24G);
}
else
{
min = PHY_TRIDENT_MIN_PWR_5G;
#if PHY_TRIDENT_LIMIT_PWR > PHY_TRIDENT_MAX_PWR_24G
max = PHY_TRIDENT_MAX_PWR_5G;
#else
max = PHY_TRIDENT_LIMIT_PWR;
#endif
oft = (PHY_TRIDENT_TX_GAIN_MIN + PHY_TRIDENT_PA_GAIN_5G);
}
if (*power > max)
{
*power = max;
}
else if (*power < min)
{
*power = min;
}
#if CFG_SUPPORT_TPC_PA_MAP
*idx = (*power - 5);
#else
*idx = 2 * (*power - oft);
#endif
}
void phy_get_rf_gain_capab(int8_t *max, int8_t *min)
{
if (phy_env->band == PHY_BAND_2G4)
{
*max = PHY_TRIDENT_MAX_PWR_24G;
*min = PHY_TRIDENT_MIN_PWR_24G;
}
else
{
*max = PHY_TRIDENT_MAX_PWR_5G;
*min = PHY_TRIDENT_MIN_PWR_5G;
}
}
void rc_reset_patch(void)
{
if(rc_rc_en_getf() == 0)
{
os_printf("********* RC_BEKEN_RESET ***********!\r\n");
rcbeken_reconfigure();
phy_agc_reset();
}
}
void phy_init_after_wakeup(void)
{
uint16_t freq;
struct phy_cfg_tag cfg;
freq = phy_env->chnl_center1_freq;
phy_env->chnl_center1_freq = 0;
cfg.parameters[0] = 1;
cfg.parameters[1] = 0;
phy_init(&cfg);
phy_set_channel(PHY_BAND_2G4, PHY_CHNL_BW_20, freq, freq, 0, PHY_PRIM);
}
/// @}
Raw
phy_trident.h
/**
****************************************************************************************
*
* @file phy_trident.h
*
* @brief File containing the nX Trident Radio register access functions and defines.
*
* Copyright (C) RivieraWaves 2011-2016
*
****************************************************************************************
*/
#ifndef PHY_TRIDENT_H_
#define PHY_TRIDENT_H_
#define PHY_DEBUG
#ifdef PHY_DEBUG
#define PHY_PRT os_printf
#define PHY_WPRT os_null_printf
#else
#define PHY_PRT os_null_printf
#define PHY_WPRT os_null_printf
#endif
/**
****************************************************************************************
* @addtogroup PHY
* @brief This driver is specific to the TRIDENT radio board based PHY. A very light
* control on MODEM, AGC, RF (through RC) and TRIDENT board components is grouped into
* specific block control functions in this driver. Its content remains transparent to SW
* in order for other drivers to be usable with the same SW. The PHY driver represents the
* link between SW and PHY.
*
* !!! Trident related settings use A,B, C radio paths.
* !!! MDM and RC related settings use paths 0,1,2
* One register will have the mapping between the two.
*
* The MAXIM2829 Radio(s) are controlled through the Radio Controller.
* @{
****************************************************************************************
*/
/*
* INCLUDE FILES
****************************************************************************************
*/
//for __INLINE
#include "compiler.h"
#include "mac.h"
/*
* DEFINES
****************************************************************************************
*/
#if CFG_SUPPORT_TPC_PA_MAP
// Limit as defined per radio specifications
#define PHY_TRIDENT_MAX_PWR_24G 20 // dBm
#define PHY_TRIDENT_MIN_PWR_24G 5 // dBm
#define PHY_TRIDENT_MAX_PWR_5G 22 // dBm
#define PHY_TRIDENT_MIN_PWR_5G -9 // dBm
#define PHY_TRIDENT_PA_GAIN_24G 0 // dBm
#define PHY_TRIDENT_PA_GAIN_5G 26 // dBm
#define PHY_TRIDENT_TX_GAIN_MIN -35 // dBm
// To prevent distortion Limit pwr to 10 dBm
#define PHY_TRIDENT_LIMIT_PWR 25 // dBm
#else
// Limit as defined per radio specifications
#define PHY_TRIDENT_MAX_PWR_24G 25 // dBm
#define PHY_TRIDENT_MIN_PWR_24G -6 // dBm
#define PHY_TRIDENT_MAX_PWR_5G 22 // dBm
#define PHY_TRIDENT_MIN_PWR_5G -9 // dBm
#define PHY_TRIDENT_PA_GAIN_24G 29 // dBm
#define PHY_TRIDENT_PA_GAIN_5G 26 // dBm
#define PHY_TRIDENT_TX_GAIN_MIN -35 // dBm
// To prevent distortion Limit pwr to 10 dBm
#define PHY_TRIDENT_LIMIT_PWR 10 // dBm
#endif
///MAXIM radio SPI prescaler
#define RF_SPI_PRESCALER 2//for until debug over
///Bit offset for generic enables for Radio path A
#define RF_PATH_A 0
///Bit offset for generic enables for Radio path B
#define RF_PATH_B 1
///Bit offset for generic enables for Radio path C
#define RF_PATH_C 2
///Bit offset for generic enables for MDM+RC path 0
#define RC_PATH_0 0
///Bit offset for generic enables for MDM+RC path 1
#define RC_PATH_1 1
///Bit offset for generic enables for MDM+RC path 2
#define RC_PATH_2 2
//Upper nibble of PHY_CFG parameter of phy_init
#define MDM_TYPE_1x1 0x00
#define MDM_TYPE_1x2 0x10
#define MDM_TYPE_1x3 0x20
#define MDM_TYPE_2x3 0x30
#define MDM_TYPE_3x3 0x40
//Lower nibble of PHY_CFG parameter of phy_init
#define MDM2RF_ABC 0x00
#define MDM2RF_BCA 0x01
#define MDM2RF_CAB 0x02
#define MDM2RF_ACB 0x03
#define MDM2RF_BAC 0x04
#define MDM2RF_CBA 0x05
/*
* CHANNEL SYNTHESIZER SETTINGS FOR RF REGISTERS
****************************************************************************************
*/
/// PHY driver context.
struct phy_env_tag
{
///Exact mapping of (MDM+RC) to Radio paths
uint8_t phy2rf;
///Rf selection: b0=A, b1=B, b2=C
uint8_t rf_path_sel;
///MDM+RC Path selection: b0=0, b1=1, b2=2
uint8_t rc_path_sel;
///MIMO enable
uint8_t mimo_en;
///Number of Rx Paths (for modem setting)
uint8_t nb_rx_paths;
///Current selected band
uint8_t band;
//20/40/80/160/80+80 channel type
uint8_t chnl_type;
///Currently configured 20MHz primary frequency (in MHz)
uint16_t chnl_prim20_freq;
///Currently configured nMHz contiguous channel (of primary 80 if 80+80)
uint16_t chnl_center1_freq;
///Currently configured secondary 80MHz channel if 80+80, unused otherwise
uint16_t chnl_center2_freq;
};
/// Global PHY driver environment.
extern struct phy_env_tag phy_env[];
/*
* FUNCTION DECLARATIONS
****************************************************************************************
*/
void phy_rc_rf_reg_write(uint8_t addr, uint16_t value);
/*
* MAXIM 2829 REGISTER ACCESS
****************************************************************************************
*/
#define RF_DONT_CARE 0
#define RF_DEFAULT0 0
#define RF_DEFAULT1 1
#define RF_FIXED0 0
#define RF_FIXED1 1
#define RF_VCO_SPI_BANDSW_DIS 0
#define RF_VCO_BANDSW_DIS 0
#define RF_VCO_BANDSW_EN 1
#define RF_5G_LOW 0
#define RF_5G_HIGH 1
//parameters are in lowest to highest bit positions order
// STANDBY-------------------------------------------------------------------------------
#define RF_STANDBY_ADDR 0x02
#define RF_STANDBY_RST 0x1007
#define RF_STANDBY_FIXED 0x1007
__INLINE void rf_standby_set(uint8_t pa_bias, uint8_t v_ref, uint8_t mimo_sel)
{
phy_rc_rf_reg_write(RF_STANDBY_ADDR,
RF_STANDBY_FIXED | (pa_bias << 10) | (v_ref << 11) | (mimo_sel << 13));
}
// INTEGER DIVIDER RATIO------------------------------------------------------------------
//no fields to define - values in table contain mandatory 0 set fields
#define RF_INTDIV_ADDR 0x03
#define RF_INTDIV_RST 0x30A2
__INLINE void rf_intdiv_set(uint16_t value)
{
phy_rc_rf_reg_write(RF_INTDIV_ADDR, value);
}
// FRACTIONAL DIVIDER RATIO---------------------------------------------------------------
//no fields to define - LSBs of value in RF are intdiv register MSBs !
#define RF_FRACDIV_ADDR 0x04
#define RF_FRACDIV_RST 0x1DDD
__INLINE void rf_fracdiv_set(uint16_t value)
{
phy_rc_rf_reg_write(RF_FRACDIV_ADDR, value);
}
// BAND SELECT----------------------------------------------------------------------------
//register used only in 2.4GHz band and never enable band switching, in 5GHz RC_SHADOW programs it
#define RF_BANDSEL_ADDR 0x05
#define RF_BANDSEL_RST 0x1824
#define RF_BANDSEL_FIXED 0x1800
__INLINE void rf_bandsel_set(uint8_t band, uint8_t ref_div, uint8_t mimo)
{
phy_rc_rf_reg_write(RF_BANDSEL_ADDR,
RF_BANDSEL_FIXED | (band) | (ref_div << 1) | (RF_DEFAULT1 << 5) |
(RF_DONT_CARE << 6) | (RF_VCO_BANDSW_DIS << 7) | (RF_VCO_SPI_BANDSW_DIS << 8) |
(RF_DONT_CARE << 9) | (mimo << 13));
}
// CALIBRATION---------------------------------------------------------------------------
#define RF_CALIB_ADDR 0x06
#define RF_CALIB_RST 0x1C00
#define RF_CALIB_FIXED 0x0400
__INLINE void rf_calib_set(uint8_t rxcal_en, uint8_t txcal_en, uint8_t txcal_cntl)
{
phy_rc_rf_reg_write(RF_CALIB_ADDR,
RF_CALIB_FIXED | (rxcal_en) | (txcal_en << 1) | (txcal_cntl << 11));
}
// LOW PASS FILTER------------------------------------------------------------------------
#define RF_LPF_ADDR 0x07
#define RF_LPF_RST 0x002A
#define RF_LPF_FIXED 0x0000
__INLINE void rf_lpf_set(uint8_t rx_cf_fine, uint8_t rx_cf_crs, uint8_t tx_cf_crs, uint8_t rssi_hbw_en)
{
phy_rc_rf_reg_write(RF_LPF_ADDR,
RF_LPF_FIXED | (rx_cf_fine) | (rx_cf_crs << 3) |
(tx_cf_crs << 5) | (rssi_hbw_en << 11));
}
// RX CONTROL/RSSI------------------------------------------------------------------------
#define RF_RXRSSI_ADDR 0x08
#define RF_RXRSSIF_RST 0x0025
#define RF_RXRSSIF_FIXED 0x0021
__INLINE void rf_rxrssi_set(uint8_t rx_cf, uint8_t temp_out_en, uint8_t rssi_mode, uint8_t rssi_range, uint8_t rx_vga_gain_prog_en)
{
phy_rc_rf_reg_write(RF_RXRSSI_ADDR,
RF_RXRSSIF_FIXED | (rx_cf << 2) | (temp_out_en << 8) |
(rssi_mode << 10) | (rssi_range << 11) | (rx_vga_gain_prog_en << 12));
}
// TXLINEARITY/BB GAIN--------------------------------------------------------------------
#define RF_TXLIN_ADDR 0x09
#define RF_TXLIN_RST 0x0200
#define RF_TXLIN_FIXED 0x0000
__INLINE void rf_txlin_set(uint8_t bb_gain, uint8_t upconv_lin, uint8_t vga_lin, uint8_t pa_lin, uint8_t tx_vga_gain_prog_en)
{
phy_rc_rf_reg_write(RF_TXLIN_ADDR,
RF_TXLIN_FIXED | (bb_gain) | (upconv_lin << 2) |
(vga_lin << 6) | (pa_lin << 8) | (tx_vga_gain_prog_en << 10));
}
// PA BIAS DAC----------------------------------------------------------------------------
#define RF_PABIAS_ADDR 0x0A
#define RF_PABIAS_RST 0x03C0
#define RF_PABIAS_FIXED 0x0000
__INLINE void rf_pabias_set(uint8_t dac_o_cur, uint8_t dac_on_del)
{
phy_rc_rf_reg_write(RF_PABIAS_ADDR, RF_PABIAS_FIXED | (dac_o_cur) | (dac_on_del << 6));
}
// RX GAIN--------------------------------------------------------------------------------
#define RF_RXGAIN_ADDR 0x0B
#define RF_RXGAIN_RST 0x007F
#define RF_RXGAIN_FIXED 0x0000
//todo check if two params or just one
__INLINE void rf_rxgain_set(uint8_t value)
{
phy_rc_rf_reg_write(RF_RXGAIN_ADDR, RF_RXGAIN_FIXED | value);
}
// TX VGA GAIN----------------------------------------------------------------------------
#define RF_TXGAIN_ADDR 0x0C
#define RF_TXGAIN_RST 0x0000
#define RF_TXGAIN_FIXED 0x0000
__INLINE void rf_txgain_set(uint8_t value)
{
phy_rc_rf_reg_write(RF_TXGAIN_ADDR, RF_TXGAIN_FIXED | value);
}
/**
****************************************************************************************
* @brief Simple check for set bits in a value
* @param[in] value A one byte value in which a certain bit will be checked for its state.
* @param[in] bit_pos Index of the bit to check, possible values from 0 to 7
* @return True is the bit at the indicated position is set, False otherwise.
****************************************************************************************
*/
__INLINE bool phy_is_bit_set(uint8_t value, uint8_t bit_pos)
{
if ((value & (1 << bit_pos)) == (1 << bit_pos))
return true;
return false;
}
/**
****************************************************************************************
* @brief Extraction of rf_sel and MIMO information out of MODEM type and MDM2RF path map
* @param[in] cfg Combined info with MDM2RF path mapping in lower nibble and Modem nxm type
* in upper nibble.
****************************************************************************************
*/
__INLINE void phy_get_config(uint8_t cfg)
{
uint8_t mdm_type = cfg & 0xF0;
switch(mdm_type)
{
case MDM_TYPE_1x1:
{
phy_env->mimo_en = 0;
phy_env->nb_rx_paths = 1;
phy_env->rc_path_sel = (1 << RC_PATH_0);
}
break;
case MDM_TYPE_1x2:
{
phy_env->mimo_en = 1;
phy_env->nb_rx_paths = 2;
phy_env->rc_path_sel = (1 << RC_PATH_0) | (1 << RC_PATH_1);
}
break;
default:
{
phy_env->mimo_en = 1;
phy_env->nb_rx_paths = 3;
phy_env->rc_path_sel = (1 << RC_PATH_0) | (1 << RC_PATH_1) | (1 << RC_PATH_2);
}
break;
}
switch(cfg & 0x0F)
{
//PHY 0,1,2 to RF A, B, C
case MDM2RF_ABC:
//get how many channels will be used rx+tx
// 1x1 - A alone
if (mdm_type == MDM_TYPE_1x1)
{
phy_env->rf_path_sel = (1 << RF_PATH_A);
}
// 1x2 - A&B
else if (mdm_type == MDM_TYPE_1x2)
{
phy_env->rf_path_sel = (1 << RF_PATH_A) | (1 << RF_PATH_B);
}
// 1x3, 2x3, 3x3 - all 3...
else
{
phy_env->rf_path_sel = (1 << RF_PATH_A) | (1 << RF_PATH_B) | (1 << RF_PATH_C);
}
break;
//PHY 0,1,2 to RF B, C, A
case MDM2RF_BCA:
//get how many channels will be used rx+tx
// 1x1 - B alone
if (mdm_type == MDM_TYPE_1x1)
{
phy_env->rf_path_sel = (1 << RF_PATH_B);
}
// 1x2 - B&C
else if (mdm_type == MDM_TYPE_1x2)
{
phy_env->rf_path_sel = (1 << RF_PATH_B) | (1 << RF_PATH_C);
}
// 1x3, 2x3, 3x3 - all 3...
else
{
phy_env->rf_path_sel = (1 << RF_PATH_A) | (1 << RF_PATH_B) | (1 << RF_PATH_C);
}
break;
//PHY 0,1,2 to RF C, A, B
case MDM2RF_CAB:
//get how many channels will be used rx+tx
// 1x1 - C alone
if (mdm_type == MDM_TYPE_1x1)
{
phy_env->rf_path_sel = (1 << RF_PATH_C);
}
// 1x2 - C&A
else if (mdm_type == MDM_TYPE_1x2)
{
phy_env->rf_path_sel = (1 << RF_PATH_C) | (1 << RF_PATH_A);
}
// 1x3, 2x3, 3x3 - all 3...
else
{
phy_env->rf_path_sel = (1 << RF_PATH_A) | (1 << RF_PATH_B) | (1 << RF_PATH_C);
}
break;
//PHY 0,1,2 to RF A, C, B
case MDM2RF_ACB:
//get how many channels will be used rx+tx
// 1x1 - A alone
if (mdm_type == MDM_TYPE_1x1)
{
phy_env->rf_path_sel = (1 << RF_PATH_A);
}
// 1x2 - A&C
else if (mdm_type == MDM_TYPE_1x2)
{
phy_env->rf_path_sel = (1 << RF_PATH_A) | (1 << RF_PATH_C);
}
// 1x3, 2x3, 3x3 - all 3...
else
{
phy_env->rf_path_sel = (1 << RF_PATH_A) | (1 << RF_PATH_B) | (1 << RF_PATH_C);
}
break;
//PHY 0,1,2 to RF B, A, C
case MDM2RF_BAC:
//get how many channels will be used rx+tx
// 1x1 - B alone
if (mdm_type == MDM_TYPE_1x1)
{
phy_env->rf_path_sel = (1 << RF_PATH_B);
}
// 1x2 - B&A
else if (mdm_type == MDM_TYPE_1x2)
{
phy_env->rf_path_sel = (1 << RF_PATH_B) | (1 << RF_PATH_A);
}
// 1x3, 2x3, 3x3 - all 3...
else
{
phy_env->rf_path_sel = (1 << RF_PATH_A) | (1 << RF_PATH_B) | (1 << RF_PATH_C);
}
break;
//PHY 0,1,2 to RF C, B, A
case MDM2RF_CBA:
//get how many channels will be used rx+tx
// 1x1 - C alone
if (mdm_type == MDM_TYPE_1x1)
{
phy_env->rf_path_sel = (1 << RF_PATH_B);
}
// 1x2 - C&B
else if (mdm_type == MDM_TYPE_1x2)
{
phy_env->rf_path_sel = (1 << RF_PATH_C) | (1 << RF_PATH_B);
}
// 1x3, 2x3, 3x3 - all 3...
else
{
phy_env->rf_path_sel = (1 << RF_PATH_A) | (1 << RF_PATH_B) | (1 << RF_PATH_C);
}
break;
default:
break;
}
}
extern void phy_init_after_wakeup(void);
extern void phy_disable_lsig_intr(void);
extern void phy_enable_lsig_intr(void);
/// @}
#endif /* PHY_TRIDENT_H_ */
Raw
reg_access.h
/**
****************************************************************************************
*
* @file reg_access.h
*
* @brief File implementing the basic primitives for register accesses
*
* Copyright (C) RivieraWaves 2011-2016
*
****************************************************************************************
*/
#ifndef REG_ACCESS_H_
#define REG_ACCESS_H_
/**
****************************************************************************************
* @defgroup REG REG
* @ingroup PLATFORM_DRIVERS
*
* @brief Basic primitives for register access.
*
* @{
****************************************************************************************
*/
/*
* MACROS
****************************************************************************************
*/
/// Macro to read a platform register
#define REG_PL_RD(addr) (*(volatile uint32_t *)(addr))
/// Macro to write a platform register
#define REG_PL_WR(addr, value) (*(volatile uint32_t *)(addr)) = (value)
/// @} REG
#endif // REG_ACCESS_H_
Raw
reg_agc.h
/**
* @file reg_agc.h
* @brief Definitions of the AGC HW block registers and register access functions.
*
* @defgroup REG_AGC REG_AGC
* @ingroup REG
* @{
*
* @brief Definitions of the AGC HW block registers and register access functions.
*/
#ifndef _REG_AGC_H_
#define _REG_AGC_H_
#include "co_int.h"
#include "_reg_agc.h"
#include "compiler.h"
#include "arch.h"
#include "reg_access.h"
/** @brief Number of registers in the REG_AGC peripheral.
*/
#define REG_AGC_COUNT 2091
/** @brief Decoding mask of the REG_AGC peripheral registers from the CPU point of view.
*/
#define REG_AGC_DECODING_MASK 0x00003FFF
/**
* @name RWNXAGCGAINRG register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:28 RFLOSSANT3DB 0x0
* 27:24 RFLOSSANT2DB 0x0
* 23:20 RFLOSSANT1DB 0x0
* 19:16 RFLOSSANT0DB 0x0
* 14:08 RFGAINMAXDB 0x64
* 06:00 RFGAINMINDB 0x0
* </pre>
*
* @{
*/
/// Address of the RWNXAGCGAINRG register
#define AGC_RWNXAGCGAINRG_ADDR 0x01002000
/// Offset of the RWNXAGCGAINRG register from the base address
#define AGC_RWNXAGCGAINRG_OFFSET 0x00002000
/// Index of the RWNXAGCGAINRG register
#define AGC_RWNXAGCGAINRG_INDEX 0x00000800
/// Reset value of the RWNXAGCGAINRG register
#define AGC_RWNXAGCGAINRG_RESET 0x00006400
/**
* @brief Returns the current value of the RWNXAGCGAINRG register.
* The RWNXAGCGAINRG register will be read and its value returned.
* @return The current value of the RWNXAGCGAINRG register.
*/
__INLINE uint32_t agc_rwnxagcgainrg_get(void)
{
return REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR);
}
/**
* @brief Sets the RWNXAGCGAINRG register to a value.
* The RWNXAGCGAINRG register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcgainrg_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCGAINRG_ADDR, value);
}
// field definitions
/// RFLOSSANT3DB field mask
#define AGC_RFLOSSANT3DB_MASK ((uint32_t)0xF0000000)
/// RFLOSSANT3DB field LSB position
#define AGC_RFLOSSANT3DB_LSB 28
/// RFLOSSANT3DB field width
#define AGC_RFLOSSANT3DB_WIDTH ((uint32_t)0x00000004)
/// RFLOSSANT2DB field mask
#define AGC_RFLOSSANT2DB_MASK ((uint32_t)0x0F000000)
/// RFLOSSANT2DB field LSB position
#define AGC_RFLOSSANT2DB_LSB 24
/// RFLOSSANT2DB field width
#define AGC_RFLOSSANT2DB_WIDTH ((uint32_t)0x00000004)
/// RFLOSSANT1DB field mask
#define AGC_RFLOSSANT1DB_MASK ((uint32_t)0x00F00000)
/// RFLOSSANT1DB field LSB position
#define AGC_RFLOSSANT1DB_LSB 20
/// RFLOSSANT1DB field width
#define AGC_RFLOSSANT1DB_WIDTH ((uint32_t)0x00000004)
/// RFLOSSANT0DB field mask
#define AGC_RFLOSSANT0DB_MASK ((uint32_t)0x000F0000)
/// RFLOSSANT0DB field LSB position
#define AGC_RFLOSSANT0DB_LSB 16
/// RFLOSSANT0DB field width
#define AGC_RFLOSSANT0DB_WIDTH ((uint32_t)0x00000004)
/// RFGAINMAXDB field mask
#define AGC_RFGAINMAXDB_MASK ((uint32_t)0x00007F00)
/// RFGAINMAXDB field LSB position
#define AGC_RFGAINMAXDB_LSB 8
/// RFGAINMAXDB field width
#define AGC_RFGAINMAXDB_WIDTH ((uint32_t)0x00000007)
/// RFGAINMINDB field mask
#define AGC_RFGAINMINDB_MASK ((uint32_t)0x0000007F)
/// RFGAINMINDB field LSB position
#define AGC_RFGAINMINDB_LSB 0
/// RFGAINMINDB field width
#define AGC_RFGAINMINDB_WIDTH ((uint32_t)0x00000007)
/// RFLOSSANT3DB field reset value
#define AGC_RFLOSSANT3DB_RST 0x0
/// RFLOSSANT2DB field reset value
#define AGC_RFLOSSANT2DB_RST 0x0
/// RFLOSSANT1DB field reset value
#define AGC_RFLOSSANT1DB_RST 0x0
/// RFLOSSANT0DB field reset value
#define AGC_RFLOSSANT0DB_RST 0x0
/// RFGAINMAXDB field reset value
#define AGC_RFGAINMAXDB_RST 0x64
/// RFGAINMINDB field reset value
#define AGC_RFGAINMINDB_RST 0x0
/**
* @brief Constructs a value for the RWNXAGCGAINRG register given values for its fields
* and writes the value to the register.
*
* @param[in] rflossant3db - The value to use for the RFLOSSANT3DB field.
* @param[in] rflossant2db - The value to use for the RFLOSSANT2DB field.
* @param[in] rflossant1db - The value to use for the RFLOSSANT1DB field.
* @param[in] rflossant0db - The value to use for the RFLOSSANT0DB field.
* @param[in] rfgainmaxdb - The value to use for the RFGAINMAXDB field.
* @param[in] rfgainmindb - The value to use for the RFGAINMINDB field.
*/
__INLINE void agc_rwnxagcgainrg_pack(uint8_t rflossant3db, uint8_t rflossant2db, uint8_t rflossant1db, uint8_t rflossant0db, uint8_t rfgainmaxdb, uint8_t rfgainmindb)
{
ASSERT_ERR((((uint32_t)rflossant3db << 28) & ~((uint32_t)0xF0000000)) == 0);
ASSERT_ERR((((uint32_t)rflossant2db << 24) & ~((uint32_t)0x0F000000)) == 0);
ASSERT_ERR((((uint32_t)rflossant1db << 20) & ~((uint32_t)0x00F00000)) == 0);
ASSERT_ERR((((uint32_t)rflossant0db << 16) & ~((uint32_t)0x000F0000)) == 0);
ASSERT_ERR((((uint32_t)rfgainmaxdb << 8) & ~((uint32_t)0x00007F00)) == 0);
ASSERT_ERR((((uint32_t)rfgainmindb << 0) & ~((uint32_t)0x0000007F)) == 0);
REG_PL_WR(AGC_RWNXAGCGAINRG_ADDR, ((uint32_t)rflossant3db << 28) | ((uint32_t)rflossant2db << 24) | ((uint32_t)rflossant1db << 20) | ((uint32_t)rflossant0db << 16) | ((uint32_t)rfgainmaxdb << 8) | ((uint32_t)rfgainmindb << 0));
}
/**
* @brief Unpacks RWNXAGCGAINRG's fields from current value of the RWNXAGCGAINRG register.
*
* Reads the RWNXAGCGAINRG register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] rflossant3db - Will be populated with the current value of this field from the register.
* @param[out] rflossant2db - Will be populated with the current value of this field from the register.
* @param[out] rflossant1db - Will be populated with the current value of this field from the register.
* @param[out] rflossant0db - Will be populated with the current value of this field from the register.
* @param[out] rfgainmaxdb - Will be populated with the current value of this field from the register.
* @param[out] rfgainmindb - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcgainrg_unpack(uint8_t *rflossant3db, uint8_t *rflossant2db, uint8_t *rflossant1db, uint8_t *rflossant0db, uint8_t *rfgainmaxdb, uint8_t *rfgainmindb)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR);
*rflossant3db = (localVal & ((uint32_t)0xF0000000)) >> 28;
*rflossant2db = (localVal & ((uint32_t)0x0F000000)) >> 24;
*rflossant1db = (localVal & ((uint32_t)0x00F00000)) >> 20;
*rflossant0db = (localVal & ((uint32_t)0x000F0000)) >> 16;
*rfgainmaxdb = (localVal & ((uint32_t)0x00007F00)) >> 8;
*rfgainmindb = (localVal & ((uint32_t)0x0000007F)) >> 0;
}
/**
* @brief Returns the current value of the RFLOSSANT3DB field in the RWNXAGCGAINRG register.
*
* The RWNXAGCGAINRG register will be read and the RFLOSSANT3DB field's value will be returned.
*
* @return The current value of the RFLOSSANT3DB field in the RWNXAGCGAINRG register.
*/
__INLINE uint8_t agc_rflossant3db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR);
return ((localVal & ((uint32_t)0xF0000000)) >> 28);
}
/**
* @brief Sets the RFLOSSANT3DB field of the RWNXAGCGAINRG register.
*
* The RWNXAGCGAINRG register will be read, modified to contain the new field value, and written.
*
* @param[in] rflossant3db - The value to set the field to.
*/
__INLINE void agc_rflossant3db_setf(uint8_t rflossant3db)
{
ASSERT_ERR((((uint32_t)rflossant3db << 28) & ~((uint32_t)0xF0000000)) == 0);
REG_PL_WR(AGC_RWNXAGCGAINRG_ADDR, (REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR) & ~((uint32_t)0xF0000000)) | ((uint32_t)rflossant3db << 28));
}
/**
* @brief Returns the current value of the RFLOSSANT2DB field in the RWNXAGCGAINRG register.
*
* The RWNXAGCGAINRG register will be read and the RFLOSSANT2DB field's value will be returned.
*
* @return The current value of the RFLOSSANT2DB field in the RWNXAGCGAINRG register.
*/
__INLINE uint8_t agc_rflossant2db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR);
return ((localVal & ((uint32_t)0x0F000000)) >> 24);
}
/**
* @brief Sets the RFLOSSANT2DB field of the RWNXAGCGAINRG register.
*
* The RWNXAGCGAINRG register will be read, modified to contain the new field value, and written.
*
* @param[in] rflossant2db - The value to set the field to.
*/
__INLINE void agc_rflossant2db_setf(uint8_t rflossant2db)
{
ASSERT_ERR((((uint32_t)rflossant2db << 24) & ~((uint32_t)0x0F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCGAINRG_ADDR, (REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR) & ~((uint32_t)0x0F000000)) | ((uint32_t)rflossant2db << 24));
}
/**
* @brief Returns the current value of the RFLOSSANT1DB field in the RWNXAGCGAINRG register.
*
* The RWNXAGCGAINRG register will be read and the RFLOSSANT1DB field's value will be returned.
*
* @return The current value of the RFLOSSANT1DB field in the RWNXAGCGAINRG register.
*/
__INLINE uint8_t agc_rflossant1db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR);
return ((localVal & ((uint32_t)0x00F00000)) >> 20);
}
/**
* @brief Sets the RFLOSSANT1DB field of the RWNXAGCGAINRG register.
*
* The RWNXAGCGAINRG register will be read, modified to contain the new field value, and written.
*
* @param[in] rflossant1db - The value to set the field to.
*/
__INLINE void agc_rflossant1db_setf(uint8_t rflossant1db)
{
ASSERT_ERR((((uint32_t)rflossant1db << 20) & ~((uint32_t)0x00F00000)) == 0);
REG_PL_WR(AGC_RWNXAGCGAINRG_ADDR, (REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR) & ~((uint32_t)0x00F00000)) | ((uint32_t)rflossant1db << 20));
}
/**
* @brief Returns the current value of the RFLOSSANT0DB field in the RWNXAGCGAINRG register.
*
* The RWNXAGCGAINRG register will be read and the RFLOSSANT0DB field's value will be returned.
*
* @return The current value of the RFLOSSANT0DB field in the RWNXAGCGAINRG register.
*/
__INLINE uint8_t agc_rflossant0db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR);
return ((localVal & ((uint32_t)0x000F0000)) >> 16);
}
/**
* @brief Sets the RFLOSSANT0DB field of the RWNXAGCGAINRG register.
*
* The RWNXAGCGAINRG register will be read, modified to contain the new field value, and written.
*
* @param[in] rflossant0db - The value to set the field to.
*/
__INLINE void agc_rflossant0db_setf(uint8_t rflossant0db)
{
ASSERT_ERR((((uint32_t)rflossant0db << 16) & ~((uint32_t)0x000F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCGAINRG_ADDR, (REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR) & ~((uint32_t)0x000F0000)) | ((uint32_t)rflossant0db << 16));
}
/**
* @brief Returns the current value of the RFGAINMAXDB field in the RWNXAGCGAINRG register.
*
* The RWNXAGCGAINRG register will be read and the RFGAINMAXDB field's value will be returned.
*
* @return The current value of the RFGAINMAXDB field in the RWNXAGCGAINRG register.
*/
__INLINE uint8_t agc_rfgainmaxdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR);
return ((localVal & ((uint32_t)0x00007F00)) >> 8);
}
/**
* @brief Sets the RFGAINMAXDB field of the RWNXAGCGAINRG register.
*
* The RWNXAGCGAINRG register will be read, modified to contain the new field value, and written.
*
* @param[in] rfgainmaxdb - The value to set the field to.
*/
__INLINE void agc_rfgainmaxdb_setf(uint8_t rfgainmaxdb)
{
ASSERT_ERR((((uint32_t)rfgainmaxdb << 8) & ~((uint32_t)0x00007F00)) == 0);
REG_PL_WR(AGC_RWNXAGCGAINRG_ADDR, (REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR) & ~((uint32_t)0x00007F00)) | ((uint32_t)rfgainmaxdb << 8));
}
/**
* @brief Returns the current value of the RFGAINMINDB field in the RWNXAGCGAINRG register.
*
* The RWNXAGCGAINRG register will be read and the RFGAINMINDB field's value will be returned.
*
* @return The current value of the RFGAINMINDB field in the RWNXAGCGAINRG register.
*/
__INLINE uint8_t agc_rfgainmindb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR);
return ((localVal & ((uint32_t)0x0000007F)) >> 0);
}
/**
* @brief Sets the RFGAINMINDB field of the RWNXAGCGAINRG register.
*
* The RWNXAGCGAINRG register will be read, modified to contain the new field value, and written.
*
* @param[in] rfgainmindb - The value to set the field to.
*/
__INLINE void agc_rfgainmindb_setf(uint8_t rfgainmindb)
{
ASSERT_ERR((((uint32_t)rfgainmindb << 0) & ~((uint32_t)0x0000007F)) == 0);
REG_PL_WR(AGC_RWNXAGCGAINRG_ADDR, (REG_PL_RD(AGC_RWNXAGCGAINRG_ADDR) & ~((uint32_t)0x0000007F)) | ((uint32_t)rfgainmindb << 0));
}
/// @}
/**
* @name RWNXAGCLNAVGAREF0 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 30:28 VGASTEPDB 0x2
* 27:24 VGAMINDB 0x0
* 21:16 LNAHDB 0x1E
* 13:08 LMAMDB 0xF
* 06:00 LNALDB 0x0
* </pre>
*
* @{
*/
/// Address of the RWNXAGCLNAVGAREF0 register
#define AGC_RWNXAGCLNAVGAREF0_ADDR 0x01002004
/// Offset of the RWNXAGCLNAVGAREF0 register from the base address
#define AGC_RWNXAGCLNAVGAREF0_OFFSET 0x00002004
/// Index of the RWNXAGCLNAVGAREF0 register
#define AGC_RWNXAGCLNAVGAREF0_INDEX 0x00000801
/// Reset value of the RWNXAGCLNAVGAREF0 register
#define AGC_RWNXAGCLNAVGAREF0_RESET 0x201E0F00
/**
* @brief Returns the current value of the RWNXAGCLNAVGAREF0 register.
* The RWNXAGCLNAVGAREF0 register will be read and its value returned.
* @return The current value of the RWNXAGCLNAVGAREF0 register.
*/
__INLINE uint32_t agc_rwnxagclnavgaref0_get(void)
{
return REG_PL_RD(AGC_RWNXAGCLNAVGAREF0_ADDR);
}
/**
* @brief Sets the RWNXAGCLNAVGAREF0 register to a value.
* The RWNXAGCLNAVGAREF0 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagclnavgaref0_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCLNAVGAREF0_ADDR, value);
}
// field definitions
/// VGASTEPDB field mask
#define AGC_VGASTEPDB_MASK ((uint32_t)0x70000000)
/// VGASTEPDB field LSB position
#define AGC_VGASTEPDB_LSB 28
/// VGASTEPDB field width
#define AGC_VGASTEPDB_WIDTH ((uint32_t)0x00000003)
/// VGAMINDB field mask
#define AGC_VGAMINDB_MASK ((uint32_t)0x0F000000)
/// VGAMINDB field LSB position
#define AGC_VGAMINDB_LSB 24
/// VGAMINDB field width
#define AGC_VGAMINDB_WIDTH ((uint32_t)0x00000004)
/// LNAHDB field mask
#define AGC_LNAHDB_MASK ((uint32_t)0x003F0000)
/// LNAHDB field LSB position
#define AGC_LNAHDB_LSB 16
/// LNAHDB field width
#define AGC_LNAHDB_WIDTH ((uint32_t)0x00000006)
/// LMAMDB field mask
#define AGC_LMAMDB_MASK ((uint32_t)0x00003F00)
/// LMAMDB field LSB position
#define AGC_LMAMDB_LSB 8
/// LMAMDB field width
#define AGC_LMAMDB_WIDTH ((uint32_t)0x00000006)
/// LNALDB field mask
#define AGC_LNALDB_MASK ((uint32_t)0x0000007F)
/// LNALDB field LSB position
#define AGC_LNALDB_LSB 0
/// LNALDB field width
#define AGC_LNALDB_WIDTH ((uint32_t)0x00000007)
/// VGASTEPDB field reset value
#define AGC_VGASTEPDB_RST 0x2
/// VGAMINDB field reset value
#define AGC_VGAMINDB_RST 0x0
/// LNAHDB field reset value
#define AGC_LNAHDB_RST 0x1E
/// LMAMDB field reset value
#define AGC_LMAMDB_RST 0xF
/// LNALDB field reset value
#define AGC_LNALDB_RST 0x0
/**
* @brief Constructs a value for the RWNXAGCLNAVGAREF0 register given values for its fields
* and writes the value to the register.
*
* @param[in] vgastepdb - The value to use for the VGASTEPDB field.
* @param[in] vgamindb - The value to use for the VGAMINDB field.
* @param[in] lnahdb - The value to use for the LNAHDB field.
* @param[in] lmamdb - The value to use for the LMAMDB field.
* @param[in] lnaldb - The value to use for the LNALDB field.
*/
__INLINE void agc_rwnxagclnavgaref0_pack(uint8_t vgastepdb, uint8_t vgamindb, uint8_t lnahdb, uint8_t lmamdb, uint8_t lnaldb)
{
ASSERT_ERR((((uint32_t)vgastepdb << 28) & ~((uint32_t)0x70000000)) == 0);
ASSERT_ERR((((uint32_t)vgamindb << 24) & ~((uint32_t)0x0F000000)) == 0);
ASSERT_ERR((((uint32_t)lnahdb << 16) & ~((uint32_t)0x003F0000)) == 0);
ASSERT_ERR((((uint32_t)lmamdb << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)lnaldb << 0) & ~((uint32_t)0x0000007F)) == 0);
REG_PL_WR(AGC_RWNXAGCLNAVGAREF0_ADDR, ((uint32_t)vgastepdb << 28) | ((uint32_t)vgamindb << 24) | ((uint32_t)lnahdb << 16) | ((uint32_t)lmamdb << 8) | ((uint32_t)lnaldb << 0));
}
/**
* @brief Unpacks RWNXAGCLNAVGAREF0's fields from current value of the RWNXAGCLNAVGAREF0 register.
*
* Reads the RWNXAGCLNAVGAREF0 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] vgastepdb - Will be populated with the current value of this field from the register.
* @param[out] vgamindb - Will be populated with the current value of this field from the register.
* @param[out] lnahdb - Will be populated with the current value of this field from the register.
* @param[out] lmamdb - Will be populated with the current value of this field from the register.
* @param[out] lnaldb - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagclnavgaref0_unpack(uint8_t *vgastepdb, uint8_t *vgamindb, uint8_t *lnahdb, uint8_t *lmamdb, uint8_t *lnaldb)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCLNAVGAREF0_ADDR);
*vgastepdb = (localVal & ((uint32_t)0x70000000)) >> 28;
*vgamindb = (localVal & ((uint32_t)0x0F000000)) >> 24;
*lnahdb = (localVal & ((uint32_t)0x003F0000)) >> 16;
*lmamdb = (localVal & ((uint32_t)0x00003F00)) >> 8;
*lnaldb = (localVal & ((uint32_t)0x0000007F)) >> 0;
}
/**
* @brief Returns the current value of the VGASTEPDB field in the RWNXAGCLNAVGAREF0 register.
*
* The RWNXAGCLNAVGAREF0 register will be read and the VGASTEPDB field's value will be returned.
*
* @return The current value of the VGASTEPDB field in the RWNXAGCLNAVGAREF0 register.
*/
__INLINE uint8_t agc_vgastepdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCLNAVGAREF0_ADDR);
return ((localVal & ((uint32_t)0x70000000)) >> 28);
}
/**
* @brief Sets the VGASTEPDB field of the RWNXAGCLNAVGAREF0 register.
*
* The RWNXAGCLNAVGAREF0 register will be read, modified to contain the new field value, and written.
*
* @param[in] vgastepdb - The value to set the field to.
*/
__INLINE void agc_vgastepdb_setf(uint8_t vgastepdb)
{
ASSERT_ERR((((uint32_t)vgastepdb << 28) & ~((uint32_t)0x70000000)) == 0);
REG_PL_WR(AGC_RWNXAGCLNAVGAREF0_ADDR, (REG_PL_RD(AGC_RWNXAGCLNAVGAREF0_ADDR) & ~((uint32_t)0x70000000)) | ((uint32_t)vgastepdb << 28));
}
/**
* @brief Returns the current value of the VGAMINDB field in the RWNXAGCLNAVGAREF0 register.
*
* The RWNXAGCLNAVGAREF0 register will be read and the VGAMINDB field's value will be returned.
*
* @return The current value of the VGAMINDB field in the RWNXAGCLNAVGAREF0 register.
*/
__INLINE uint8_t agc_vgamindb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCLNAVGAREF0_ADDR);
return ((localVal & ((uint32_t)0x0F000000)) >> 24);
}
/**
* @brief Sets the VGAMINDB field of the RWNXAGCLNAVGAREF0 register.
*
* The RWNXAGCLNAVGAREF0 register will be read, modified to contain the new field value, and written.
*
* @param[in] vgamindb - The value to set the field to.
*/
__INLINE void agc_vgamindb_setf(uint8_t vgamindb)
{
ASSERT_ERR((((uint32_t)vgamindb << 24) & ~((uint32_t)0x0F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCLNAVGAREF0_ADDR, (REG_PL_RD(AGC_RWNXAGCLNAVGAREF0_ADDR) & ~((uint32_t)0x0F000000)) | ((uint32_t)vgamindb << 24));
}
/**
* @brief Returns the current value of the LNAHDB field in the RWNXAGCLNAVGAREF0 register.
*
* The RWNXAGCLNAVGAREF0 register will be read and the LNAHDB field's value will be returned.
*
* @return The current value of the LNAHDB field in the RWNXAGCLNAVGAREF0 register.
*/
__INLINE uint8_t agc_lnahdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCLNAVGAREF0_ADDR);
return ((localVal & ((uint32_t)0x003F0000)) >> 16);
}
/**
* @brief Sets the LNAHDB field of the RWNXAGCLNAVGAREF0 register.
*
* The RWNXAGCLNAVGAREF0 register will be read, modified to contain the new field value, and written.
*
* @param[in] lnahdb - The value to set the field to.
*/
__INLINE void agc_lnahdb_setf(uint8_t lnahdb)
{
ASSERT_ERR((((uint32_t)lnahdb << 16) & ~((uint32_t)0x003F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCLNAVGAREF0_ADDR, (REG_PL_RD(AGC_RWNXAGCLNAVGAREF0_ADDR) & ~((uint32_t)0x003F0000)) | ((uint32_t)lnahdb << 16));
}
/**
* @brief Returns the current value of the LMAMDB field in the RWNXAGCLNAVGAREF0 register.
*
* The RWNXAGCLNAVGAREF0 register will be read and the LMAMDB field's value will be returned.
*
* @return The current value of the LMAMDB field in the RWNXAGCLNAVGAREF0 register.
*/
__INLINE uint8_t agc_lmamdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCLNAVGAREF0_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the LMAMDB field of the RWNXAGCLNAVGAREF0 register.
*
* The RWNXAGCLNAVGAREF0 register will be read, modified to contain the new field value, and written.
*
* @param[in] lmamdb - The value to set the field to.
*/
__INLINE void agc_lmamdb_setf(uint8_t lmamdb)
{
ASSERT_ERR((((uint32_t)lmamdb << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCLNAVGAREF0_ADDR, (REG_PL_RD(AGC_RWNXAGCLNAVGAREF0_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)lmamdb << 8));
}
/**
* @brief Returns the current value of the LNALDB field in the RWNXAGCLNAVGAREF0 register.
*
* The RWNXAGCLNAVGAREF0 register will be read and the LNALDB field's value will be returned.
*
* @return The current value of the LNALDB field in the RWNXAGCLNAVGAREF0 register.
*/
__INLINE uint8_t agc_lnaldb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCLNAVGAREF0_ADDR);
return ((localVal & ((uint32_t)0x0000007F)) >> 0);
}
/**
* @brief Sets the LNALDB field of the RWNXAGCLNAVGAREF0 register.
*
* The RWNXAGCLNAVGAREF0 register will be read, modified to contain the new field value, and written.
*
* @param[in] lnaldb - The value to set the field to.
*/
__INLINE void agc_lnaldb_setf(uint8_t lnaldb)
{
ASSERT_ERR((((uint32_t)lnaldb << 0) & ~((uint32_t)0x0000007F)) == 0);
REG_PL_WR(AGC_RWNXAGCLNAVGAREF0_ADDR, (REG_PL_RD(AGC_RWNXAGCLNAVGAREF0_ADDR) & ~((uint32_t)0x0000007F)) | ((uint32_t)lnaldb << 0));
}
/// @}
/**
* @name RWNXAGCLNAVGAREF1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:28 DIGGAIN80VS20 0x0
* 27:24 DIGGAIN40VS20 0x0
* 20:16 VGAINDMAX 0x1F
* 13:08 LNAHMTHRDB 0x1E
* 05:00 LNAMLTHRDB 0xF
* </pre>
*
* @{
*/
/// Address of the RWNXAGCLNAVGAREF1 register
#define AGC_RWNXAGCLNAVGAREF1_ADDR 0x01002008
/// Offset of the RWNXAGCLNAVGAREF1 register from the base address
#define AGC_RWNXAGCLNAVGAREF1_OFFSET 0x00002008
/// Index of the RWNXAGCLNAVGAREF1 register
#define AGC_RWNXAGCLNAVGAREF1_INDEX 0x00000802
/// Reset value of the RWNXAGCLNAVGAREF1 register
#define AGC_RWNXAGCLNAVGAREF1_RESET 0x001F1E0F
/**
* @brief Returns the current value of the RWNXAGCLNAVGAREF1 register.
* The RWNXAGCLNAVGAREF1 register will be read and its value returned.
* @return The current value of the RWNXAGCLNAVGAREF1 register.
*/
__INLINE uint32_t agc_rwnxagclnavgaref1_get(void)
{
return REG_PL_RD(AGC_RWNXAGCLNAVGAREF1_ADDR);
}
/**
* @brief Sets the RWNXAGCLNAVGAREF1 register to a value.
* The RWNXAGCLNAVGAREF1 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagclnavgaref1_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCLNAVGAREF1_ADDR, value);
}
// field definitions
/// DIGGAIN80VS20 field mask
#define AGC_DIGGAIN80VS20_MASK ((uint32_t)0xF0000000)
/// DIGGAIN80VS20 field LSB position
#define AGC_DIGGAIN80VS20_LSB 28
/// DIGGAIN80VS20 field width
#define AGC_DIGGAIN80VS20_WIDTH ((uint32_t)0x00000004)
/// DIGGAIN40VS20 field mask
#define AGC_DIGGAIN40VS20_MASK ((uint32_t)0x0F000000)
/// DIGGAIN40VS20 field LSB position
#define AGC_DIGGAIN40VS20_LSB 24
/// DIGGAIN40VS20 field width
#define AGC_DIGGAIN40VS20_WIDTH ((uint32_t)0x00000004)
/// VGAINDMAX field mask
#define AGC_VGAINDMAX_MASK ((uint32_t)0x001F0000)
/// VGAINDMAX field LSB position
#define AGC_VGAINDMAX_LSB 16
/// VGAINDMAX field width
#define AGC_VGAINDMAX_WIDTH ((uint32_t)0x00000005)
/// LNAHMTHRDB field mask
#define AGC_LNAHMTHRDB_MASK ((uint32_t)0x00003F00)
/// LNAHMTHRDB field LSB position
#define AGC_LNAHMTHRDB_LSB 8
/// LNAHMTHRDB field width
#define AGC_LNAHMTHRDB_WIDTH ((uint32_t)0x00000006)
/// LNAMLTHRDB field mask
#define AGC_LNAMLTHRDB_MASK ((uint32_t)0x0000003F)
/// LNAMLTHRDB field LSB position
#define AGC_LNAMLTHRDB_LSB 0
/// LNAMLTHRDB field width
#define AGC_LNAMLTHRDB_WIDTH ((uint32_t)0x00000006)
/// DIGGAIN80VS20 field reset value
#define AGC_DIGGAIN80VS20_RST 0x0
/// DIGGAIN40VS20 field reset value
#define AGC_DIGGAIN40VS20_RST 0x0
/// VGAINDMAX field reset value
#define AGC_VGAINDMAX_RST 0x1F
/// LNAHMTHRDB field reset value
#define AGC_LNAHMTHRDB_RST 0x1E
/// LNAMLTHRDB field reset value
#define AGC_LNAMLTHRDB_RST 0xF
/**
* @brief Constructs a value for the RWNXAGCLNAVGAREF1 register given values for its fields
* and writes the value to the register.
*
* @param[in] diggain80vs20 - The value to use for the DIGGAIN80VS20 field.
* @param[in] diggain40vs20 - The value to use for the DIGGAIN40VS20 field.
* @param[in] vgaindmax - The value to use for the VGAINDMAX field.
* @param[in] lnahmthrdb - The value to use for the LNAHMTHRDB field.
* @param[in] lnamlthrdb - The value to use for the LNAMLTHRDB field.
*/
__INLINE void agc_rwnxagclnavgaref1_pack(uint8_t diggain80vs20, uint8_t diggain40vs20, uint8_t vgaindmax, uint8_t lnahmthrdb, uint8_t lnamlthrdb)
{
ASSERT_ERR((((uint32_t)diggain80vs20 << 28) & ~((uint32_t)0xF0000000)) == 0);
ASSERT_ERR((((uint32_t)diggain40vs20 << 24) & ~((uint32_t)0x0F000000)) == 0);
ASSERT_ERR((((uint32_t)vgaindmax << 16) & ~((uint32_t)0x001F0000)) == 0);
ASSERT_ERR((((uint32_t)lnahmthrdb << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)lnamlthrdb << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCLNAVGAREF1_ADDR, ((uint32_t)diggain80vs20 << 28) | ((uint32_t)diggain40vs20 << 24) | ((uint32_t)vgaindmax << 16) | ((uint32_t)lnahmthrdb << 8) | ((uint32_t)lnamlthrdb << 0));
}
/**
* @brief Unpacks RWNXAGCLNAVGAREF1's fields from current value of the RWNXAGCLNAVGAREF1 register.
*
* Reads the RWNXAGCLNAVGAREF1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] diggain80vs20 - Will be populated with the current value of this field from the register.
* @param[out] diggain40vs20 - Will be populated with the current value of this field from the register.
* @param[out] vgaindmax - Will be populated with the current value of this field from the register.
* @param[out] lnahmthrdb - Will be populated with the current value of this field from the register.
* @param[out] lnamlthrdb - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagclnavgaref1_unpack(uint8_t *diggain80vs20, uint8_t *diggain40vs20, uint8_t *vgaindmax, uint8_t *lnahmthrdb, uint8_t *lnamlthrdb)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCLNAVGAREF1_ADDR);
*diggain80vs20 = (localVal & ((uint32_t)0xF0000000)) >> 28;
*diggain40vs20 = (localVal & ((uint32_t)0x0F000000)) >> 24;
*vgaindmax = (localVal & ((uint32_t)0x001F0000)) >> 16;
*lnahmthrdb = (localVal & ((uint32_t)0x00003F00)) >> 8;
*lnamlthrdb = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the DIGGAIN80VS20 field in the RWNXAGCLNAVGAREF1 register.
*
* The RWNXAGCLNAVGAREF1 register will be read and the DIGGAIN80VS20 field's value will be returned.
*
* @return The current value of the DIGGAIN80VS20 field in the RWNXAGCLNAVGAREF1 register.
*/
__INLINE uint8_t agc_diggain80vs20_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCLNAVGAREF1_ADDR);
return ((localVal & ((uint32_t)0xF0000000)) >> 28);
}
/**
* @brief Sets the DIGGAIN80VS20 field of the RWNXAGCLNAVGAREF1 register.
*
* The RWNXAGCLNAVGAREF1 register will be read, modified to contain the new field value, and written.
*
* @param[in] diggain80vs20 - The value to set the field to.
*/
__INLINE void agc_diggain80vs20_setf(uint8_t diggain80vs20)
{
ASSERT_ERR((((uint32_t)diggain80vs20 << 28) & ~((uint32_t)0xF0000000)) == 0);
REG_PL_WR(AGC_RWNXAGCLNAVGAREF1_ADDR, (REG_PL_RD(AGC_RWNXAGCLNAVGAREF1_ADDR) & ~((uint32_t)0xF0000000)) | ((uint32_t)diggain80vs20 << 28));
}
/**
* @brief Returns the current value of the DIGGAIN40VS20 field in the RWNXAGCLNAVGAREF1 register.
*
* The RWNXAGCLNAVGAREF1 register will be read and the DIGGAIN40VS20 field's value will be returned.
*
* @return The current value of the DIGGAIN40VS20 field in the RWNXAGCLNAVGAREF1 register.
*/
__INLINE uint8_t agc_diggain40vs20_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCLNAVGAREF1_ADDR);
return ((localVal & ((uint32_t)0x0F000000)) >> 24);
}
/**
* @brief Sets the DIGGAIN40VS20 field of the RWNXAGCLNAVGAREF1 register.
*
* The RWNXAGCLNAVGAREF1 register will be read, modified to contain the new field value, and written.
*
* @param[in] diggain40vs20 - The value to set the field to.
*/
__INLINE void agc_diggain40vs20_setf(uint8_t diggain40vs20)
{
ASSERT_ERR((((uint32_t)diggain40vs20 << 24) & ~((uint32_t)0x0F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCLNAVGAREF1_ADDR, (REG_PL_RD(AGC_RWNXAGCLNAVGAREF1_ADDR) & ~((uint32_t)0x0F000000)) | ((uint32_t)diggain40vs20 << 24));
}
/**
* @brief Returns the current value of the VGAINDMAX field in the RWNXAGCLNAVGAREF1 register.
*
* The RWNXAGCLNAVGAREF1 register will be read and the VGAINDMAX field's value will be returned.
*
* @return The current value of the VGAINDMAX field in the RWNXAGCLNAVGAREF1 register.
*/
__INLINE uint8_t agc_vgaindmax_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCLNAVGAREF1_ADDR);
return ((localVal & ((uint32_t)0x001F0000)) >> 16);
}
/**
* @brief Sets the VGAINDMAX field of the RWNXAGCLNAVGAREF1 register.
*
* The RWNXAGCLNAVGAREF1 register will be read, modified to contain the new field value, and written.
*
* @param[in] vgaindmax - The value to set the field to.
*/
__INLINE void agc_vgaindmax_setf(uint8_t vgaindmax)
{
ASSERT_ERR((((uint32_t)vgaindmax << 16) & ~((uint32_t)0x001F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCLNAVGAREF1_ADDR, (REG_PL_RD(AGC_RWNXAGCLNAVGAREF1_ADDR) & ~((uint32_t)0x001F0000)) | ((uint32_t)vgaindmax << 16));
}
/**
* @brief Returns the current value of the LNAHMTHRDB field in the RWNXAGCLNAVGAREF1 register.
*
* The RWNXAGCLNAVGAREF1 register will be read and the LNAHMTHRDB field's value will be returned.
*
* @return The current value of the LNAHMTHRDB field in the RWNXAGCLNAVGAREF1 register.
*/
__INLINE uint8_t agc_lnahmthrdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCLNAVGAREF1_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the LNAHMTHRDB field of the RWNXAGCLNAVGAREF1 register.
*
* The RWNXAGCLNAVGAREF1 register will be read, modified to contain the new field value, and written.
*
* @param[in] lnahmthrdb - The value to set the field to.
*/
__INLINE void agc_lnahmthrdb_setf(uint8_t lnahmthrdb)
{
ASSERT_ERR((((uint32_t)lnahmthrdb << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCLNAVGAREF1_ADDR, (REG_PL_RD(AGC_RWNXAGCLNAVGAREF1_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)lnahmthrdb << 8));
}
/**
* @brief Returns the current value of the LNAMLTHRDB field in the RWNXAGCLNAVGAREF1 register.
*
* The RWNXAGCLNAVGAREF1 register will be read and the LNAMLTHRDB field's value will be returned.
*
* @return The current value of the LNAMLTHRDB field in the RWNXAGCLNAVGAREF1 register.
*/
__INLINE uint8_t agc_lnamlthrdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCLNAVGAREF1_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the LNAMLTHRDB field of the RWNXAGCLNAVGAREF1 register.
*
* The RWNXAGCLNAVGAREF1 register will be read, modified to contain the new field value, and written.
*
* @param[in] lnamlthrdb - The value to set the field to.
*/
__INLINE void agc_lnamlthrdb_setf(uint8_t lnamlthrdb)
{
ASSERT_ERR((((uint32_t)lnamlthrdb << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCLNAVGAREF1_ADDR, (REG_PL_RD(AGC_RWNXAGCLNAVGAREF1_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)lnamlthrdb << 0));
}
/// @}
/**
* @name RWNXAGCACI20MARG0 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:24 ACI20MARGMCS3 0x2
* 21:16 ACI20MARGMCS2 0x4
* 13:08 ACI20MARGMCS1 0x5
* 05:00 ACI20MARGMCS0 0x7
* </pre>
*
* @{
*/
/// Address of the RWNXAGCACI20MARG0 register
#define AGC_RWNXAGCACI20MARG0_ADDR 0x0100200C
/// Offset of the RWNXAGCACI20MARG0 register from the base address
#define AGC_RWNXAGCACI20MARG0_OFFSET 0x0000200C
/// Index of the RWNXAGCACI20MARG0 register
#define AGC_RWNXAGCACI20MARG0_INDEX 0x00000803
/// Reset value of the RWNXAGCACI20MARG0 register
#define AGC_RWNXAGCACI20MARG0_RESET 0x02040507
/**
* @brief Returns the current value of the RWNXAGCACI20MARG0 register.
* The RWNXAGCACI20MARG0 register will be read and its value returned.
* @return The current value of the RWNXAGCACI20MARG0 register.
*/
__INLINE uint32_t agc_rwnxagcaci20marg0_get(void)
{
return REG_PL_RD(AGC_RWNXAGCACI20MARG0_ADDR);
}
/**
* @brief Sets the RWNXAGCACI20MARG0 register to a value.
* The RWNXAGCACI20MARG0 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcaci20marg0_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCACI20MARG0_ADDR, value);
}
// field definitions
/// ACI20MARGMCS3 field mask
#define AGC_ACI20MARGMCS3_MASK ((uint32_t)0x3F000000)
/// ACI20MARGMCS3 field LSB position
#define AGC_ACI20MARGMCS3_LSB 24
/// ACI20MARGMCS3 field width
#define AGC_ACI20MARGMCS3_WIDTH ((uint32_t)0x00000006)
/// ACI20MARGMCS2 field mask
#define AGC_ACI20MARGMCS2_MASK ((uint32_t)0x003F0000)
/// ACI20MARGMCS2 field LSB position
#define AGC_ACI20MARGMCS2_LSB 16
/// ACI20MARGMCS2 field width
#define AGC_ACI20MARGMCS2_WIDTH ((uint32_t)0x00000006)
/// ACI20MARGMCS1 field mask
#define AGC_ACI20MARGMCS1_MASK ((uint32_t)0x00003F00)
/// ACI20MARGMCS1 field LSB position
#define AGC_ACI20MARGMCS1_LSB 8
/// ACI20MARGMCS1 field width
#define AGC_ACI20MARGMCS1_WIDTH ((uint32_t)0x00000006)
/// ACI20MARGMCS0 field mask
#define AGC_ACI20MARGMCS0_MASK ((uint32_t)0x0000003F)
/// ACI20MARGMCS0 field LSB position
#define AGC_ACI20MARGMCS0_LSB 0
/// ACI20MARGMCS0 field width
#define AGC_ACI20MARGMCS0_WIDTH ((uint32_t)0x00000006)
/// ACI20MARGMCS3 field reset value
#define AGC_ACI20MARGMCS3_RST 0x2
/// ACI20MARGMCS2 field reset value
#define AGC_ACI20MARGMCS2_RST 0x4
/// ACI20MARGMCS1 field reset value
#define AGC_ACI20MARGMCS1_RST 0x5
/// ACI20MARGMCS0 field reset value
#define AGC_ACI20MARGMCS0_RST 0x7
/**
* @brief Constructs a value for the RWNXAGCACI20MARG0 register given values for its fields
* and writes the value to the register.
*
* @param[in] aci20margmcs3 - The value to use for the ACI20MARGMCS3 field.
* @param[in] aci20margmcs2 - The value to use for the ACI20MARGMCS2 field.
* @param[in] aci20margmcs1 - The value to use for the ACI20MARGMCS1 field.
* @param[in] aci20margmcs0 - The value to use for the ACI20MARGMCS0 field.
*/
__INLINE void agc_rwnxagcaci20marg0_pack(uint8_t aci20margmcs3, uint8_t aci20margmcs2, uint8_t aci20margmcs1, uint8_t aci20margmcs0)
{
ASSERT_ERR((((uint32_t)aci20margmcs3 << 24) & ~((uint32_t)0x3F000000)) == 0);
ASSERT_ERR((((uint32_t)aci20margmcs2 << 16) & ~((uint32_t)0x003F0000)) == 0);
ASSERT_ERR((((uint32_t)aci20margmcs1 << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)aci20margmcs0 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG0_ADDR, ((uint32_t)aci20margmcs3 << 24) | ((uint32_t)aci20margmcs2 << 16) | ((uint32_t)aci20margmcs1 << 8) | ((uint32_t)aci20margmcs0 << 0));
}
/**
* @brief Unpacks RWNXAGCACI20MARG0's fields from current value of the RWNXAGCACI20MARG0 register.
*
* Reads the RWNXAGCACI20MARG0 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] aci20margmcs3 - Will be populated with the current value of this field from the register.
* @param[out] aci20margmcs2 - Will be populated with the current value of this field from the register.
* @param[out] aci20margmcs1 - Will be populated with the current value of this field from the register.
* @param[out] aci20margmcs0 - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcaci20marg0_unpack(uint8_t *aci20margmcs3, uint8_t *aci20margmcs2, uint8_t *aci20margmcs1, uint8_t *aci20margmcs0)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG0_ADDR);
*aci20margmcs3 = (localVal & ((uint32_t)0x3F000000)) >> 24;
*aci20margmcs2 = (localVal & ((uint32_t)0x003F0000)) >> 16;
*aci20margmcs1 = (localVal & ((uint32_t)0x00003F00)) >> 8;
*aci20margmcs0 = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the ACI20MARGMCS3 field in the RWNXAGCACI20MARG0 register.
*
* The RWNXAGCACI20MARG0 register will be read and the ACI20MARGMCS3 field's value will be returned.
*
* @return The current value of the ACI20MARGMCS3 field in the RWNXAGCACI20MARG0 register.
*/
__INLINE uint8_t agc_aci20margmcs3_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG0_ADDR);
return ((localVal & ((uint32_t)0x3F000000)) >> 24);
}
/**
* @brief Sets the ACI20MARGMCS3 field of the RWNXAGCACI20MARG0 register.
*
* The RWNXAGCACI20MARG0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci20margmcs3 - The value to set the field to.
*/
__INLINE void agc_aci20margmcs3_setf(uint8_t aci20margmcs3)
{
ASSERT_ERR((((uint32_t)aci20margmcs3 << 24) & ~((uint32_t)0x3F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG0_ADDR, (REG_PL_RD(AGC_RWNXAGCACI20MARG0_ADDR) & ~((uint32_t)0x3F000000)) | ((uint32_t)aci20margmcs3 << 24));
}
/**
* @brief Returns the current value of the ACI20MARGMCS2 field in the RWNXAGCACI20MARG0 register.
*
* The RWNXAGCACI20MARG0 register will be read and the ACI20MARGMCS2 field's value will be returned.
*
* @return The current value of the ACI20MARGMCS2 field in the RWNXAGCACI20MARG0 register.
*/
__INLINE uint8_t agc_aci20margmcs2_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG0_ADDR);
return ((localVal & ((uint32_t)0x003F0000)) >> 16);
}
/**
* @brief Sets the ACI20MARGMCS2 field of the RWNXAGCACI20MARG0 register.
*
* The RWNXAGCACI20MARG0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci20margmcs2 - The value to set the field to.
*/
__INLINE void agc_aci20margmcs2_setf(uint8_t aci20margmcs2)
{
ASSERT_ERR((((uint32_t)aci20margmcs2 << 16) & ~((uint32_t)0x003F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG0_ADDR, (REG_PL_RD(AGC_RWNXAGCACI20MARG0_ADDR) & ~((uint32_t)0x003F0000)) | ((uint32_t)aci20margmcs2 << 16));
}
/**
* @brief Returns the current value of the ACI20MARGMCS1 field in the RWNXAGCACI20MARG0 register.
*
* The RWNXAGCACI20MARG0 register will be read and the ACI20MARGMCS1 field's value will be returned.
*
* @return The current value of the ACI20MARGMCS1 field in the RWNXAGCACI20MARG0 register.
*/
__INLINE uint8_t agc_aci20margmcs1_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG0_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the ACI20MARGMCS1 field of the RWNXAGCACI20MARG0 register.
*
* The RWNXAGCACI20MARG0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci20margmcs1 - The value to set the field to.
*/
__INLINE void agc_aci20margmcs1_setf(uint8_t aci20margmcs1)
{
ASSERT_ERR((((uint32_t)aci20margmcs1 << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG0_ADDR, (REG_PL_RD(AGC_RWNXAGCACI20MARG0_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)aci20margmcs1 << 8));
}
/**
* @brief Returns the current value of the ACI20MARGMCS0 field in the RWNXAGCACI20MARG0 register.
*
* The RWNXAGCACI20MARG0 register will be read and the ACI20MARGMCS0 field's value will be returned.
*
* @return The current value of the ACI20MARGMCS0 field in the RWNXAGCACI20MARG0 register.
*/
__INLINE uint8_t agc_aci20margmcs0_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG0_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the ACI20MARGMCS0 field of the RWNXAGCACI20MARG0 register.
*
* The RWNXAGCACI20MARG0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci20margmcs0 - The value to set the field to.
*/
__INLINE void agc_aci20margmcs0_setf(uint8_t aci20margmcs0)
{
ASSERT_ERR((((uint32_t)aci20margmcs0 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG0_ADDR, (REG_PL_RD(AGC_RWNXAGCACI20MARG0_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)aci20margmcs0 << 0));
}
/// @}
/**
* @name RWNXAGCACI20MARG1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:24 ACI20MARGMCS7 0x0
* 21:16 ACI20MARGMCS6 0x0
* 13:08 ACI20MARGMCS5 0x0
* 05:00 ACI20MARGMCS4 0x1
* </pre>
*
* @{
*/
/// Address of the RWNXAGCACI20MARG1 register
#define AGC_RWNXAGCACI20MARG1_ADDR 0x01002010
/// Offset of the RWNXAGCACI20MARG1 register from the base address
#define AGC_RWNXAGCACI20MARG1_OFFSET 0x00002010
/// Index of the RWNXAGCACI20MARG1 register
#define AGC_RWNXAGCACI20MARG1_INDEX 0x00000804
/// Reset value of the RWNXAGCACI20MARG1 register
#define AGC_RWNXAGCACI20MARG1_RESET 0x00000001
/**
* @brief Returns the current value of the RWNXAGCACI20MARG1 register.
* The RWNXAGCACI20MARG1 register will be read and its value returned.
* @return The current value of the RWNXAGCACI20MARG1 register.
*/
__INLINE uint32_t agc_rwnxagcaci20marg1_get(void)
{
return REG_PL_RD(AGC_RWNXAGCACI20MARG1_ADDR);
}
/**
* @brief Sets the RWNXAGCACI20MARG1 register to a value.
* The RWNXAGCACI20MARG1 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcaci20marg1_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCACI20MARG1_ADDR, value);
}
// field definitions
/// ACI20MARGMCS7 field mask
#define AGC_ACI20MARGMCS7_MASK ((uint32_t)0x3F000000)
/// ACI20MARGMCS7 field LSB position
#define AGC_ACI20MARGMCS7_LSB 24
/// ACI20MARGMCS7 field width
#define AGC_ACI20MARGMCS7_WIDTH ((uint32_t)0x00000006)
/// ACI20MARGMCS6 field mask
#define AGC_ACI20MARGMCS6_MASK ((uint32_t)0x003F0000)
/// ACI20MARGMCS6 field LSB position
#define AGC_ACI20MARGMCS6_LSB 16
/// ACI20MARGMCS6 field width
#define AGC_ACI20MARGMCS6_WIDTH ((uint32_t)0x00000006)
/// ACI20MARGMCS5 field mask
#define AGC_ACI20MARGMCS5_MASK ((uint32_t)0x00003F00)
/// ACI20MARGMCS5 field LSB position
#define AGC_ACI20MARGMCS5_LSB 8
/// ACI20MARGMCS5 field width
#define AGC_ACI20MARGMCS5_WIDTH ((uint32_t)0x00000006)
/// ACI20MARGMCS4 field mask
#define AGC_ACI20MARGMCS4_MASK ((uint32_t)0x0000003F)
/// ACI20MARGMCS4 field LSB position
#define AGC_ACI20MARGMCS4_LSB 0
/// ACI20MARGMCS4 field width
#define AGC_ACI20MARGMCS4_WIDTH ((uint32_t)0x00000006)
/// ACI20MARGMCS7 field reset value
#define AGC_ACI20MARGMCS7_RST 0x0
/// ACI20MARGMCS6 field reset value
#define AGC_ACI20MARGMCS6_RST 0x0
/// ACI20MARGMCS5 field reset value
#define AGC_ACI20MARGMCS5_RST 0x0
/// ACI20MARGMCS4 field reset value
#define AGC_ACI20MARGMCS4_RST 0x1
/**
* @brief Constructs a value for the RWNXAGCACI20MARG1 register given values for its fields
* and writes the value to the register.
*
* @param[in] aci20margmcs7 - The value to use for the ACI20MARGMCS7 field.
* @param[in] aci20margmcs6 - The value to use for the ACI20MARGMCS6 field.
* @param[in] aci20margmcs5 - The value to use for the ACI20MARGMCS5 field.
* @param[in] aci20margmcs4 - The value to use for the ACI20MARGMCS4 field.
*/
__INLINE void agc_rwnxagcaci20marg1_pack(uint8_t aci20margmcs7, uint8_t aci20margmcs6, uint8_t aci20margmcs5, uint8_t aci20margmcs4)
{
ASSERT_ERR((((uint32_t)aci20margmcs7 << 24) & ~((uint32_t)0x3F000000)) == 0);
ASSERT_ERR((((uint32_t)aci20margmcs6 << 16) & ~((uint32_t)0x003F0000)) == 0);
ASSERT_ERR((((uint32_t)aci20margmcs5 << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)aci20margmcs4 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG1_ADDR, ((uint32_t)aci20margmcs7 << 24) | ((uint32_t)aci20margmcs6 << 16) | ((uint32_t)aci20margmcs5 << 8) | ((uint32_t)aci20margmcs4 << 0));
}
/**
* @brief Unpacks RWNXAGCACI20MARG1's fields from current value of the RWNXAGCACI20MARG1 register.
*
* Reads the RWNXAGCACI20MARG1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] aci20margmcs7 - Will be populated with the current value of this field from the register.
* @param[out] aci20margmcs6 - Will be populated with the current value of this field from the register.
* @param[out] aci20margmcs5 - Will be populated with the current value of this field from the register.
* @param[out] aci20margmcs4 - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcaci20marg1_unpack(uint8_t *aci20margmcs7, uint8_t *aci20margmcs6, uint8_t *aci20margmcs5, uint8_t *aci20margmcs4)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG1_ADDR);
*aci20margmcs7 = (localVal & ((uint32_t)0x3F000000)) >> 24;
*aci20margmcs6 = (localVal & ((uint32_t)0x003F0000)) >> 16;
*aci20margmcs5 = (localVal & ((uint32_t)0x00003F00)) >> 8;
*aci20margmcs4 = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the ACI20MARGMCS7 field in the RWNXAGCACI20MARG1 register.
*
* The RWNXAGCACI20MARG1 register will be read and the ACI20MARGMCS7 field's value will be returned.
*
* @return The current value of the ACI20MARGMCS7 field in the RWNXAGCACI20MARG1 register.
*/
__INLINE uint8_t agc_aci20margmcs7_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG1_ADDR);
return ((localVal & ((uint32_t)0x3F000000)) >> 24);
}
/**
* @brief Sets the ACI20MARGMCS7 field of the RWNXAGCACI20MARG1 register.
*
* The RWNXAGCACI20MARG1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci20margmcs7 - The value to set the field to.
*/
__INLINE void agc_aci20margmcs7_setf(uint8_t aci20margmcs7)
{
ASSERT_ERR((((uint32_t)aci20margmcs7 << 24) & ~((uint32_t)0x3F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG1_ADDR, (REG_PL_RD(AGC_RWNXAGCACI20MARG1_ADDR) & ~((uint32_t)0x3F000000)) | ((uint32_t)aci20margmcs7 << 24));
}
/**
* @brief Returns the current value of the ACI20MARGMCS6 field in the RWNXAGCACI20MARG1 register.
*
* The RWNXAGCACI20MARG1 register will be read and the ACI20MARGMCS6 field's value will be returned.
*
* @return The current value of the ACI20MARGMCS6 field in the RWNXAGCACI20MARG1 register.
*/
__INLINE uint8_t agc_aci20margmcs6_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG1_ADDR);
return ((localVal & ((uint32_t)0x003F0000)) >> 16);
}
/**
* @brief Sets the ACI20MARGMCS6 field of the RWNXAGCACI20MARG1 register.
*
* The RWNXAGCACI20MARG1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci20margmcs6 - The value to set the field to.
*/
__INLINE void agc_aci20margmcs6_setf(uint8_t aci20margmcs6)
{
ASSERT_ERR((((uint32_t)aci20margmcs6 << 16) & ~((uint32_t)0x003F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG1_ADDR, (REG_PL_RD(AGC_RWNXAGCACI20MARG1_ADDR) & ~((uint32_t)0x003F0000)) | ((uint32_t)aci20margmcs6 << 16));
}
/**
* @brief Returns the current value of the ACI20MARGMCS5 field in the RWNXAGCACI20MARG1 register.
*
* The RWNXAGCACI20MARG1 register will be read and the ACI20MARGMCS5 field's value will be returned.
*
* @return The current value of the ACI20MARGMCS5 field in the RWNXAGCACI20MARG1 register.
*/
__INLINE uint8_t agc_aci20margmcs5_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG1_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the ACI20MARGMCS5 field of the RWNXAGCACI20MARG1 register.
*
* The RWNXAGCACI20MARG1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci20margmcs5 - The value to set the field to.
*/
__INLINE void agc_aci20margmcs5_setf(uint8_t aci20margmcs5)
{
ASSERT_ERR((((uint32_t)aci20margmcs5 << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG1_ADDR, (REG_PL_RD(AGC_RWNXAGCACI20MARG1_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)aci20margmcs5 << 8));
}
/**
* @brief Returns the current value of the ACI20MARGMCS4 field in the RWNXAGCACI20MARG1 register.
*
* The RWNXAGCACI20MARG1 register will be read and the ACI20MARGMCS4 field's value will be returned.
*
* @return The current value of the ACI20MARGMCS4 field in the RWNXAGCACI20MARG1 register.
*/
__INLINE uint8_t agc_aci20margmcs4_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG1_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the ACI20MARGMCS4 field of the RWNXAGCACI20MARG1 register.
*
* The RWNXAGCACI20MARG1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci20margmcs4 - The value to set the field to.
*/
__INLINE void agc_aci20margmcs4_setf(uint8_t aci20margmcs4)
{
ASSERT_ERR((((uint32_t)aci20margmcs4 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG1_ADDR, (REG_PL_RD(AGC_RWNXAGCACI20MARG1_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)aci20margmcs4 << 0));
}
/// @}
/**
* @name RWNXAGCACI20MARG2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 13:08 ACI20MARGMCS9 0x0
* 05:00 ACI20MARGMCS8 0x0
* </pre>
*
* @{
*/
/// Address of the RWNXAGCACI20MARG2 register
#define AGC_RWNXAGCACI20MARG2_ADDR 0x01002014
/// Offset of the RWNXAGCACI20MARG2 register from the base address
#define AGC_RWNXAGCACI20MARG2_OFFSET 0x00002014
/// Index of the RWNXAGCACI20MARG2 register
#define AGC_RWNXAGCACI20MARG2_INDEX 0x00000805
/// Reset value of the RWNXAGCACI20MARG2 register
#define AGC_RWNXAGCACI20MARG2_RESET 0x00000000
/**
* @brief Returns the current value of the RWNXAGCACI20MARG2 register.
* The RWNXAGCACI20MARG2 register will be read and its value returned.
* @return The current value of the RWNXAGCACI20MARG2 register.
*/
__INLINE uint32_t agc_rwnxagcaci20marg2_get(void)
{
return REG_PL_RD(AGC_RWNXAGCACI20MARG2_ADDR);
}
/**
* @brief Sets the RWNXAGCACI20MARG2 register to a value.
* The RWNXAGCACI20MARG2 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcaci20marg2_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCACI20MARG2_ADDR, value);
}
// field definitions
/// ACI20MARGMCS9 field mask
#define AGC_ACI20MARGMCS9_MASK ((uint32_t)0x00003F00)
/// ACI20MARGMCS9 field LSB position
#define AGC_ACI20MARGMCS9_LSB 8
/// ACI20MARGMCS9 field width
#define AGC_ACI20MARGMCS9_WIDTH ((uint32_t)0x00000006)
/// ACI20MARGMCS8 field mask
#define AGC_ACI20MARGMCS8_MASK ((uint32_t)0x0000003F)
/// ACI20MARGMCS8 field LSB position
#define AGC_ACI20MARGMCS8_LSB 0
/// ACI20MARGMCS8 field width
#define AGC_ACI20MARGMCS8_WIDTH ((uint32_t)0x00000006)
/// ACI20MARGMCS9 field reset value
#define AGC_ACI20MARGMCS9_RST 0x0
/// ACI20MARGMCS8 field reset value
#define AGC_ACI20MARGMCS8_RST 0x0
/**
* @brief Constructs a value for the RWNXAGCACI20MARG2 register given values for its fields
* and writes the value to the register.
*
* @param[in] aci20margmcs9 - The value to use for the ACI20MARGMCS9 field.
* @param[in] aci20margmcs8 - The value to use for the ACI20MARGMCS8 field.
*/
__INLINE void agc_rwnxagcaci20marg2_pack(uint8_t aci20margmcs9, uint8_t aci20margmcs8)
{
ASSERT_ERR((((uint32_t)aci20margmcs9 << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)aci20margmcs8 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG2_ADDR, ((uint32_t)aci20margmcs9 << 8) | ((uint32_t)aci20margmcs8 << 0));
}
/**
* @brief Unpacks RWNXAGCACI20MARG2's fields from current value of the RWNXAGCACI20MARG2 register.
*
* Reads the RWNXAGCACI20MARG2 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] aci20margmcs9 - Will be populated with the current value of this field from the register.
* @param[out] aci20margmcs8 - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcaci20marg2_unpack(uint8_t *aci20margmcs9, uint8_t *aci20margmcs8)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG2_ADDR);
*aci20margmcs9 = (localVal & ((uint32_t)0x00003F00)) >> 8;
*aci20margmcs8 = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the ACI20MARGMCS9 field in the RWNXAGCACI20MARG2 register.
*
* The RWNXAGCACI20MARG2 register will be read and the ACI20MARGMCS9 field's value will be returned.
*
* @return The current value of the ACI20MARGMCS9 field in the RWNXAGCACI20MARG2 register.
*/
__INLINE uint8_t agc_aci20margmcs9_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG2_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the ACI20MARGMCS9 field of the RWNXAGCACI20MARG2 register.
*
* The RWNXAGCACI20MARG2 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci20margmcs9 - The value to set the field to.
*/
__INLINE void agc_aci20margmcs9_setf(uint8_t aci20margmcs9)
{
ASSERT_ERR((((uint32_t)aci20margmcs9 << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG2_ADDR, (REG_PL_RD(AGC_RWNXAGCACI20MARG2_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)aci20margmcs9 << 8));
}
/**
* @brief Returns the current value of the ACI20MARGMCS8 field in the RWNXAGCACI20MARG2 register.
*
* The RWNXAGCACI20MARG2 register will be read and the ACI20MARGMCS8 field's value will be returned.
*
* @return The current value of the ACI20MARGMCS8 field in the RWNXAGCACI20MARG2 register.
*/
__INLINE uint8_t agc_aci20margmcs8_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI20MARG2_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the ACI20MARGMCS8 field of the RWNXAGCACI20MARG2 register.
*
* The RWNXAGCACI20MARG2 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci20margmcs8 - The value to set the field to.
*/
__INLINE void agc_aci20margmcs8_setf(uint8_t aci20margmcs8)
{
ASSERT_ERR((((uint32_t)aci20margmcs8 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI20MARG2_ADDR, (REG_PL_RD(AGC_RWNXAGCACI20MARG2_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)aci20margmcs8 << 0));
}
/// @}
/**
* @name RWNXAGCACI40MARG0 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:24 ACI40MARGMCS3 0x9
* 21:16 ACI40MARGMCS2 0xB
* 13:08 ACI40MARGMCS1 0xD
* 05:00 ACI40MARGMCS0 0x10
* </pre>
*
* @{
*/
/// Address of the RWNXAGCACI40MARG0 register
#define AGC_RWNXAGCACI40MARG0_ADDR 0x01002018
/// Offset of the RWNXAGCACI40MARG0 register from the base address
#define AGC_RWNXAGCACI40MARG0_OFFSET 0x00002018
/// Index of the RWNXAGCACI40MARG0 register
#define AGC_RWNXAGCACI40MARG0_INDEX 0x00000806
/// Reset value of the RWNXAGCACI40MARG0 register
#define AGC_RWNXAGCACI40MARG0_RESET 0x090B0D10
/**
* @brief Returns the current value of the RWNXAGCACI40MARG0 register.
* The RWNXAGCACI40MARG0 register will be read and its value returned.
* @return The current value of the RWNXAGCACI40MARG0 register.
*/
__INLINE uint32_t agc_rwnxagcaci40marg0_get(void)
{
return REG_PL_RD(AGC_RWNXAGCACI40MARG0_ADDR);
}
/**
* @brief Sets the RWNXAGCACI40MARG0 register to a value.
* The RWNXAGCACI40MARG0 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcaci40marg0_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCACI40MARG0_ADDR, value);
}
// field definitions
/// ACI40MARGMCS3 field mask
#define AGC_ACI40MARGMCS3_MASK ((uint32_t)0x3F000000)
/// ACI40MARGMCS3 field LSB position
#define AGC_ACI40MARGMCS3_LSB 24
/// ACI40MARGMCS3 field width
#define AGC_ACI40MARGMCS3_WIDTH ((uint32_t)0x00000006)
/// ACI40MARGMCS2 field mask
#define AGC_ACI40MARGMCS2_MASK ((uint32_t)0x003F0000)
/// ACI40MARGMCS2 field LSB position
#define AGC_ACI40MARGMCS2_LSB 16
/// ACI40MARGMCS2 field width
#define AGC_ACI40MARGMCS2_WIDTH ((uint32_t)0x00000006)
/// ACI40MARGMCS1 field mask
#define AGC_ACI40MARGMCS1_MASK ((uint32_t)0x00003F00)
/// ACI40MARGMCS1 field LSB position
#define AGC_ACI40MARGMCS1_LSB 8
/// ACI40MARGMCS1 field width
#define AGC_ACI40MARGMCS1_WIDTH ((uint32_t)0x00000006)
/// ACI40MARGMCS0 field mask
#define AGC_ACI40MARGMCS0_MASK ((uint32_t)0x0000003F)
/// ACI40MARGMCS0 field LSB position
#define AGC_ACI40MARGMCS0_LSB 0
/// ACI40MARGMCS0 field width
#define AGC_ACI40MARGMCS0_WIDTH ((uint32_t)0x00000006)
/// ACI40MARGMCS3 field reset value
#define AGC_ACI40MARGMCS3_RST 0x9
/// ACI40MARGMCS2 field reset value
#define AGC_ACI40MARGMCS2_RST 0xB
/// ACI40MARGMCS1 field reset value
#define AGC_ACI40MARGMCS1_RST 0xD
/// ACI40MARGMCS0 field reset value
#define AGC_ACI40MARGMCS0_RST 0x10
/**
* @brief Constructs a value for the RWNXAGCACI40MARG0 register given values for its fields
* and writes the value to the register.
*
* @param[in] aci40margmcs3 - The value to use for the ACI40MARGMCS3 field.
* @param[in] aci40margmcs2 - The value to use for the ACI40MARGMCS2 field.
* @param[in] aci40margmcs1 - The value to use for the ACI40MARGMCS1 field.
* @param[in] aci40margmcs0 - The value to use for the ACI40MARGMCS0 field.
*/
__INLINE void agc_rwnxagcaci40marg0_pack(uint8_t aci40margmcs3, uint8_t aci40margmcs2, uint8_t aci40margmcs1, uint8_t aci40margmcs0)
{
ASSERT_ERR((((uint32_t)aci40margmcs3 << 24) & ~((uint32_t)0x3F000000)) == 0);
ASSERT_ERR((((uint32_t)aci40margmcs2 << 16) & ~((uint32_t)0x003F0000)) == 0);
ASSERT_ERR((((uint32_t)aci40margmcs1 << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)aci40margmcs0 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG0_ADDR, ((uint32_t)aci40margmcs3 << 24) | ((uint32_t)aci40margmcs2 << 16) | ((uint32_t)aci40margmcs1 << 8) | ((uint32_t)aci40margmcs0 << 0));
}
/**
* @brief Unpacks RWNXAGCACI40MARG0's fields from current value of the RWNXAGCACI40MARG0 register.
*
* Reads the RWNXAGCACI40MARG0 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] aci40margmcs3 - Will be populated with the current value of this field from the register.
* @param[out] aci40margmcs2 - Will be populated with the current value of this field from the register.
* @param[out] aci40margmcs1 - Will be populated with the current value of this field from the register.
* @param[out] aci40margmcs0 - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcaci40marg0_unpack(uint8_t *aci40margmcs3, uint8_t *aci40margmcs2, uint8_t *aci40margmcs1, uint8_t *aci40margmcs0)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG0_ADDR);
*aci40margmcs3 = (localVal & ((uint32_t)0x3F000000)) >> 24;
*aci40margmcs2 = (localVal & ((uint32_t)0x003F0000)) >> 16;
*aci40margmcs1 = (localVal & ((uint32_t)0x00003F00)) >> 8;
*aci40margmcs0 = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the ACI40MARGMCS3 field in the RWNXAGCACI40MARG0 register.
*
* The RWNXAGCACI40MARG0 register will be read and the ACI40MARGMCS3 field's value will be returned.
*
* @return The current value of the ACI40MARGMCS3 field in the RWNXAGCACI40MARG0 register.
*/
__INLINE uint8_t agc_aci40margmcs3_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG0_ADDR);
return ((localVal & ((uint32_t)0x3F000000)) >> 24);
}
/**
* @brief Sets the ACI40MARGMCS3 field of the RWNXAGCACI40MARG0 register.
*
* The RWNXAGCACI40MARG0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci40margmcs3 - The value to set the field to.
*/
__INLINE void agc_aci40margmcs3_setf(uint8_t aci40margmcs3)
{
ASSERT_ERR((((uint32_t)aci40margmcs3 << 24) & ~((uint32_t)0x3F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG0_ADDR, (REG_PL_RD(AGC_RWNXAGCACI40MARG0_ADDR) & ~((uint32_t)0x3F000000)) | ((uint32_t)aci40margmcs3 << 24));
}
/**
* @brief Returns the current value of the ACI40MARGMCS2 field in the RWNXAGCACI40MARG0 register.
*
* The RWNXAGCACI40MARG0 register will be read and the ACI40MARGMCS2 field's value will be returned.
*
* @return The current value of the ACI40MARGMCS2 field in the RWNXAGCACI40MARG0 register.
*/
__INLINE uint8_t agc_aci40margmcs2_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG0_ADDR);
return ((localVal & ((uint32_t)0x003F0000)) >> 16);
}
/**
* @brief Sets the ACI40MARGMCS2 field of the RWNXAGCACI40MARG0 register.
*
* The RWNXAGCACI40MARG0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci40margmcs2 - The value to set the field to.
*/
__INLINE void agc_aci40margmcs2_setf(uint8_t aci40margmcs2)
{
ASSERT_ERR((((uint32_t)aci40margmcs2 << 16) & ~((uint32_t)0x003F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG0_ADDR, (REG_PL_RD(AGC_RWNXAGCACI40MARG0_ADDR) & ~((uint32_t)0x003F0000)) | ((uint32_t)aci40margmcs2 << 16));
}
/**
* @brief Returns the current value of the ACI40MARGMCS1 field in the RWNXAGCACI40MARG0 register.
*
* The RWNXAGCACI40MARG0 register will be read and the ACI40MARGMCS1 field's value will be returned.
*
* @return The current value of the ACI40MARGMCS1 field in the RWNXAGCACI40MARG0 register.
*/
__INLINE uint8_t agc_aci40margmcs1_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG0_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the ACI40MARGMCS1 field of the RWNXAGCACI40MARG0 register.
*
* The RWNXAGCACI40MARG0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci40margmcs1 - The value to set the field to.
*/
__INLINE void agc_aci40margmcs1_setf(uint8_t aci40margmcs1)
{
ASSERT_ERR((((uint32_t)aci40margmcs1 << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG0_ADDR, (REG_PL_RD(AGC_RWNXAGCACI40MARG0_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)aci40margmcs1 << 8));
}
/**
* @brief Returns the current value of the ACI40MARGMCS0 field in the RWNXAGCACI40MARG0 register.
*
* The RWNXAGCACI40MARG0 register will be read and the ACI40MARGMCS0 field's value will be returned.
*
* @return The current value of the ACI40MARGMCS0 field in the RWNXAGCACI40MARG0 register.
*/
__INLINE uint8_t agc_aci40margmcs0_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG0_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the ACI40MARGMCS0 field of the RWNXAGCACI40MARG0 register.
*
* The RWNXAGCACI40MARG0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci40margmcs0 - The value to set the field to.
*/
__INLINE void agc_aci40margmcs0_setf(uint8_t aci40margmcs0)
{
ASSERT_ERR((((uint32_t)aci40margmcs0 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG0_ADDR, (REG_PL_RD(AGC_RWNXAGCACI40MARG0_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)aci40margmcs0 << 0));
}
/// @}
/**
* @name RWNXAGCACI40MARG1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:24 ACI40MARGMCS7 0x2
* 21:16 ACI40MARGMCS6 0x3
* 13:08 ACI40MARGMCS5 0x3
* 05:00 ACI40MARGMCS4 0x5
* </pre>
*
* @{
*/
/// Address of the RWNXAGCACI40MARG1 register
#define AGC_RWNXAGCACI40MARG1_ADDR 0x0100201C
/// Offset of the RWNXAGCACI40MARG1 register from the base address
#define AGC_RWNXAGCACI40MARG1_OFFSET 0x0000201C
/// Index of the RWNXAGCACI40MARG1 register
#define AGC_RWNXAGCACI40MARG1_INDEX 0x00000807
/// Reset value of the RWNXAGCACI40MARG1 register
#define AGC_RWNXAGCACI40MARG1_RESET 0x02030305
/**
* @brief Returns the current value of the RWNXAGCACI40MARG1 register.
* The RWNXAGCACI40MARG1 register will be read and its value returned.
* @return The current value of the RWNXAGCACI40MARG1 register.
*/
__INLINE uint32_t agc_rwnxagcaci40marg1_get(void)
{
return REG_PL_RD(AGC_RWNXAGCACI40MARG1_ADDR);
}
/**
* @brief Sets the RWNXAGCACI40MARG1 register to a value.
* The RWNXAGCACI40MARG1 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcaci40marg1_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCACI40MARG1_ADDR, value);
}
// field definitions
/// ACI40MARGMCS7 field mask
#define AGC_ACI40MARGMCS7_MASK ((uint32_t)0x3F000000)
/// ACI40MARGMCS7 field LSB position
#define AGC_ACI40MARGMCS7_LSB 24
/// ACI40MARGMCS7 field width
#define AGC_ACI40MARGMCS7_WIDTH ((uint32_t)0x00000006)
/// ACI40MARGMCS6 field mask
#define AGC_ACI40MARGMCS6_MASK ((uint32_t)0x003F0000)
/// ACI40MARGMCS6 field LSB position
#define AGC_ACI40MARGMCS6_LSB 16
/// ACI40MARGMCS6 field width
#define AGC_ACI40MARGMCS6_WIDTH ((uint32_t)0x00000006)
/// ACI40MARGMCS5 field mask
#define AGC_ACI40MARGMCS5_MASK ((uint32_t)0x00003F00)
/// ACI40MARGMCS5 field LSB position
#define AGC_ACI40MARGMCS5_LSB 8
/// ACI40MARGMCS5 field width
#define AGC_ACI40MARGMCS5_WIDTH ((uint32_t)0x00000006)
/// ACI40MARGMCS4 field mask
#define AGC_ACI40MARGMCS4_MASK ((uint32_t)0x0000003F)
/// ACI40MARGMCS4 field LSB position
#define AGC_ACI40MARGMCS4_LSB 0
/// ACI40MARGMCS4 field width
#define AGC_ACI40MARGMCS4_WIDTH ((uint32_t)0x00000006)
/// ACI40MARGMCS7 field reset value
#define AGC_ACI40MARGMCS7_RST 0x2
/// ACI40MARGMCS6 field reset value
#define AGC_ACI40MARGMCS6_RST 0x3
/// ACI40MARGMCS5 field reset value
#define AGC_ACI40MARGMCS5_RST 0x3
/// ACI40MARGMCS4 field reset value
#define AGC_ACI40MARGMCS4_RST 0x5
/**
* @brief Constructs a value for the RWNXAGCACI40MARG1 register given values for its fields
* and writes the value to the register.
*
* @param[in] aci40margmcs7 - The value to use for the ACI40MARGMCS7 field.
* @param[in] aci40margmcs6 - The value to use for the ACI40MARGMCS6 field.
* @param[in] aci40margmcs5 - The value to use for the ACI40MARGMCS5 field.
* @param[in] aci40margmcs4 - The value to use for the ACI40MARGMCS4 field.
*/
__INLINE void agc_rwnxagcaci40marg1_pack(uint8_t aci40margmcs7, uint8_t aci40margmcs6, uint8_t aci40margmcs5, uint8_t aci40margmcs4)
{
ASSERT_ERR((((uint32_t)aci40margmcs7 << 24) & ~((uint32_t)0x3F000000)) == 0);
ASSERT_ERR((((uint32_t)aci40margmcs6 << 16) & ~((uint32_t)0x003F0000)) == 0);
ASSERT_ERR((((uint32_t)aci40margmcs5 << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)aci40margmcs4 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG1_ADDR, ((uint32_t)aci40margmcs7 << 24) | ((uint32_t)aci40margmcs6 << 16) | ((uint32_t)aci40margmcs5 << 8) | ((uint32_t)aci40margmcs4 << 0));
}
/**
* @brief Unpacks RWNXAGCACI40MARG1's fields from current value of the RWNXAGCACI40MARG1 register.
*
* Reads the RWNXAGCACI40MARG1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] aci40margmcs7 - Will be populated with the current value of this field from the register.
* @param[out] aci40margmcs6 - Will be populated with the current value of this field from the register.
* @param[out] aci40margmcs5 - Will be populated with the current value of this field from the register.
* @param[out] aci40margmcs4 - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcaci40marg1_unpack(uint8_t *aci40margmcs7, uint8_t *aci40margmcs6, uint8_t *aci40margmcs5, uint8_t *aci40margmcs4)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG1_ADDR);
*aci40margmcs7 = (localVal & ((uint32_t)0x3F000000)) >> 24;
*aci40margmcs6 = (localVal & ((uint32_t)0x003F0000)) >> 16;
*aci40margmcs5 = (localVal & ((uint32_t)0x00003F00)) >> 8;
*aci40margmcs4 = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the ACI40MARGMCS7 field in the RWNXAGCACI40MARG1 register.
*
* The RWNXAGCACI40MARG1 register will be read and the ACI40MARGMCS7 field's value will be returned.
*
* @return The current value of the ACI40MARGMCS7 field in the RWNXAGCACI40MARG1 register.
*/
__INLINE uint8_t agc_aci40margmcs7_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG1_ADDR);
return ((localVal & ((uint32_t)0x3F000000)) >> 24);
}
/**
* @brief Sets the ACI40MARGMCS7 field of the RWNXAGCACI40MARG1 register.
*
* The RWNXAGCACI40MARG1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci40margmcs7 - The value to set the field to.
*/
__INLINE void agc_aci40margmcs7_setf(uint8_t aci40margmcs7)
{
ASSERT_ERR((((uint32_t)aci40margmcs7 << 24) & ~((uint32_t)0x3F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG1_ADDR, (REG_PL_RD(AGC_RWNXAGCACI40MARG1_ADDR) & ~((uint32_t)0x3F000000)) | ((uint32_t)aci40margmcs7 << 24));
}
/**
* @brief Returns the current value of the ACI40MARGMCS6 field in the RWNXAGCACI40MARG1 register.
*
* The RWNXAGCACI40MARG1 register will be read and the ACI40MARGMCS6 field's value will be returned.
*
* @return The current value of the ACI40MARGMCS6 field in the RWNXAGCACI40MARG1 register.
*/
__INLINE uint8_t agc_aci40margmcs6_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG1_ADDR);
return ((localVal & ((uint32_t)0x003F0000)) >> 16);
}
/**
* @brief Sets the ACI40MARGMCS6 field of the RWNXAGCACI40MARG1 register.
*
* The RWNXAGCACI40MARG1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci40margmcs6 - The value to set the field to.
*/
__INLINE void agc_aci40margmcs6_setf(uint8_t aci40margmcs6)
{
ASSERT_ERR((((uint32_t)aci40margmcs6 << 16) & ~((uint32_t)0x003F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG1_ADDR, (REG_PL_RD(AGC_RWNXAGCACI40MARG1_ADDR) & ~((uint32_t)0x003F0000)) | ((uint32_t)aci40margmcs6 << 16));
}
/**
* @brief Returns the current value of the ACI40MARGMCS5 field in the RWNXAGCACI40MARG1 register.
*
* The RWNXAGCACI40MARG1 register will be read and the ACI40MARGMCS5 field's value will be returned.
*
* @return The current value of the ACI40MARGMCS5 field in the RWNXAGCACI40MARG1 register.
*/
__INLINE uint8_t agc_aci40margmcs5_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG1_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the ACI40MARGMCS5 field of the RWNXAGCACI40MARG1 register.
*
* The RWNXAGCACI40MARG1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci40margmcs5 - The value to set the field to.
*/
__INLINE void agc_aci40margmcs5_setf(uint8_t aci40margmcs5)
{
ASSERT_ERR((((uint32_t)aci40margmcs5 << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG1_ADDR, (REG_PL_RD(AGC_RWNXAGCACI40MARG1_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)aci40margmcs5 << 8));
}
/**
* @brief Returns the current value of the ACI40MARGMCS4 field in the RWNXAGCACI40MARG1 register.
*
* The RWNXAGCACI40MARG1 register will be read and the ACI40MARGMCS4 field's value will be returned.
*
* @return The current value of the ACI40MARGMCS4 field in the RWNXAGCACI40MARG1 register.
*/
__INLINE uint8_t agc_aci40margmcs4_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG1_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the ACI40MARGMCS4 field of the RWNXAGCACI40MARG1 register.
*
* The RWNXAGCACI40MARG1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci40margmcs4 - The value to set the field to.
*/
__INLINE void agc_aci40margmcs4_setf(uint8_t aci40margmcs4)
{
ASSERT_ERR((((uint32_t)aci40margmcs4 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG1_ADDR, (REG_PL_RD(AGC_RWNXAGCACI40MARG1_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)aci40margmcs4 << 0));
}
/// @}
/**
* @name RWNXAGCACI40MARG2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 13:08 ACI40MARGMCS9 0x1
* 05:00 ACI40MARGMCS8 0x1
* </pre>
*
* @{
*/
/// Address of the RWNXAGCACI40MARG2 register
#define AGC_RWNXAGCACI40MARG2_ADDR 0x01002020
/// Offset of the RWNXAGCACI40MARG2 register from the base address
#define AGC_RWNXAGCACI40MARG2_OFFSET 0x00002020
/// Index of the RWNXAGCACI40MARG2 register
#define AGC_RWNXAGCACI40MARG2_INDEX 0x00000808
/// Reset value of the RWNXAGCACI40MARG2 register
#define AGC_RWNXAGCACI40MARG2_RESET 0x00000101
/**
* @brief Returns the current value of the RWNXAGCACI40MARG2 register.
* The RWNXAGCACI40MARG2 register will be read and its value returned.
* @return The current value of the RWNXAGCACI40MARG2 register.
*/
__INLINE uint32_t agc_rwnxagcaci40marg2_get(void)
{
return REG_PL_RD(AGC_RWNXAGCACI40MARG2_ADDR);
}
/**
* @brief Sets the RWNXAGCACI40MARG2 register to a value.
* The RWNXAGCACI40MARG2 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcaci40marg2_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCACI40MARG2_ADDR, value);
}
// field definitions
/// ACI40MARGMCS9 field mask
#define AGC_ACI40MARGMCS9_MASK ((uint32_t)0x00003F00)
/// ACI40MARGMCS9 field LSB position
#define AGC_ACI40MARGMCS9_LSB 8
/// ACI40MARGMCS9 field width
#define AGC_ACI40MARGMCS9_WIDTH ((uint32_t)0x00000006)
/// ACI40MARGMCS8 field mask
#define AGC_ACI40MARGMCS8_MASK ((uint32_t)0x0000003F)
/// ACI40MARGMCS8 field LSB position
#define AGC_ACI40MARGMCS8_LSB 0
/// ACI40MARGMCS8 field width
#define AGC_ACI40MARGMCS8_WIDTH ((uint32_t)0x00000006)
/// ACI40MARGMCS9 field reset value
#define AGC_ACI40MARGMCS9_RST 0x1
/// ACI40MARGMCS8 field reset value
#define AGC_ACI40MARGMCS8_RST 0x1
/**
* @brief Constructs a value for the RWNXAGCACI40MARG2 register given values for its fields
* and writes the value to the register.
*
* @param[in] aci40margmcs9 - The value to use for the ACI40MARGMCS9 field.
* @param[in] aci40margmcs8 - The value to use for the ACI40MARGMCS8 field.
*/
__INLINE void agc_rwnxagcaci40marg2_pack(uint8_t aci40margmcs9, uint8_t aci40margmcs8)
{
ASSERT_ERR((((uint32_t)aci40margmcs9 << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)aci40margmcs8 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG2_ADDR, ((uint32_t)aci40margmcs9 << 8) | ((uint32_t)aci40margmcs8 << 0));
}
/**
* @brief Unpacks RWNXAGCACI40MARG2's fields from current value of the RWNXAGCACI40MARG2 register.
*
* Reads the RWNXAGCACI40MARG2 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] aci40margmcs9 - Will be populated with the current value of this field from the register.
* @param[out] aci40margmcs8 - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcaci40marg2_unpack(uint8_t *aci40margmcs9, uint8_t *aci40margmcs8)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG2_ADDR);
*aci40margmcs9 = (localVal & ((uint32_t)0x00003F00)) >> 8;
*aci40margmcs8 = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the ACI40MARGMCS9 field in the RWNXAGCACI40MARG2 register.
*
* The RWNXAGCACI40MARG2 register will be read and the ACI40MARGMCS9 field's value will be returned.
*
* @return The current value of the ACI40MARGMCS9 field in the RWNXAGCACI40MARG2 register.
*/
__INLINE uint8_t agc_aci40margmcs9_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG2_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the ACI40MARGMCS9 field of the RWNXAGCACI40MARG2 register.
*
* The RWNXAGCACI40MARG2 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci40margmcs9 - The value to set the field to.
*/
__INLINE void agc_aci40margmcs9_setf(uint8_t aci40margmcs9)
{
ASSERT_ERR((((uint32_t)aci40margmcs9 << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG2_ADDR, (REG_PL_RD(AGC_RWNXAGCACI40MARG2_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)aci40margmcs9 << 8));
}
/**
* @brief Returns the current value of the ACI40MARGMCS8 field in the RWNXAGCACI40MARG2 register.
*
* The RWNXAGCACI40MARG2 register will be read and the ACI40MARGMCS8 field's value will be returned.
*
* @return The current value of the ACI40MARGMCS8 field in the RWNXAGCACI40MARG2 register.
*/
__INLINE uint8_t agc_aci40margmcs8_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI40MARG2_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the ACI40MARGMCS8 field of the RWNXAGCACI40MARG2 register.
*
* The RWNXAGCACI40MARG2 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci40margmcs8 - The value to set the field to.
*/
__INLINE void agc_aci40margmcs8_setf(uint8_t aci40margmcs8)
{
ASSERT_ERR((((uint32_t)aci40margmcs8 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI40MARG2_ADDR, (REG_PL_RD(AGC_RWNXAGCACI40MARG2_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)aci40margmcs8 << 0));
}
/// @}
/**
* @name RWNXAGCACI80MARG0 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:24 ACI80MARGMCS3 0x18
* 21:16 ACI80MARGMCS2 0x1B
* 13:08 ACI80MARGMCS1 0x1D
* 05:00 ACI80MARGMCS0 0x20
* </pre>
*
* @{
*/
/// Address of the RWNXAGCACI80MARG0 register
#define AGC_RWNXAGCACI80MARG0_ADDR 0x01002024
/// Offset of the RWNXAGCACI80MARG0 register from the base address
#define AGC_RWNXAGCACI80MARG0_OFFSET 0x00002024
/// Index of the RWNXAGCACI80MARG0 register
#define AGC_RWNXAGCACI80MARG0_INDEX 0x00000809
/// Reset value of the RWNXAGCACI80MARG0 register
#define AGC_RWNXAGCACI80MARG0_RESET 0x181B1D20
/**
* @brief Returns the current value of the RWNXAGCACI80MARG0 register.
* The RWNXAGCACI80MARG0 register will be read and its value returned.
* @return The current value of the RWNXAGCACI80MARG0 register.
*/
__INLINE uint32_t agc_rwnxagcaci80marg0_get(void)
{
return REG_PL_RD(AGC_RWNXAGCACI80MARG0_ADDR);
}
/**
* @brief Sets the RWNXAGCACI80MARG0 register to a value.
* The RWNXAGCACI80MARG0 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcaci80marg0_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCACI80MARG0_ADDR, value);
}
// field definitions
/// ACI80MARGMCS3 field mask
#define AGC_ACI80MARGMCS3_MASK ((uint32_t)0x3F000000)
/// ACI80MARGMCS3 field LSB position
#define AGC_ACI80MARGMCS3_LSB 24
/// ACI80MARGMCS3 field width
#define AGC_ACI80MARGMCS3_WIDTH ((uint32_t)0x00000006)
/// ACI80MARGMCS2 field mask
#define AGC_ACI80MARGMCS2_MASK ((uint32_t)0x003F0000)
/// ACI80MARGMCS2 field LSB position
#define AGC_ACI80MARGMCS2_LSB 16
/// ACI80MARGMCS2 field width
#define AGC_ACI80MARGMCS2_WIDTH ((uint32_t)0x00000006)
/// ACI80MARGMCS1 field mask
#define AGC_ACI80MARGMCS1_MASK ((uint32_t)0x00003F00)
/// ACI80MARGMCS1 field LSB position
#define AGC_ACI80MARGMCS1_LSB 8
/// ACI80MARGMCS1 field width
#define AGC_ACI80MARGMCS1_WIDTH ((uint32_t)0x00000006)
/// ACI80MARGMCS0 field mask
#define AGC_ACI80MARGMCS0_MASK ((uint32_t)0x0000003F)
/// ACI80MARGMCS0 field LSB position
#define AGC_ACI80MARGMCS0_LSB 0
/// ACI80MARGMCS0 field width
#define AGC_ACI80MARGMCS0_WIDTH ((uint32_t)0x00000006)
/// ACI80MARGMCS3 field reset value
#define AGC_ACI80MARGMCS3_RST 0x18
/// ACI80MARGMCS2 field reset value
#define AGC_ACI80MARGMCS2_RST 0x1B
/// ACI80MARGMCS1 field reset value
#define AGC_ACI80MARGMCS1_RST 0x1D
/// ACI80MARGMCS0 field reset value
#define AGC_ACI80MARGMCS0_RST 0x20
/**
* @brief Constructs a value for the RWNXAGCACI80MARG0 register given values for its fields
* and writes the value to the register.
*
* @param[in] aci80margmcs3 - The value to use for the ACI80MARGMCS3 field.
* @param[in] aci80margmcs2 - The value to use for the ACI80MARGMCS2 field.
* @param[in] aci80margmcs1 - The value to use for the ACI80MARGMCS1 field.
* @param[in] aci80margmcs0 - The value to use for the ACI80MARGMCS0 field.
*/
__INLINE void agc_rwnxagcaci80marg0_pack(uint8_t aci80margmcs3, uint8_t aci80margmcs2, uint8_t aci80margmcs1, uint8_t aci80margmcs0)
{
ASSERT_ERR((((uint32_t)aci80margmcs3 << 24) & ~((uint32_t)0x3F000000)) == 0);
ASSERT_ERR((((uint32_t)aci80margmcs2 << 16) & ~((uint32_t)0x003F0000)) == 0);
ASSERT_ERR((((uint32_t)aci80margmcs1 << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)aci80margmcs0 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG0_ADDR, ((uint32_t)aci80margmcs3 << 24) | ((uint32_t)aci80margmcs2 << 16) | ((uint32_t)aci80margmcs1 << 8) | ((uint32_t)aci80margmcs0 << 0));
}
/**
* @brief Unpacks RWNXAGCACI80MARG0's fields from current value of the RWNXAGCACI80MARG0 register.
*
* Reads the RWNXAGCACI80MARG0 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] aci80margmcs3 - Will be populated with the current value of this field from the register.
* @param[out] aci80margmcs2 - Will be populated with the current value of this field from the register.
* @param[out] aci80margmcs1 - Will be populated with the current value of this field from the register.
* @param[out] aci80margmcs0 - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcaci80marg0_unpack(uint8_t *aci80margmcs3, uint8_t *aci80margmcs2, uint8_t *aci80margmcs1, uint8_t *aci80margmcs0)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG0_ADDR);
*aci80margmcs3 = (localVal & ((uint32_t)0x3F000000)) >> 24;
*aci80margmcs2 = (localVal & ((uint32_t)0x003F0000)) >> 16;
*aci80margmcs1 = (localVal & ((uint32_t)0x00003F00)) >> 8;
*aci80margmcs0 = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the ACI80MARGMCS3 field in the RWNXAGCACI80MARG0 register.
*
* The RWNXAGCACI80MARG0 register will be read and the ACI80MARGMCS3 field's value will be returned.
*
* @return The current value of the ACI80MARGMCS3 field in the RWNXAGCACI80MARG0 register.
*/
__INLINE uint8_t agc_aci80margmcs3_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG0_ADDR);
return ((localVal & ((uint32_t)0x3F000000)) >> 24);
}
/**
* @brief Sets the ACI80MARGMCS3 field of the RWNXAGCACI80MARG0 register.
*
* The RWNXAGCACI80MARG0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci80margmcs3 - The value to set the field to.
*/
__INLINE void agc_aci80margmcs3_setf(uint8_t aci80margmcs3)
{
ASSERT_ERR((((uint32_t)aci80margmcs3 << 24) & ~((uint32_t)0x3F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG0_ADDR, (REG_PL_RD(AGC_RWNXAGCACI80MARG0_ADDR) & ~((uint32_t)0x3F000000)) | ((uint32_t)aci80margmcs3 << 24));
}
/**
* @brief Returns the current value of the ACI80MARGMCS2 field in the RWNXAGCACI80MARG0 register.
*
* The RWNXAGCACI80MARG0 register will be read and the ACI80MARGMCS2 field's value will be returned.
*
* @return The current value of the ACI80MARGMCS2 field in the RWNXAGCACI80MARG0 register.
*/
__INLINE uint8_t agc_aci80margmcs2_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG0_ADDR);
return ((localVal & ((uint32_t)0x003F0000)) >> 16);
}
/**
* @brief Sets the ACI80MARGMCS2 field of the RWNXAGCACI80MARG0 register.
*
* The RWNXAGCACI80MARG0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci80margmcs2 - The value to set the field to.
*/
__INLINE void agc_aci80margmcs2_setf(uint8_t aci80margmcs2)
{
ASSERT_ERR((((uint32_t)aci80margmcs2 << 16) & ~((uint32_t)0x003F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG0_ADDR, (REG_PL_RD(AGC_RWNXAGCACI80MARG0_ADDR) & ~((uint32_t)0x003F0000)) | ((uint32_t)aci80margmcs2 << 16));
}
/**
* @brief Returns the current value of the ACI80MARGMCS1 field in the RWNXAGCACI80MARG0 register.
*
* The RWNXAGCACI80MARG0 register will be read and the ACI80MARGMCS1 field's value will be returned.
*
* @return The current value of the ACI80MARGMCS1 field in the RWNXAGCACI80MARG0 register.
*/
__INLINE uint8_t agc_aci80margmcs1_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG0_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the ACI80MARGMCS1 field of the RWNXAGCACI80MARG0 register.
*
* The RWNXAGCACI80MARG0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci80margmcs1 - The value to set the field to.
*/
__INLINE void agc_aci80margmcs1_setf(uint8_t aci80margmcs1)
{
ASSERT_ERR((((uint32_t)aci80margmcs1 << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG0_ADDR, (REG_PL_RD(AGC_RWNXAGCACI80MARG0_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)aci80margmcs1 << 8));
}
/**
* @brief Returns the current value of the ACI80MARGMCS0 field in the RWNXAGCACI80MARG0 register.
*
* The RWNXAGCACI80MARG0 register will be read and the ACI80MARGMCS0 field's value will be returned.
*
* @return The current value of the ACI80MARGMCS0 field in the RWNXAGCACI80MARG0 register.
*/
__INLINE uint8_t agc_aci80margmcs0_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG0_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the ACI80MARGMCS0 field of the RWNXAGCACI80MARG0 register.
*
* The RWNXAGCACI80MARG0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci80margmcs0 - The value to set the field to.
*/
__INLINE void agc_aci80margmcs0_setf(uint8_t aci80margmcs0)
{
ASSERT_ERR((((uint32_t)aci80margmcs0 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG0_ADDR, (REG_PL_RD(AGC_RWNXAGCACI80MARG0_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)aci80margmcs0 << 0));
}
/// @}
/**
* @name RWNXAGCACI80MARG1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:24 ACI80MARGMCS7 0xE
* 21:16 ACI80MARGMCS6 0xF
* 13:08 ACI80MARGMCS5 0x10
* 05:00 ACI80MARGMCS4 0x14
* </pre>
*
* @{
*/
/// Address of the RWNXAGCACI80MARG1 register
#define AGC_RWNXAGCACI80MARG1_ADDR 0x01002028
/// Offset of the RWNXAGCACI80MARG1 register from the base address
#define AGC_RWNXAGCACI80MARG1_OFFSET 0x00002028
/// Index of the RWNXAGCACI80MARG1 register
#define AGC_RWNXAGCACI80MARG1_INDEX 0x0000080A
/// Reset value of the RWNXAGCACI80MARG1 register
#define AGC_RWNXAGCACI80MARG1_RESET 0x0E0F1014
/**
* @brief Returns the current value of the RWNXAGCACI80MARG1 register.
* The RWNXAGCACI80MARG1 register will be read and its value returned.
* @return The current value of the RWNXAGCACI80MARG1 register.
*/
__INLINE uint32_t agc_rwnxagcaci80marg1_get(void)
{
return REG_PL_RD(AGC_RWNXAGCACI80MARG1_ADDR);
}
/**
* @brief Sets the RWNXAGCACI80MARG1 register to a value.
* The RWNXAGCACI80MARG1 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcaci80marg1_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCACI80MARG1_ADDR, value);
}
// field definitions
/// ACI80MARGMCS7 field mask
#define AGC_ACI80MARGMCS7_MASK ((uint32_t)0x3F000000)
/// ACI80MARGMCS7 field LSB position
#define AGC_ACI80MARGMCS7_LSB 24
/// ACI80MARGMCS7 field width
#define AGC_ACI80MARGMCS7_WIDTH ((uint32_t)0x00000006)
/// ACI80MARGMCS6 field mask
#define AGC_ACI80MARGMCS6_MASK ((uint32_t)0x003F0000)
/// ACI80MARGMCS6 field LSB position
#define AGC_ACI80MARGMCS6_LSB 16
/// ACI80MARGMCS6 field width
#define AGC_ACI80MARGMCS6_WIDTH ((uint32_t)0x00000006)
/// ACI80MARGMCS5 field mask
#define AGC_ACI80MARGMCS5_MASK ((uint32_t)0x00003F00)
/// ACI80MARGMCS5 field LSB position
#define AGC_ACI80MARGMCS5_LSB 8
/// ACI80MARGMCS5 field width
#define AGC_ACI80MARGMCS5_WIDTH ((uint32_t)0x00000006)
/// ACI80MARGMCS4 field mask
#define AGC_ACI80MARGMCS4_MASK ((uint32_t)0x0000003F)
/// ACI80MARGMCS4 field LSB position
#define AGC_ACI80MARGMCS4_LSB 0
/// ACI80MARGMCS4 field width
#define AGC_ACI80MARGMCS4_WIDTH ((uint32_t)0x00000006)
/// ACI80MARGMCS7 field reset value
#define AGC_ACI80MARGMCS7_RST 0xE
/// ACI80MARGMCS6 field reset value
#define AGC_ACI80MARGMCS6_RST 0xF
/// ACI80MARGMCS5 field reset value
#define AGC_ACI80MARGMCS5_RST 0x10
/// ACI80MARGMCS4 field reset value
#define AGC_ACI80MARGMCS4_RST 0x14
/**
* @brief Constructs a value for the RWNXAGCACI80MARG1 register given values for its fields
* and writes the value to the register.
*
* @param[in] aci80margmcs7 - The value to use for the ACI80MARGMCS7 field.
* @param[in] aci80margmcs6 - The value to use for the ACI80MARGMCS6 field.
* @param[in] aci80margmcs5 - The value to use for the ACI80MARGMCS5 field.
* @param[in] aci80margmcs4 - The value to use for the ACI80MARGMCS4 field.
*/
__INLINE void agc_rwnxagcaci80marg1_pack(uint8_t aci80margmcs7, uint8_t aci80margmcs6, uint8_t aci80margmcs5, uint8_t aci80margmcs4)
{
ASSERT_ERR((((uint32_t)aci80margmcs7 << 24) & ~((uint32_t)0x3F000000)) == 0);
ASSERT_ERR((((uint32_t)aci80margmcs6 << 16) & ~((uint32_t)0x003F0000)) == 0);
ASSERT_ERR((((uint32_t)aci80margmcs5 << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)aci80margmcs4 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG1_ADDR, ((uint32_t)aci80margmcs7 << 24) | ((uint32_t)aci80margmcs6 << 16) | ((uint32_t)aci80margmcs5 << 8) | ((uint32_t)aci80margmcs4 << 0));
}
/**
* @brief Unpacks RWNXAGCACI80MARG1's fields from current value of the RWNXAGCACI80MARG1 register.
*
* Reads the RWNXAGCACI80MARG1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] aci80margmcs7 - Will be populated with the current value of this field from the register.
* @param[out] aci80margmcs6 - Will be populated with the current value of this field from the register.
* @param[out] aci80margmcs5 - Will be populated with the current value of this field from the register.
* @param[out] aci80margmcs4 - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcaci80marg1_unpack(uint8_t *aci80margmcs7, uint8_t *aci80margmcs6, uint8_t *aci80margmcs5, uint8_t *aci80margmcs4)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG1_ADDR);
*aci80margmcs7 = (localVal & ((uint32_t)0x3F000000)) >> 24;
*aci80margmcs6 = (localVal & ((uint32_t)0x003F0000)) >> 16;
*aci80margmcs5 = (localVal & ((uint32_t)0x00003F00)) >> 8;
*aci80margmcs4 = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the ACI80MARGMCS7 field in the RWNXAGCACI80MARG1 register.
*
* The RWNXAGCACI80MARG1 register will be read and the ACI80MARGMCS7 field's value will be returned.
*
* @return The current value of the ACI80MARGMCS7 field in the RWNXAGCACI80MARG1 register.
*/
__INLINE uint8_t agc_aci80margmcs7_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG1_ADDR);
return ((localVal & ((uint32_t)0x3F000000)) >> 24);
}
/**
* @brief Sets the ACI80MARGMCS7 field of the RWNXAGCACI80MARG1 register.
*
* The RWNXAGCACI80MARG1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci80margmcs7 - The value to set the field to.
*/
__INLINE void agc_aci80margmcs7_setf(uint8_t aci80margmcs7)
{
ASSERT_ERR((((uint32_t)aci80margmcs7 << 24) & ~((uint32_t)0x3F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG1_ADDR, (REG_PL_RD(AGC_RWNXAGCACI80MARG1_ADDR) & ~((uint32_t)0x3F000000)) | ((uint32_t)aci80margmcs7 << 24));
}
/**
* @brief Returns the current value of the ACI80MARGMCS6 field in the RWNXAGCACI80MARG1 register.
*
* The RWNXAGCACI80MARG1 register will be read and the ACI80MARGMCS6 field's value will be returned.
*
* @return The current value of the ACI80MARGMCS6 field in the RWNXAGCACI80MARG1 register.
*/
__INLINE uint8_t agc_aci80margmcs6_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG1_ADDR);
return ((localVal & ((uint32_t)0x003F0000)) >> 16);
}
/**
* @brief Sets the ACI80MARGMCS6 field of the RWNXAGCACI80MARG1 register.
*
* The RWNXAGCACI80MARG1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci80margmcs6 - The value to set the field to.
*/
__INLINE void agc_aci80margmcs6_setf(uint8_t aci80margmcs6)
{
ASSERT_ERR((((uint32_t)aci80margmcs6 << 16) & ~((uint32_t)0x003F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG1_ADDR, (REG_PL_RD(AGC_RWNXAGCACI80MARG1_ADDR) & ~((uint32_t)0x003F0000)) | ((uint32_t)aci80margmcs6 << 16));
}
/**
* @brief Returns the current value of the ACI80MARGMCS5 field in the RWNXAGCACI80MARG1 register.
*
* The RWNXAGCACI80MARG1 register will be read and the ACI80MARGMCS5 field's value will be returned.
*
* @return The current value of the ACI80MARGMCS5 field in the RWNXAGCACI80MARG1 register.
*/
__INLINE uint8_t agc_aci80margmcs5_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG1_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the ACI80MARGMCS5 field of the RWNXAGCACI80MARG1 register.
*
* The RWNXAGCACI80MARG1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci80margmcs5 - The value to set the field to.
*/
__INLINE void agc_aci80margmcs5_setf(uint8_t aci80margmcs5)
{
ASSERT_ERR((((uint32_t)aci80margmcs5 << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG1_ADDR, (REG_PL_RD(AGC_RWNXAGCACI80MARG1_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)aci80margmcs5 << 8));
}
/**
* @brief Returns the current value of the ACI80MARGMCS4 field in the RWNXAGCACI80MARG1 register.
*
* The RWNXAGCACI80MARG1 register will be read and the ACI80MARGMCS4 field's value will be returned.
*
* @return The current value of the ACI80MARGMCS4 field in the RWNXAGCACI80MARG1 register.
*/
__INLINE uint8_t agc_aci80margmcs4_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG1_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the ACI80MARGMCS4 field of the RWNXAGCACI80MARG1 register.
*
* The RWNXAGCACI80MARG1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci80margmcs4 - The value to set the field to.
*/
__INLINE void agc_aci80margmcs4_setf(uint8_t aci80margmcs4)
{
ASSERT_ERR((((uint32_t)aci80margmcs4 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG1_ADDR, (REG_PL_RD(AGC_RWNXAGCACI80MARG1_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)aci80margmcs4 << 0));
}
/// @}
/**
* @name RWNXAGCACI80MARG2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 13:08 ACI80MARGMCS9 0x8
* 05:00 ACI80MARGMCS8 0xA
* </pre>
*
* @{
*/
/// Address of the RWNXAGCACI80MARG2 register
#define AGC_RWNXAGCACI80MARG2_ADDR 0x0100202C
/// Offset of the RWNXAGCACI80MARG2 register from the base address
#define AGC_RWNXAGCACI80MARG2_OFFSET 0x0000202C
/// Index of the RWNXAGCACI80MARG2 register
#define AGC_RWNXAGCACI80MARG2_INDEX 0x0000080B
/// Reset value of the RWNXAGCACI80MARG2 register
#define AGC_RWNXAGCACI80MARG2_RESET 0x0000080A
/**
* @brief Returns the current value of the RWNXAGCACI80MARG2 register.
* The RWNXAGCACI80MARG2 register will be read and its value returned.
* @return The current value of the RWNXAGCACI80MARG2 register.
*/
__INLINE uint32_t agc_rwnxagcaci80marg2_get(void)
{
return REG_PL_RD(AGC_RWNXAGCACI80MARG2_ADDR);
}
/**
* @brief Sets the RWNXAGCACI80MARG2 register to a value.
* The RWNXAGCACI80MARG2 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcaci80marg2_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCACI80MARG2_ADDR, value);
}
// field definitions
/// ACI80MARGMCS9 field mask
#define AGC_ACI80MARGMCS9_MASK ((uint32_t)0x00003F00)
/// ACI80MARGMCS9 field LSB position
#define AGC_ACI80MARGMCS9_LSB 8
/// ACI80MARGMCS9 field width
#define AGC_ACI80MARGMCS9_WIDTH ((uint32_t)0x00000006)
/// ACI80MARGMCS8 field mask
#define AGC_ACI80MARGMCS8_MASK ((uint32_t)0x0000003F)
/// ACI80MARGMCS8 field LSB position
#define AGC_ACI80MARGMCS8_LSB 0
/// ACI80MARGMCS8 field width
#define AGC_ACI80MARGMCS8_WIDTH ((uint32_t)0x00000006)
/// ACI80MARGMCS9 field reset value
#define AGC_ACI80MARGMCS9_RST 0x8
/// ACI80MARGMCS8 field reset value
#define AGC_ACI80MARGMCS8_RST 0xA
/**
* @brief Constructs a value for the RWNXAGCACI80MARG2 register given values for its fields
* and writes the value to the register.
*
* @param[in] aci80margmcs9 - The value to use for the ACI80MARGMCS9 field.
* @param[in] aci80margmcs8 - The value to use for the ACI80MARGMCS8 field.
*/
__INLINE void agc_rwnxagcaci80marg2_pack(uint8_t aci80margmcs9, uint8_t aci80margmcs8)
{
ASSERT_ERR((((uint32_t)aci80margmcs9 << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)aci80margmcs8 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG2_ADDR, ((uint32_t)aci80margmcs9 << 8) | ((uint32_t)aci80margmcs8 << 0));
}
/**
* @brief Unpacks RWNXAGCACI80MARG2's fields from current value of the RWNXAGCACI80MARG2 register.
*
* Reads the RWNXAGCACI80MARG2 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] aci80margmcs9 - Will be populated with the current value of this field from the register.
* @param[out] aci80margmcs8 - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcaci80marg2_unpack(uint8_t *aci80margmcs9, uint8_t *aci80margmcs8)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG2_ADDR);
*aci80margmcs9 = (localVal & ((uint32_t)0x00003F00)) >> 8;
*aci80margmcs8 = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the ACI80MARGMCS9 field in the RWNXAGCACI80MARG2 register.
*
* The RWNXAGCACI80MARG2 register will be read and the ACI80MARGMCS9 field's value will be returned.
*
* @return The current value of the ACI80MARGMCS9 field in the RWNXAGCACI80MARG2 register.
*/
__INLINE uint8_t agc_aci80margmcs9_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG2_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the ACI80MARGMCS9 field of the RWNXAGCACI80MARG2 register.
*
* The RWNXAGCACI80MARG2 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci80margmcs9 - The value to set the field to.
*/
__INLINE void agc_aci80margmcs9_setf(uint8_t aci80margmcs9)
{
ASSERT_ERR((((uint32_t)aci80margmcs9 << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG2_ADDR, (REG_PL_RD(AGC_RWNXAGCACI80MARG2_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)aci80margmcs9 << 8));
}
/**
* @brief Returns the current value of the ACI80MARGMCS8 field in the RWNXAGCACI80MARG2 register.
*
* The RWNXAGCACI80MARG2 register will be read and the ACI80MARGMCS8 field's value will be returned.
*
* @return The current value of the ACI80MARGMCS8 field in the RWNXAGCACI80MARG2 register.
*/
__INLINE uint8_t agc_aci80margmcs8_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCACI80MARG2_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the ACI80MARGMCS8 field of the RWNXAGCACI80MARG2 register.
*
* The RWNXAGCACI80MARG2 register will be read, modified to contain the new field value, and written.
*
* @param[in] aci80margmcs8 - The value to set the field to.
*/
__INLINE void agc_aci80margmcs8_setf(uint8_t aci80margmcs8)
{
ASSERT_ERR((((uint32_t)aci80margmcs8 << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCACI80MARG2_ADDR, (REG_PL_RD(AGC_RWNXAGCACI80MARG2_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)aci80margmcs8 << 0));
}
/// @}
/**
* @name RWNXAGCCGH register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 28:24 CHGVGAPSTHR 0x1
* 20:16 CHGVGAPLTHR 0x5
* 12:08 CHGVGANSTHR 0x1
* 04:00 CHGVGANLTHR 0x5
* </pre>
*
* @{
*/
/// Address of the RWNXAGCCGH register
#define AGC_RWNXAGCCGH_ADDR 0x01002030
/// Offset of the RWNXAGCCGH register from the base address
#define AGC_RWNXAGCCGH_OFFSET 0x00002030
/// Index of the RWNXAGCCGH register
#define AGC_RWNXAGCCGH_INDEX 0x0000080C
/// Reset value of the RWNXAGCCGH register
#define AGC_RWNXAGCCGH_RESET 0x01050105
/**
* @brief Returns the current value of the RWNXAGCCGH register.
* The RWNXAGCCGH register will be read and its value returned.
* @return The current value of the RWNXAGCCGH register.
*/
__INLINE uint32_t agc_rwnxagccgh_get(void)
{
return REG_PL_RD(AGC_RWNXAGCCGH_ADDR);
}
/**
* @brief Sets the RWNXAGCCGH register to a value.
* The RWNXAGCCGH register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagccgh_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCCGH_ADDR, value);
}
// field definitions
/// CHGVGAPSTHR field mask
#define AGC_CHGVGAPSTHR_MASK ((uint32_t)0x1F000000)
/// CHGVGAPSTHR field LSB position
#define AGC_CHGVGAPSTHR_LSB 24
/// CHGVGAPSTHR field width
#define AGC_CHGVGAPSTHR_WIDTH ((uint32_t)0x00000005)
/// CHGVGAPLTHR field mask
#define AGC_CHGVGAPLTHR_MASK ((uint32_t)0x001F0000)
/// CHGVGAPLTHR field LSB position
#define AGC_CHGVGAPLTHR_LSB 16
/// CHGVGAPLTHR field width
#define AGC_CHGVGAPLTHR_WIDTH ((uint32_t)0x00000005)
/// CHGVGANSTHR field mask
#define AGC_CHGVGANSTHR_MASK ((uint32_t)0x00001F00)
/// CHGVGANSTHR field LSB position
#define AGC_CHGVGANSTHR_LSB 8
/// CHGVGANSTHR field width
#define AGC_CHGVGANSTHR_WIDTH ((uint32_t)0x00000005)
/// CHGVGANLTHR field mask
#define AGC_CHGVGANLTHR_MASK ((uint32_t)0x0000001F)
/// CHGVGANLTHR field LSB position
#define AGC_CHGVGANLTHR_LSB 0
/// CHGVGANLTHR field width
#define AGC_CHGVGANLTHR_WIDTH ((uint32_t)0x00000005)
/// CHGVGAPSTHR field reset value
#define AGC_CHGVGAPSTHR_RST 0x1
/// CHGVGAPLTHR field reset value
#define AGC_CHGVGAPLTHR_RST 0x5
/// CHGVGANSTHR field reset value
#define AGC_CHGVGANSTHR_RST 0x1
/// CHGVGANLTHR field reset value
#define AGC_CHGVGANLTHR_RST 0x5
/**
* @brief Constructs a value for the RWNXAGCCGH register given values for its fields
* and writes the value to the register.
*
* @param[in] chgvgapsthr - The value to use for the CHGVGAPSTHR field.
* @param[in] chgvgaplthr - The value to use for the CHGVGAPLTHR field.
* @param[in] chgvgansthr - The value to use for the CHGVGANSTHR field.
* @param[in] chgvganlthr - The value to use for the CHGVGANLTHR field.
*/
__INLINE void agc_rwnxagccgh_pack(uint8_t chgvgapsthr, uint8_t chgvgaplthr, uint8_t chgvgansthr, uint8_t chgvganlthr)
{
ASSERT_ERR((((uint32_t)chgvgapsthr << 24) & ~((uint32_t)0x1F000000)) == 0);
ASSERT_ERR((((uint32_t)chgvgaplthr << 16) & ~((uint32_t)0x001F0000)) == 0);
ASSERT_ERR((((uint32_t)chgvgansthr << 8) & ~((uint32_t)0x00001F00)) == 0);
ASSERT_ERR((((uint32_t)chgvganlthr << 0) & ~((uint32_t)0x0000001F)) == 0);
REG_PL_WR(AGC_RWNXAGCCGH_ADDR, ((uint32_t)chgvgapsthr << 24) | ((uint32_t)chgvgaplthr << 16) | ((uint32_t)chgvgansthr << 8) | ((uint32_t)chgvganlthr << 0));
}
/**
* @brief Unpacks RWNXAGCCGH's fields from current value of the RWNXAGCCGH register.
*
* Reads the RWNXAGCCGH register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] chgvgapsthr - Will be populated with the current value of this field from the register.
* @param[out] chgvgaplthr - Will be populated with the current value of this field from the register.
* @param[out] chgvgansthr - Will be populated with the current value of this field from the register.
* @param[out] chgvganlthr - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagccgh_unpack(uint8_t *chgvgapsthr, uint8_t *chgvgaplthr, uint8_t *chgvgansthr, uint8_t *chgvganlthr)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCGH_ADDR);
*chgvgapsthr = (localVal & ((uint32_t)0x1F000000)) >> 24;
*chgvgaplthr = (localVal & ((uint32_t)0x001F0000)) >> 16;
*chgvgansthr = (localVal & ((uint32_t)0x00001F00)) >> 8;
*chgvganlthr = (localVal & ((uint32_t)0x0000001F)) >> 0;
}
/**
* @brief Returns the current value of the CHGVGAPSTHR field in the RWNXAGCCGH register.
*
* The RWNXAGCCGH register will be read and the CHGVGAPSTHR field's value will be returned.
*
* @return The current value of the CHGVGAPSTHR field in the RWNXAGCCGH register.
*/
__INLINE uint8_t agc_chgvgapsthr_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCGH_ADDR);
return ((localVal & ((uint32_t)0x1F000000)) >> 24);
}
/**
* @brief Sets the CHGVGAPSTHR field of the RWNXAGCCGH register.
*
* The RWNXAGCCGH register will be read, modified to contain the new field value, and written.
*
* @param[in] chgvgapsthr - The value to set the field to.
*/
__INLINE void agc_chgvgapsthr_setf(uint8_t chgvgapsthr)
{
ASSERT_ERR((((uint32_t)chgvgapsthr << 24) & ~((uint32_t)0x1F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCCGH_ADDR, (REG_PL_RD(AGC_RWNXAGCCGH_ADDR) & ~((uint32_t)0x1F000000)) | ((uint32_t)chgvgapsthr << 24));
}
/**
* @brief Returns the current value of the CHGVGAPLTHR field in the RWNXAGCCGH register.
*
* The RWNXAGCCGH register will be read and the CHGVGAPLTHR field's value will be returned.
*
* @return The current value of the CHGVGAPLTHR field in the RWNXAGCCGH register.
*/
__INLINE uint8_t agc_chgvgaplthr_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCGH_ADDR);
return ((localVal & ((uint32_t)0x001F0000)) >> 16);
}
/**
* @brief Sets the CHGVGAPLTHR field of the RWNXAGCCGH register.
*
* The RWNXAGCCGH register will be read, modified to contain the new field value, and written.
*
* @param[in] chgvgaplthr - The value to set the field to.
*/
__INLINE void agc_chgvgaplthr_setf(uint8_t chgvgaplthr)
{
ASSERT_ERR((((uint32_t)chgvgaplthr << 16) & ~((uint32_t)0x001F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCCGH_ADDR, (REG_PL_RD(AGC_RWNXAGCCGH_ADDR) & ~((uint32_t)0x001F0000)) | ((uint32_t)chgvgaplthr << 16));
}
/**
* @brief Returns the current value of the CHGVGANSTHR field in the RWNXAGCCGH register.
*
* The RWNXAGCCGH register will be read and the CHGVGANSTHR field's value will be returned.
*
* @return The current value of the CHGVGANSTHR field in the RWNXAGCCGH register.
*/
__INLINE uint8_t agc_chgvgansthr_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCGH_ADDR);
return ((localVal & ((uint32_t)0x00001F00)) >> 8);
}
/**
* @brief Sets the CHGVGANSTHR field of the RWNXAGCCGH register.
*
* The RWNXAGCCGH register will be read, modified to contain the new field value, and written.
*
* @param[in] chgvgansthr - The value to set the field to.
*/
__INLINE void agc_chgvgansthr_setf(uint8_t chgvgansthr)
{
ASSERT_ERR((((uint32_t)chgvgansthr << 8) & ~((uint32_t)0x00001F00)) == 0);
REG_PL_WR(AGC_RWNXAGCCGH_ADDR, (REG_PL_RD(AGC_RWNXAGCCGH_ADDR) & ~((uint32_t)0x00001F00)) | ((uint32_t)chgvgansthr << 8));
}
/**
* @brief Returns the current value of the CHGVGANLTHR field in the RWNXAGCCGH register.
*
* The RWNXAGCCGH register will be read and the CHGVGANLTHR field's value will be returned.
*
* @return The current value of the CHGVGANLTHR field in the RWNXAGCCGH register.
*/
__INLINE uint8_t agc_chgvganlthr_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCGH_ADDR);
return ((localVal & ((uint32_t)0x0000001F)) >> 0);
}
/**
* @brief Sets the CHGVGANLTHR field of the RWNXAGCCGH register.
*
* The RWNXAGCCGH register will be read, modified to contain the new field value, and written.
*
* @param[in] chgvganlthr - The value to set the field to.
*/
__INLINE void agc_chgvganlthr_setf(uint8_t chgvganlthr)
{
ASSERT_ERR((((uint32_t)chgvganlthr << 0) & ~((uint32_t)0x0000001F)) == 0);
REG_PL_WR(AGC_RWNXAGCCGH_ADDR, (REG_PL_RD(AGC_RWNXAGCCGH_ADDR) & ~((uint32_t)0x0000001F)) | ((uint32_t)chgvganlthr << 0));
}
/// @}
/**
* @name RWNXAGCSAT register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 28:24 SATDELAY50NS 0x8
* 21:16 SATHIGHTHRDBV 0x39
* 13:08 SATLOWTHRDBV 0x35
* 05:00 SATTHRDBV 0x36
* </pre>
*
* @{
*/
/// Address of the RWNXAGCSAT register
#define AGC_RWNXAGCSAT_ADDR 0x01002034
/// Offset of the RWNXAGCSAT register from the base address
#define AGC_RWNXAGCSAT_OFFSET 0x00002034
/// Index of the RWNXAGCSAT register
#define AGC_RWNXAGCSAT_INDEX 0x0000080D
/// Reset value of the RWNXAGCSAT register
#define AGC_RWNXAGCSAT_RESET 0x08393536
/**
* @brief Returns the current value of the RWNXAGCSAT register.
* The RWNXAGCSAT register will be read and its value returned.
* @return The current value of the RWNXAGCSAT register.
*/
__INLINE uint32_t agc_rwnxagcsat_get(void)
{
return REG_PL_RD(AGC_RWNXAGCSAT_ADDR);
}
/**
* @brief Sets the RWNXAGCSAT register to a value.
* The RWNXAGCSAT register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcsat_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCSAT_ADDR, value);
}
// field definitions
/// SATDELAY50NS field mask
#define AGC_SATDELAY50NS_MASK ((uint32_t)0x1F000000)
/// SATDELAY50NS field LSB position
#define AGC_SATDELAY50NS_LSB 24
/// SATDELAY50NS field width
#define AGC_SATDELAY50NS_WIDTH ((uint32_t)0x00000005)
/// SATHIGHTHRDBV field mask
#define AGC_SATHIGHTHRDBV_MASK ((uint32_t)0x003F0000)
/// SATHIGHTHRDBV field LSB position
#define AGC_SATHIGHTHRDBV_LSB 16
/// SATHIGHTHRDBV field width
#define AGC_SATHIGHTHRDBV_WIDTH ((uint32_t)0x00000006)
/// SATLOWTHRDBV field mask
#define AGC_SATLOWTHRDBV_MASK ((uint32_t)0x00003F00)
/// SATLOWTHRDBV field LSB position
#define AGC_SATLOWTHRDBV_LSB 8
/// SATLOWTHRDBV field width
#define AGC_SATLOWTHRDBV_WIDTH ((uint32_t)0x00000006)
/// SATTHRDBV field mask
#define AGC_SATTHRDBV_MASK ((uint32_t)0x0000003F)
/// SATTHRDBV field LSB position
#define AGC_SATTHRDBV_LSB 0
/// SATTHRDBV field width
#define AGC_SATTHRDBV_WIDTH ((uint32_t)0x00000006)
/// SATDELAY50NS field reset value
#define AGC_SATDELAY50NS_RST 0x8
/// SATHIGHTHRDBV field reset value
#define AGC_SATHIGHTHRDBV_RST 0x39
/// SATLOWTHRDBV field reset value
#define AGC_SATLOWTHRDBV_RST 0x35
/// SATTHRDBV field reset value
#define AGC_SATTHRDBV_RST 0x36
/**
* @brief Constructs a value for the RWNXAGCSAT register given values for its fields
* and writes the value to the register.
*
* @param[in] satdelay50ns - The value to use for the SATDELAY50NS field.
* @param[in] sathighthrdbv - The value to use for the SATHIGHTHRDBV field.
* @param[in] satlowthrdbv - The value to use for the SATLOWTHRDBV field.
* @param[in] satthrdbv - The value to use for the SATTHRDBV field.
*/
__INLINE void agc_rwnxagcsat_pack(uint8_t satdelay50ns, uint8_t sathighthrdbv, uint8_t satlowthrdbv, uint8_t satthrdbv)
{
ASSERT_ERR((((uint32_t)satdelay50ns << 24) & ~((uint32_t)0x1F000000)) == 0);
ASSERT_ERR((((uint32_t)sathighthrdbv << 16) & ~((uint32_t)0x003F0000)) == 0);
ASSERT_ERR((((uint32_t)satlowthrdbv << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)satthrdbv << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCSAT_ADDR, ((uint32_t)satdelay50ns << 24) | ((uint32_t)sathighthrdbv << 16) | ((uint32_t)satlowthrdbv << 8) | ((uint32_t)satthrdbv << 0));
}
/**
* @brief Unpacks RWNXAGCSAT's fields from current value of the RWNXAGCSAT register.
*
* Reads the RWNXAGCSAT register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] satdelay50ns - Will be populated with the current value of this field from the register.
* @param[out] sathighthrdbv - Will be populated with the current value of this field from the register.
* @param[out] satlowthrdbv - Will be populated with the current value of this field from the register.
* @param[out] satthrdbv - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcsat_unpack(uint8_t *satdelay50ns, uint8_t *sathighthrdbv, uint8_t *satlowthrdbv, uint8_t *satthrdbv)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSAT_ADDR);
*satdelay50ns = (localVal & ((uint32_t)0x1F000000)) >> 24;
*sathighthrdbv = (localVal & ((uint32_t)0x003F0000)) >> 16;
*satlowthrdbv = (localVal & ((uint32_t)0x00003F00)) >> 8;
*satthrdbv = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the SATDELAY50NS field in the RWNXAGCSAT register.
*
* The RWNXAGCSAT register will be read and the SATDELAY50NS field's value will be returned.
*
* @return The current value of the SATDELAY50NS field in the RWNXAGCSAT register.
*/
__INLINE uint8_t agc_satdelay50ns_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSAT_ADDR);
return ((localVal & ((uint32_t)0x1F000000)) >> 24);
}
/**
* @brief Sets the SATDELAY50NS field of the RWNXAGCSAT register.
*
* The RWNXAGCSAT register will be read, modified to contain the new field value, and written.
*
* @param[in] satdelay50ns - The value to set the field to.
*/
__INLINE void agc_satdelay50ns_setf(uint8_t satdelay50ns)
{
ASSERT_ERR((((uint32_t)satdelay50ns << 24) & ~((uint32_t)0x1F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCSAT_ADDR, (REG_PL_RD(AGC_RWNXAGCSAT_ADDR) & ~((uint32_t)0x1F000000)) | ((uint32_t)satdelay50ns << 24));
}
/**
* @brief Returns the current value of the SATHIGHTHRDBV field in the RWNXAGCSAT register.
*
* The RWNXAGCSAT register will be read and the SATHIGHTHRDBV field's value will be returned.
*
* @return The current value of the SATHIGHTHRDBV field in the RWNXAGCSAT register.
*/
__INLINE uint8_t agc_sathighthrdbv_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSAT_ADDR);
return ((localVal & ((uint32_t)0x003F0000)) >> 16);
}
/**
* @brief Sets the SATHIGHTHRDBV field of the RWNXAGCSAT register.
*
* The RWNXAGCSAT register will be read, modified to contain the new field value, and written.
*
* @param[in] sathighthrdbv - The value to set the field to.
*/
__INLINE void agc_sathighthrdbv_setf(uint8_t sathighthrdbv)
{
ASSERT_ERR((((uint32_t)sathighthrdbv << 16) & ~((uint32_t)0x003F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCSAT_ADDR, (REG_PL_RD(AGC_RWNXAGCSAT_ADDR) & ~((uint32_t)0x003F0000)) | ((uint32_t)sathighthrdbv << 16));
}
/**
* @brief Returns the current value of the SATLOWTHRDBV field in the RWNXAGCSAT register.
*
* The RWNXAGCSAT register will be read and the SATLOWTHRDBV field's value will be returned.
*
* @return The current value of the SATLOWTHRDBV field in the RWNXAGCSAT register.
*/
__INLINE uint8_t agc_satlowthrdbv_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSAT_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the SATLOWTHRDBV field of the RWNXAGCSAT register.
*
* The RWNXAGCSAT register will be read, modified to contain the new field value, and written.
*
* @param[in] satlowthrdbv - The value to set the field to.
*/
__INLINE void agc_satlowthrdbv_setf(uint8_t satlowthrdbv)
{
ASSERT_ERR((((uint32_t)satlowthrdbv << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCSAT_ADDR, (REG_PL_RD(AGC_RWNXAGCSAT_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)satlowthrdbv << 8));
}
/**
* @brief Returns the current value of the SATTHRDBV field in the RWNXAGCSAT register.
*
* The RWNXAGCSAT register will be read and the SATTHRDBV field's value will be returned.
*
* @return The current value of the SATTHRDBV field in the RWNXAGCSAT register.
*/
__INLINE uint8_t agc_satthrdbv_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSAT_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the SATTHRDBV field of the RWNXAGCSAT register.
*
* The RWNXAGCSAT register will be read, modified to contain the new field value, and written.
*
* @param[in] satthrdbv - The value to set the field to.
*/
__INLINE void agc_satthrdbv_setf(uint8_t satthrdbv)
{
ASSERT_ERR((((uint32_t)satthrdbv << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCSAT_ADDR, (REG_PL_RD(AGC_RWNXAGCSAT_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)satthrdbv << 0));
}
/// @}
/**
* @name RWNXAGCCROSS register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 21:12 CROSSDNTHRQDBM 0x280
* 09:00 CROSSUPTHRQDBM 0x288
* </pre>
*
* @{
*/
/// Address of the RWNXAGCCROSS register
#define AGC_RWNXAGCCROSS_ADDR 0x01002038
/// Offset of the RWNXAGCCROSS register from the base address
#define AGC_RWNXAGCCROSS_OFFSET 0x00002038
/// Index of the RWNXAGCCROSS register
#define AGC_RWNXAGCCROSS_INDEX 0x0000080E
/// Reset value of the RWNXAGCCROSS register
#define AGC_RWNXAGCCROSS_RESET 0x00280288
/**
* @brief Returns the current value of the RWNXAGCCROSS register.
* The RWNXAGCCROSS register will be read and its value returned.
* @return The current value of the RWNXAGCCROSS register.
*/
__INLINE uint32_t agc_rwnxagccross_get(void)
{
return REG_PL_RD(AGC_RWNXAGCCROSS_ADDR);
}
/**
* @brief Sets the RWNXAGCCROSS register to a value.
* The RWNXAGCCROSS register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagccross_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCCROSS_ADDR, value);
}
// field definitions
/// CROSSDNTHRQDBM field mask
#define AGC_CROSSDNTHRQDBM_MASK ((uint32_t)0x003FF000)
/// CROSSDNTHRQDBM field LSB position
#define AGC_CROSSDNTHRQDBM_LSB 12
/// CROSSDNTHRQDBM field width
#define AGC_CROSSDNTHRQDBM_WIDTH ((uint32_t)0x0000000A)
/// CROSSUPTHRQDBM field mask
#define AGC_CROSSUPTHRQDBM_MASK ((uint32_t)0x000003FF)
/// CROSSUPTHRQDBM field LSB position
#define AGC_CROSSUPTHRQDBM_LSB 0
/// CROSSUPTHRQDBM field width
#define AGC_CROSSUPTHRQDBM_WIDTH ((uint32_t)0x0000000A)
/// CROSSDNTHRQDBM field reset value
#define AGC_CROSSDNTHRQDBM_RST 0x280
/// CROSSUPTHRQDBM field reset value
#define AGC_CROSSUPTHRQDBM_RST 0x288
/**
* @brief Constructs a value for the RWNXAGCCROSS register given values for its fields
* and writes the value to the register.
*
* @param[in] crossdnthrqdbm - The value to use for the CROSSDNTHRQDBM field.
* @param[in] crossupthrqdbm - The value to use for the CROSSUPTHRQDBM field.
*/
__INLINE void agc_rwnxagccross_pack(uint16_t crossdnthrqdbm, uint16_t crossupthrqdbm)
{
ASSERT_ERR((((uint32_t)crossdnthrqdbm << 12) & ~((uint32_t)0x003FF000)) == 0);
ASSERT_ERR((((uint32_t)crossupthrqdbm << 0) & ~((uint32_t)0x000003FF)) == 0);
REG_PL_WR(AGC_RWNXAGCCROSS_ADDR, ((uint32_t)crossdnthrqdbm << 12) | ((uint32_t)crossupthrqdbm << 0));
}
/**
* @brief Unpacks RWNXAGCCROSS's fields from current value of the RWNXAGCCROSS register.
*
* Reads the RWNXAGCCROSS register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] crossdnthrqdbm - Will be populated with the current value of this field from the register.
* @param[out] crossupthrqdbm - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagccross_unpack(uint16_t *crossdnthrqdbm, uint16_t *crossupthrqdbm)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCROSS_ADDR);
*crossdnthrqdbm = (localVal & ((uint32_t)0x003FF000)) >> 12;
*crossupthrqdbm = (localVal & ((uint32_t)0x000003FF)) >> 0;
}
/**
* @brief Returns the current value of the CROSSDNTHRQDBM field in the RWNXAGCCROSS register.
*
* The RWNXAGCCROSS register will be read and the CROSSDNTHRQDBM field's value will be returned.
*
* @return The current value of the CROSSDNTHRQDBM field in the RWNXAGCCROSS register.
*/
__INLINE uint16_t agc_crossdnthrqdbm_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCROSS_ADDR);
return ((localVal & ((uint32_t)0x003FF000)) >> 12);
}
/**
* @brief Sets the CROSSDNTHRQDBM field of the RWNXAGCCROSS register.
*
* The RWNXAGCCROSS register will be read, modified to contain the new field value, and written.
*
* @param[in] crossdnthrqdbm - The value to set the field to.
*/
__INLINE void agc_crossdnthrqdbm_setf(uint16_t crossdnthrqdbm)
{
ASSERT_ERR((((uint32_t)crossdnthrqdbm << 12) & ~((uint32_t)0x003FF000)) == 0);
REG_PL_WR(AGC_RWNXAGCCROSS_ADDR, (REG_PL_RD(AGC_RWNXAGCCROSS_ADDR) & ~((uint32_t)0x003FF000)) | ((uint32_t)crossdnthrqdbm << 12));
}
/**
* @brief Returns the current value of the CROSSUPTHRQDBM field in the RWNXAGCCROSS register.
*
* The RWNXAGCCROSS register will be read and the CROSSUPTHRQDBM field's value will be returned.
*
* @return The current value of the CROSSUPTHRQDBM field in the RWNXAGCCROSS register.
*/
__INLINE uint16_t agc_crossupthrqdbm_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCROSS_ADDR);
return ((localVal & ((uint32_t)0x000003FF)) >> 0);
}
/**
* @brief Sets the CROSSUPTHRQDBM field of the RWNXAGCCROSS register.
*
* The RWNXAGCCROSS register will be read, modified to contain the new field value, and written.
*
* @param[in] crossupthrqdbm - The value to set the field to.
*/
__INLINE void agc_crossupthrqdbm_setf(uint16_t crossupthrqdbm)
{
ASSERT_ERR((((uint32_t)crossupthrqdbm << 0) & ~((uint32_t)0x000003FF)) == 0);
REG_PL_WR(AGC_RWNXAGCCROSS_ADDR, (REG_PL_RD(AGC_RWNXAGCCROSS_ADDR) & ~((uint32_t)0x000003FF)) | ((uint32_t)crossupthrqdbm << 0));
}
/// @}
/**
* @name RWNXAGCRAMP register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 26:24 RAMPDNNDLINDEX 0x7
* 23:16 RAMPDNGAPQDB 0x20
* 10:08 RAMPUPNDLINDEX 0x7
* 07:00 RAMPUPGAPQDB 0x10
* </pre>
*
* @{
*/
/// Address of the RWNXAGCRAMP register
#define AGC_RWNXAGCRAMP_ADDR 0x0100203C
/// Offset of the RWNXAGCRAMP register from the base address
#define AGC_RWNXAGCRAMP_OFFSET 0x0000203C
/// Index of the RWNXAGCRAMP register
#define AGC_RWNXAGCRAMP_INDEX 0x0000080F
/// Reset value of the RWNXAGCRAMP register
#define AGC_RWNXAGCRAMP_RESET 0x07200710
/**
* @brief Returns the current value of the RWNXAGCRAMP register.
* The RWNXAGCRAMP register will be read and its value returned.
* @return The current value of the RWNXAGCRAMP register.
*/
__INLINE uint32_t agc_rwnxagcramp_get(void)
{
return REG_PL_RD(AGC_RWNXAGCRAMP_ADDR);
}
/**
* @brief Sets the RWNXAGCRAMP register to a value.
* The RWNXAGCRAMP register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcramp_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCRAMP_ADDR, value);
}
// field definitions
/// RAMPDNNDLINDEX field mask
#define AGC_RAMPDNNDLINDEX_MASK ((uint32_t)0x07000000)
/// RAMPDNNDLINDEX field LSB position
#define AGC_RAMPDNNDLINDEX_LSB 24
/// RAMPDNNDLINDEX field width
#define AGC_RAMPDNNDLINDEX_WIDTH ((uint32_t)0x00000003)
/// RAMPDNGAPQDB field mask
#define AGC_RAMPDNGAPQDB_MASK ((uint32_t)0x00FF0000)
/// RAMPDNGAPQDB field LSB position
#define AGC_RAMPDNGAPQDB_LSB 16
/// RAMPDNGAPQDB field width
#define AGC_RAMPDNGAPQDB_WIDTH ((uint32_t)0x00000008)
/// RAMPUPNDLINDEX field mask
#define AGC_RAMPUPNDLINDEX_MASK ((uint32_t)0x00000700)
/// RAMPUPNDLINDEX field LSB position
#define AGC_RAMPUPNDLINDEX_LSB 8
/// RAMPUPNDLINDEX field width
#define AGC_RAMPUPNDLINDEX_WIDTH ((uint32_t)0x00000003)
/// RAMPUPGAPQDB field mask
#define AGC_RAMPUPGAPQDB_MASK ((uint32_t)0x000000FF)
/// RAMPUPGAPQDB field LSB position
#define AGC_RAMPUPGAPQDB_LSB 0
/// RAMPUPGAPQDB field width
#define AGC_RAMPUPGAPQDB_WIDTH ((uint32_t)0x00000008)
/// RAMPDNNDLINDEX field reset value
#define AGC_RAMPDNNDLINDEX_RST 0x7
/// RAMPDNGAPQDB field reset value
#define AGC_RAMPDNGAPQDB_RST 0x20
/// RAMPUPNDLINDEX field reset value
#define AGC_RAMPUPNDLINDEX_RST 0x7
/// RAMPUPGAPQDB field reset value
#define AGC_RAMPUPGAPQDB_RST 0x10
/**
* @brief Constructs a value for the RWNXAGCRAMP register given values for its fields
* and writes the value to the register.
*
* @param[in] rampdnndlindex - The value to use for the RAMPDNNDLINDEX field.
* @param[in] rampdngapqdb - The value to use for the RAMPDNGAPQDB field.
* @param[in] rampupndlindex - The value to use for the RAMPUPNDLINDEX field.
* @param[in] rampupgapqdb - The value to use for the RAMPUPGAPQDB field.
*/
__INLINE void agc_rwnxagcramp_pack(uint8_t rampdnndlindex, uint8_t rampdngapqdb, uint8_t rampupndlindex, uint8_t rampupgapqdb)
{
ASSERT_ERR((((uint32_t)rampdnndlindex << 24) & ~((uint32_t)0x07000000)) == 0);
ASSERT_ERR((((uint32_t)rampdngapqdb << 16) & ~((uint32_t)0x00FF0000)) == 0);
ASSERT_ERR((((uint32_t)rampupndlindex << 8) & ~((uint32_t)0x00000700)) == 0);
ASSERT_ERR((((uint32_t)rampupgapqdb << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCRAMP_ADDR, ((uint32_t)rampdnndlindex << 24) | ((uint32_t)rampdngapqdb << 16) | ((uint32_t)rampupndlindex << 8) | ((uint32_t)rampupgapqdb << 0));
}
/**
* @brief Unpacks RWNXAGCRAMP's fields from current value of the RWNXAGCRAMP register.
*
* Reads the RWNXAGCRAMP register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] rampdnndlindex - Will be populated with the current value of this field from the register.
* @param[out] rampdngapqdb - Will be populated with the current value of this field from the register.
* @param[out] rampupndlindex - Will be populated with the current value of this field from the register.
* @param[out] rampupgapqdb - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcramp_unpack(uint8_t *rampdnndlindex, uint8_t *rampdngapqdb, uint8_t *rampupndlindex, uint8_t *rampupgapqdb)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRAMP_ADDR);
*rampdnndlindex = (localVal & ((uint32_t)0x07000000)) >> 24;
*rampdngapqdb = (localVal & ((uint32_t)0x00FF0000)) >> 16;
*rampupndlindex = (localVal & ((uint32_t)0x00000700)) >> 8;
*rampupgapqdb = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the RAMPDNNDLINDEX field in the RWNXAGCRAMP register.
*
* The RWNXAGCRAMP register will be read and the RAMPDNNDLINDEX field's value will be returned.
*
* @return The current value of the RAMPDNNDLINDEX field in the RWNXAGCRAMP register.
*/
__INLINE uint8_t agc_rampdnndlindex_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRAMP_ADDR);
return ((localVal & ((uint32_t)0x07000000)) >> 24);
}
/**
* @brief Sets the RAMPDNNDLINDEX field of the RWNXAGCRAMP register.
*
* The RWNXAGCRAMP register will be read, modified to contain the new field value, and written.
*
* @param[in] rampdnndlindex - The value to set the field to.
*/
__INLINE void agc_rampdnndlindex_setf(uint8_t rampdnndlindex)
{
ASSERT_ERR((((uint32_t)rampdnndlindex << 24) & ~((uint32_t)0x07000000)) == 0);
REG_PL_WR(AGC_RWNXAGCRAMP_ADDR, (REG_PL_RD(AGC_RWNXAGCRAMP_ADDR) & ~((uint32_t)0x07000000)) | ((uint32_t)rampdnndlindex << 24));
}
/**
* @brief Returns the current value of the RAMPDNGAPQDB field in the RWNXAGCRAMP register.
*
* The RWNXAGCRAMP register will be read and the RAMPDNGAPQDB field's value will be returned.
*
* @return The current value of the RAMPDNGAPQDB field in the RWNXAGCRAMP register.
*/
__INLINE uint8_t agc_rampdngapqdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRAMP_ADDR);
return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
}
/**
* @brief Sets the RAMPDNGAPQDB field of the RWNXAGCRAMP register.
*
* The RWNXAGCRAMP register will be read, modified to contain the new field value, and written.
*
* @param[in] rampdngapqdb - The value to set the field to.
*/
__INLINE void agc_rampdngapqdb_setf(uint8_t rampdngapqdb)
{
ASSERT_ERR((((uint32_t)rampdngapqdb << 16) & ~((uint32_t)0x00FF0000)) == 0);
REG_PL_WR(AGC_RWNXAGCRAMP_ADDR, (REG_PL_RD(AGC_RWNXAGCRAMP_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)rampdngapqdb << 16));
}
/**
* @brief Returns the current value of the RAMPUPNDLINDEX field in the RWNXAGCRAMP register.
*
* The RWNXAGCRAMP register will be read and the RAMPUPNDLINDEX field's value will be returned.
*
* @return The current value of the RAMPUPNDLINDEX field in the RWNXAGCRAMP register.
*/
__INLINE uint8_t agc_rampupndlindex_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRAMP_ADDR);
return ((localVal & ((uint32_t)0x00000700)) >> 8);
}
/**
* @brief Sets the RAMPUPNDLINDEX field of the RWNXAGCRAMP register.
*
* The RWNXAGCRAMP register will be read, modified to contain the new field value, and written.
*
* @param[in] rampupndlindex - The value to set the field to.
*/
__INLINE void agc_rampupndlindex_setf(uint8_t rampupndlindex)
{
ASSERT_ERR((((uint32_t)rampupndlindex << 8) & ~((uint32_t)0x00000700)) == 0);
REG_PL_WR(AGC_RWNXAGCRAMP_ADDR, (REG_PL_RD(AGC_RWNXAGCRAMP_ADDR) & ~((uint32_t)0x00000700)) | ((uint32_t)rampupndlindex << 8));
}
/**
* @brief Returns the current value of the RAMPUPGAPQDB field in the RWNXAGCRAMP register.
*
* The RWNXAGCRAMP register will be read and the RAMPUPGAPQDB field's value will be returned.
*
* @return The current value of the RAMPUPGAPQDB field in the RWNXAGCRAMP register.
*/
__INLINE uint8_t agc_rampupgapqdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRAMP_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the RAMPUPGAPQDB field of the RWNXAGCRAMP register.
*
* The RWNXAGCRAMP register will be read, modified to contain the new field value, and written.
*
* @param[in] rampupgapqdb - The value to set the field to.
*/
__INLINE void agc_rampupgapqdb_setf(uint8_t rampupgapqdb)
{
ASSERT_ERR((((uint32_t)rampupgapqdb << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCRAMP_ADDR, (REG_PL_RD(AGC_RWNXAGCRAMP_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)rampupgapqdb << 0));
}
/// @}
/**
* @name RWNXAGCSTABDIS register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 27:24 ADCPOWDISNDL 0x8
* 22:16 ADCPOWDISTHRDBV 0x5D
* 10:08 PLATNDLINDEX 0x3
* 04:00 PLATDPQDB 0x8
* </pre>
*
* @{
*/
/// Address of the RWNXAGCSTABDIS register
#define AGC_RWNXAGCSTABDIS_ADDR 0x01002040
/// Offset of the RWNXAGCSTABDIS register from the base address
#define AGC_RWNXAGCSTABDIS_OFFSET 0x00002040
/// Index of the RWNXAGCSTABDIS register
#define AGC_RWNXAGCSTABDIS_INDEX 0x00000810
/// Reset value of the RWNXAGCSTABDIS register
#define AGC_RWNXAGCSTABDIS_RESET 0x085D0308
/**
* @brief Returns the current value of the RWNXAGCSTABDIS register.
* The RWNXAGCSTABDIS register will be read and its value returned.
* @return The current value of the RWNXAGCSTABDIS register.
*/
__INLINE uint32_t agc_rwnxagcstabdis_get(void)
{
return REG_PL_RD(AGC_RWNXAGCSTABDIS_ADDR);
}
/**
* @brief Sets the RWNXAGCSTABDIS register to a value.
* The RWNXAGCSTABDIS register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcstabdis_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCSTABDIS_ADDR, value);
}
// field definitions
/// ADCPOWDISNDL field mask
#define AGC_ADCPOWDISNDL_MASK ((uint32_t)0x0F000000)
/// ADCPOWDISNDL field LSB position
#define AGC_ADCPOWDISNDL_LSB 24
/// ADCPOWDISNDL field width
#define AGC_ADCPOWDISNDL_WIDTH ((uint32_t)0x00000004)
/// ADCPOWDISTHRDBV field mask
#define AGC_ADCPOWDISTHRDBV_MASK ((uint32_t)0x007F0000)
/// ADCPOWDISTHRDBV field LSB position
#define AGC_ADCPOWDISTHRDBV_LSB 16
/// ADCPOWDISTHRDBV field width
#define AGC_ADCPOWDISTHRDBV_WIDTH ((uint32_t)0x00000007)
/// PLATNDLINDEX field mask
#define AGC_PLATNDLINDEX_MASK ((uint32_t)0x00000700)
/// PLATNDLINDEX field LSB position
#define AGC_PLATNDLINDEX_LSB 8
/// PLATNDLINDEX field width
#define AGC_PLATNDLINDEX_WIDTH ((uint32_t)0x00000003)
/// PLATDPQDB field mask
#define AGC_PLATDPQDB_MASK ((uint32_t)0x0000001F)
/// PLATDPQDB field LSB position
#define AGC_PLATDPQDB_LSB 0
/// PLATDPQDB field width
#define AGC_PLATDPQDB_WIDTH ((uint32_t)0x00000005)
/// ADCPOWDISNDL field reset value
#define AGC_ADCPOWDISNDL_RST 0x8
/// ADCPOWDISTHRDBV field reset value
#define AGC_ADCPOWDISTHRDBV_RST 0x5D
/// PLATNDLINDEX field reset value
#define AGC_PLATNDLINDEX_RST 0x3
/// PLATDPQDB field reset value
#define AGC_PLATDPQDB_RST 0x8
/**
* @brief Constructs a value for the RWNXAGCSTABDIS register given values for its fields
* and writes the value to the register.
*
* @param[in] adcpowdisndl - The value to use for the ADCPOWDISNDL field.
* @param[in] adcpowdisthrdbv - The value to use for the ADCPOWDISTHRDBV field.
* @param[in] platndlindex - The value to use for the PLATNDLINDEX field.
* @param[in] platdpqdb - The value to use for the PLATDPQDB field.
*/
__INLINE void agc_rwnxagcstabdis_pack(uint8_t adcpowdisndl, uint8_t adcpowdisthrdbv, uint8_t platndlindex, uint8_t platdpqdb)
{
ASSERT_ERR((((uint32_t)adcpowdisndl << 24) & ~((uint32_t)0x0F000000)) == 0);
ASSERT_ERR((((uint32_t)adcpowdisthrdbv << 16) & ~((uint32_t)0x007F0000)) == 0);
ASSERT_ERR((((uint32_t)platndlindex << 8) & ~((uint32_t)0x00000700)) == 0);
ASSERT_ERR((((uint32_t)platdpqdb << 0) & ~((uint32_t)0x0000001F)) == 0);
REG_PL_WR(AGC_RWNXAGCSTABDIS_ADDR, ((uint32_t)adcpowdisndl << 24) | ((uint32_t)adcpowdisthrdbv << 16) | ((uint32_t)platndlindex << 8) | ((uint32_t)platdpqdb << 0));
}
/**
* @brief Unpacks RWNXAGCSTABDIS's fields from current value of the RWNXAGCSTABDIS register.
*
* Reads the RWNXAGCSTABDIS register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] adcpowdisndl - Will be populated with the current value of this field from the register.
* @param[out] adcpowdisthrdbv - Will be populated with the current value of this field from the register.
* @param[out] platndlindex - Will be populated with the current value of this field from the register.
* @param[out] platdpqdb - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcstabdis_unpack(uint8_t *adcpowdisndl, uint8_t *adcpowdisthrdbv, uint8_t *platndlindex, uint8_t *platdpqdb)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSTABDIS_ADDR);
*adcpowdisndl = (localVal & ((uint32_t)0x0F000000)) >> 24;
*adcpowdisthrdbv = (localVal & ((uint32_t)0x007F0000)) >> 16;
*platndlindex = (localVal & ((uint32_t)0x00000700)) >> 8;
*platdpqdb = (localVal & ((uint32_t)0x0000001F)) >> 0;
}
/**
* @brief Returns the current value of the ADCPOWDISNDL field in the RWNXAGCSTABDIS register.
*
* The RWNXAGCSTABDIS register will be read and the ADCPOWDISNDL field's value will be returned.
*
* @return The current value of the ADCPOWDISNDL field in the RWNXAGCSTABDIS register.
*/
__INLINE uint8_t agc_adcpowdisndl_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSTABDIS_ADDR);
return ((localVal & ((uint32_t)0x0F000000)) >> 24);
}
/**
* @brief Sets the ADCPOWDISNDL field of the RWNXAGCSTABDIS register.
*
* The RWNXAGCSTABDIS register will be read, modified to contain the new field value, and written.
*
* @param[in] adcpowdisndl - The value to set the field to.
*/
__INLINE void agc_adcpowdisndl_setf(uint8_t adcpowdisndl)
{
ASSERT_ERR((((uint32_t)adcpowdisndl << 24) & ~((uint32_t)0x0F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCSTABDIS_ADDR, (REG_PL_RD(AGC_RWNXAGCSTABDIS_ADDR) & ~((uint32_t)0x0F000000)) | ((uint32_t)adcpowdisndl << 24));
}
/**
* @brief Returns the current value of the ADCPOWDISTHRDBV field in the RWNXAGCSTABDIS register.
*
* The RWNXAGCSTABDIS register will be read and the ADCPOWDISTHRDBV field's value will be returned.
*
* @return The current value of the ADCPOWDISTHRDBV field in the RWNXAGCSTABDIS register.
*/
__INLINE uint8_t agc_adcpowdisthrdbv_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSTABDIS_ADDR);
return ((localVal & ((uint32_t)0x007F0000)) >> 16);
}
/**
* @brief Sets the ADCPOWDISTHRDBV field of the RWNXAGCSTABDIS register.
*
* The RWNXAGCSTABDIS register will be read, modified to contain the new field value, and written.
*
* @param[in] adcpowdisthrdbv - The value to set the field to.
*/
__INLINE void agc_adcpowdisthrdbv_setf(uint8_t adcpowdisthrdbv)
{
ASSERT_ERR((((uint32_t)adcpowdisthrdbv << 16) & ~((uint32_t)0x007F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCSTABDIS_ADDR, (REG_PL_RD(AGC_RWNXAGCSTABDIS_ADDR) & ~((uint32_t)0x007F0000)) | ((uint32_t)adcpowdisthrdbv << 16));
}
/**
* @brief Returns the current value of the PLATNDLINDEX field in the RWNXAGCSTABDIS register.
*
* The RWNXAGCSTABDIS register will be read and the PLATNDLINDEX field's value will be returned.
*
* @return The current value of the PLATNDLINDEX field in the RWNXAGCSTABDIS register.
*/
__INLINE uint8_t agc_platndlindex_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSTABDIS_ADDR);
return ((localVal & ((uint32_t)0x00000700)) >> 8);
}
/**
* @brief Sets the PLATNDLINDEX field of the RWNXAGCSTABDIS register.
*
* The RWNXAGCSTABDIS register will be read, modified to contain the new field value, and written.
*
* @param[in] platndlindex - The value to set the field to.
*/
__INLINE void agc_platndlindex_setf(uint8_t platndlindex)
{
ASSERT_ERR((((uint32_t)platndlindex << 8) & ~((uint32_t)0x00000700)) == 0);
REG_PL_WR(AGC_RWNXAGCSTABDIS_ADDR, (REG_PL_RD(AGC_RWNXAGCSTABDIS_ADDR) & ~((uint32_t)0x00000700)) | ((uint32_t)platndlindex << 8));
}
/**
* @brief Returns the current value of the PLATDPQDB field in the RWNXAGCSTABDIS register.
*
* The RWNXAGCSTABDIS register will be read and the PLATDPQDB field's value will be returned.
*
* @return The current value of the PLATDPQDB field in the RWNXAGCSTABDIS register.
*/
__INLINE uint8_t agc_platdpqdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSTABDIS_ADDR);
return ((localVal & ((uint32_t)0x0000001F)) >> 0);
}
/**
* @brief Sets the PLATDPQDB field of the RWNXAGCSTABDIS register.
*
* The RWNXAGCSTABDIS register will be read, modified to contain the new field value, and written.
*
* @param[in] platdpqdb - The value to set the field to.
*/
__INLINE void agc_platdpqdb_setf(uint8_t platdpqdb)
{
ASSERT_ERR((((uint32_t)platdpqdb << 0) & ~((uint32_t)0x0000001F)) == 0);
REG_PL_WR(AGC_RWNXAGCSTABDIS_ADDR, (REG_PL_RD(AGC_RWNXAGCSTABDIS_ADDR) & ~((uint32_t)0x0000001F)) | ((uint32_t)platdpqdb << 0));
}
/// @}
/**
* @name RWNXAGCDCCOMP0 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:28 DCRADARTYPE 0x3
* 25:24 DCMDM20TYPE 0x3
* 21:20 DCAGC20TYPE 0x1
* 17:16 DCADCTYPE 0x1
* 14:08 DCADCHOLDTIME50NS 0x0
* 06:00 DCADCZEROTIME50NS 0x0
* </pre>
*
* @{
*/
/// Address of the RWNXAGCDCCOMP0 register
#define AGC_RWNXAGCDCCOMP0_ADDR 0x01002044
/// Offset of the RWNXAGCDCCOMP0 register from the base address
#define AGC_RWNXAGCDCCOMP0_OFFSET 0x00002044
/// Index of the RWNXAGCDCCOMP0 register
#define AGC_RWNXAGCDCCOMP0_INDEX 0x00000811
/// Reset value of the RWNXAGCDCCOMP0 register
#define AGC_RWNXAGCDCCOMP0_RESET 0x33110000
/**
* @brief Returns the current value of the RWNXAGCDCCOMP0 register.
* The RWNXAGCDCCOMP0 register will be read and its value returned.
* @return The current value of the RWNXAGCDCCOMP0 register.
*/
__INLINE uint32_t agc_rwnxagcdccomp0_get(void)
{
return REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR);
}
/**
* @brief Sets the RWNXAGCDCCOMP0 register to a value.
* The RWNXAGCDCCOMP0 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcdccomp0_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCDCCOMP0_ADDR, value);
}
// field definitions
/// DCRADARTYPE field mask
#define AGC_DCRADARTYPE_MASK ((uint32_t)0x30000000)
/// DCRADARTYPE field LSB position
#define AGC_DCRADARTYPE_LSB 28
/// DCRADARTYPE field width
#define AGC_DCRADARTYPE_WIDTH ((uint32_t)0x00000002)
/// DCMDM20TYPE field mask
#define AGC_DCMDM20TYPE_MASK ((uint32_t)0x03000000)
/// DCMDM20TYPE field LSB position
#define AGC_DCMDM20TYPE_LSB 24
/// DCMDM20TYPE field width
#define AGC_DCMDM20TYPE_WIDTH ((uint32_t)0x00000002)
/// DCAGC20TYPE field mask
#define AGC_DCAGC20TYPE_MASK ((uint32_t)0x00300000)
/// DCAGC20TYPE field LSB position
#define AGC_DCAGC20TYPE_LSB 20
/// DCAGC20TYPE field width
#define AGC_DCAGC20TYPE_WIDTH ((uint32_t)0x00000002)
/// DCADCTYPE field mask
#define AGC_DCADCTYPE_MASK ((uint32_t)0x00030000)
/// DCADCTYPE field LSB position
#define AGC_DCADCTYPE_LSB 16
/// DCADCTYPE field width
#define AGC_DCADCTYPE_WIDTH ((uint32_t)0x00000002)
/// DCADCHOLDTIME50NS field mask
#define AGC_DCADCHOLDTIME50NS_MASK ((uint32_t)0x00007F00)
/// DCADCHOLDTIME50NS field LSB position
#define AGC_DCADCHOLDTIME50NS_LSB 8
/// DCADCHOLDTIME50NS field width
#define AGC_DCADCHOLDTIME50NS_WIDTH ((uint32_t)0x00000007)
/// DCADCZEROTIME50NS field mask
#define AGC_DCADCZEROTIME50NS_MASK ((uint32_t)0x0000007F)
/// DCADCZEROTIME50NS field LSB position
#define AGC_DCADCZEROTIME50NS_LSB 0
/// DCADCZEROTIME50NS field width
#define AGC_DCADCZEROTIME50NS_WIDTH ((uint32_t)0x00000007)
/// DCRADARTYPE field reset value
#define AGC_DCRADARTYPE_RST 0x3
/// DCMDM20TYPE field reset value
#define AGC_DCMDM20TYPE_RST 0x3
/// DCAGC20TYPE field reset value
#define AGC_DCAGC20TYPE_RST 0x1
/// DCADCTYPE field reset value
#define AGC_DCADCTYPE_RST 0x1
/// DCADCHOLDTIME50NS field reset value
#define AGC_DCADCHOLDTIME50NS_RST 0x0
/// DCADCZEROTIME50NS field reset value
#define AGC_DCADCZEROTIME50NS_RST 0x0
/**
* @brief Constructs a value for the RWNXAGCDCCOMP0 register given values for its fields
* and writes the value to the register.
*
* @param[in] dcradartype - The value to use for the DCRADARTYPE field.
* @param[in] dcmdm20type - The value to use for the DCMDM20TYPE field.
* @param[in] dcagc20type - The value to use for the DCAGC20TYPE field.
* @param[in] dcadctype - The value to use for the DCADCTYPE field.
* @param[in] dcadcholdtime50ns - The value to use for the DCADCHOLDTIME50NS field.
* @param[in] dcadczerotime50ns - The value to use for the DCADCZEROTIME50NS field.
*/
__INLINE void agc_rwnxagcdccomp0_pack(uint8_t dcradartype, uint8_t dcmdm20type, uint8_t dcagc20type, uint8_t dcadctype, uint8_t dcadcholdtime50ns, uint8_t dcadczerotime50ns)
{
ASSERT_ERR((((uint32_t)dcradartype << 28) & ~((uint32_t)0x30000000)) == 0);
ASSERT_ERR((((uint32_t)dcmdm20type << 24) & ~((uint32_t)0x03000000)) == 0);
ASSERT_ERR((((uint32_t)dcagc20type << 20) & ~((uint32_t)0x00300000)) == 0);
ASSERT_ERR((((uint32_t)dcadctype << 16) & ~((uint32_t)0x00030000)) == 0);
ASSERT_ERR((((uint32_t)dcadcholdtime50ns << 8) & ~((uint32_t)0x00007F00)) == 0);
ASSERT_ERR((((uint32_t)dcadczerotime50ns << 0) & ~((uint32_t)0x0000007F)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP0_ADDR, ((uint32_t)dcradartype << 28) | ((uint32_t)dcmdm20type << 24) | ((uint32_t)dcagc20type << 20) | ((uint32_t)dcadctype << 16) | ((uint32_t)dcadcholdtime50ns << 8) | ((uint32_t)dcadczerotime50ns << 0));
}
/**
* @brief Unpacks RWNXAGCDCCOMP0's fields from current value of the RWNXAGCDCCOMP0 register.
*
* Reads the RWNXAGCDCCOMP0 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] dcradartype - Will be populated with the current value of this field from the register.
* @param[out] dcmdm20type - Will be populated with the current value of this field from the register.
* @param[out] dcagc20type - Will be populated with the current value of this field from the register.
* @param[out] dcadctype - Will be populated with the current value of this field from the register.
* @param[out] dcadcholdtime50ns - Will be populated with the current value of this field from the register.
* @param[out] dcadczerotime50ns - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcdccomp0_unpack(uint8_t *dcradartype, uint8_t *dcmdm20type, uint8_t *dcagc20type, uint8_t *dcadctype, uint8_t *dcadcholdtime50ns, uint8_t *dcadczerotime50ns)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR);
*dcradartype = (localVal & ((uint32_t)0x30000000)) >> 28;
*dcmdm20type = (localVal & ((uint32_t)0x03000000)) >> 24;
*dcagc20type = (localVal & ((uint32_t)0x00300000)) >> 20;
*dcadctype = (localVal & ((uint32_t)0x00030000)) >> 16;
*dcadcholdtime50ns = (localVal & ((uint32_t)0x00007F00)) >> 8;
*dcadczerotime50ns = (localVal & ((uint32_t)0x0000007F)) >> 0;
}
/**
* @brief Returns the current value of the DCRADARTYPE field in the RWNXAGCDCCOMP0 register.
*
* The RWNXAGCDCCOMP0 register will be read and the DCRADARTYPE field's value will be returned.
*
* @return The current value of the DCRADARTYPE field in the RWNXAGCDCCOMP0 register.
*/
__INLINE uint8_t agc_dcradartype_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR);
return ((localVal & ((uint32_t)0x30000000)) >> 28);
}
/**
* @brief Sets the DCRADARTYPE field of the RWNXAGCDCCOMP0 register.
*
* The RWNXAGCDCCOMP0 register will be read, modified to contain the new field value, and written.
*
* @param[in] dcradartype - The value to set the field to.
*/
__INLINE void agc_dcradartype_setf(uint8_t dcradartype)
{
ASSERT_ERR((((uint32_t)dcradartype << 28) & ~((uint32_t)0x30000000)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP0_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR) & ~((uint32_t)0x30000000)) | ((uint32_t)dcradartype << 28));
}
/**
* @brief Returns the current value of the DCMDM20TYPE field in the RWNXAGCDCCOMP0 register.
*
* The RWNXAGCDCCOMP0 register will be read and the DCMDM20TYPE field's value will be returned.
*
* @return The current value of the DCMDM20TYPE field in the RWNXAGCDCCOMP0 register.
*/
__INLINE uint8_t agc_dcmdm20type_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR);
return ((localVal & ((uint32_t)0x03000000)) >> 24);
}
/**
* @brief Sets the DCMDM20TYPE field of the RWNXAGCDCCOMP0 register.
*
* The RWNXAGCDCCOMP0 register will be read, modified to contain the new field value, and written.
*
* @param[in] dcmdm20type - The value to set the field to.
*/
__INLINE void agc_dcmdm20type_setf(uint8_t dcmdm20type)
{
ASSERT_ERR((((uint32_t)dcmdm20type << 24) & ~((uint32_t)0x03000000)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP0_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR) & ~((uint32_t)0x03000000)) | ((uint32_t)dcmdm20type << 24));
}
/**
* @brief Returns the current value of the DCAGC20TYPE field in the RWNXAGCDCCOMP0 register.
*
* The RWNXAGCDCCOMP0 register will be read and the DCAGC20TYPE field's value will be returned.
*
* @return The current value of the DCAGC20TYPE field in the RWNXAGCDCCOMP0 register.
*/
__INLINE uint8_t agc_dcagc20type_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR);
return ((localVal & ((uint32_t)0x00300000)) >> 20);
}
/**
* @brief Sets the DCAGC20TYPE field of the RWNXAGCDCCOMP0 register.
*
* The RWNXAGCDCCOMP0 register will be read, modified to contain the new field value, and written.
*
* @param[in] dcagc20type - The value to set the field to.
*/
__INLINE void agc_dcagc20type_setf(uint8_t dcagc20type)
{
ASSERT_ERR((((uint32_t)dcagc20type << 20) & ~((uint32_t)0x00300000)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP0_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR) & ~((uint32_t)0x00300000)) | ((uint32_t)dcagc20type << 20));
}
/**
* @brief Returns the current value of the DCADCTYPE field in the RWNXAGCDCCOMP0 register.
*
* The RWNXAGCDCCOMP0 register will be read and the DCADCTYPE field's value will be returned.
*
* @return The current value of the DCADCTYPE field in the RWNXAGCDCCOMP0 register.
*/
__INLINE uint8_t agc_dcadctype_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR);
return ((localVal & ((uint32_t)0x00030000)) >> 16);
}
/**
* @brief Sets the DCADCTYPE field of the RWNXAGCDCCOMP0 register.
*
* The RWNXAGCDCCOMP0 register will be read, modified to contain the new field value, and written.
*
* @param[in] dcadctype - The value to set the field to.
*/
__INLINE void agc_dcadctype_setf(uint8_t dcadctype)
{
ASSERT_ERR((((uint32_t)dcadctype << 16) & ~((uint32_t)0x00030000)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP0_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR) & ~((uint32_t)0x00030000)) | ((uint32_t)dcadctype << 16));
}
/**
* @brief Returns the current value of the DCADCHOLDTIME50NS field in the RWNXAGCDCCOMP0 register.
*
* The RWNXAGCDCCOMP0 register will be read and the DCADCHOLDTIME50NS field's value will be returned.
*
* @return The current value of the DCADCHOLDTIME50NS field in the RWNXAGCDCCOMP0 register.
*/
__INLINE uint8_t agc_dcadcholdtime50ns_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR);
return ((localVal & ((uint32_t)0x00007F00)) >> 8);
}
/**
* @brief Sets the DCADCHOLDTIME50NS field of the RWNXAGCDCCOMP0 register.
*
* The RWNXAGCDCCOMP0 register will be read, modified to contain the new field value, and written.
*
* @param[in] dcadcholdtime50ns - The value to set the field to.
*/
__INLINE void agc_dcadcholdtime50ns_setf(uint8_t dcadcholdtime50ns)
{
ASSERT_ERR((((uint32_t)dcadcholdtime50ns << 8) & ~((uint32_t)0x00007F00)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP0_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR) & ~((uint32_t)0x00007F00)) | ((uint32_t)dcadcholdtime50ns << 8));
}
/**
* @brief Returns the current value of the DCADCZEROTIME50NS field in the RWNXAGCDCCOMP0 register.
*
* The RWNXAGCDCCOMP0 register will be read and the DCADCZEROTIME50NS field's value will be returned.
*
* @return The current value of the DCADCZEROTIME50NS field in the RWNXAGCDCCOMP0 register.
*/
__INLINE uint8_t agc_dcadczerotime50ns_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR);
return ((localVal & ((uint32_t)0x0000007F)) >> 0);
}
/**
* @brief Sets the DCADCZEROTIME50NS field of the RWNXAGCDCCOMP0 register.
*
* The RWNXAGCDCCOMP0 register will be read, modified to contain the new field value, and written.
*
* @param[in] dcadczerotime50ns - The value to set the field to.
*/
__INLINE void agc_dcadczerotime50ns_setf(uint8_t dcadczerotime50ns)
{
ASSERT_ERR((((uint32_t)dcadczerotime50ns << 0) & ~((uint32_t)0x0000007F)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP0_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP0_ADDR) & ~((uint32_t)0x0000007F)) | ((uint32_t)dcadczerotime50ns << 0));
}
/// @}
/**
* @name RWNXAGCDCCOMP1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 30:24 DCMDM20HOLDTIME50NS 0x14
* 22:16 DCMDM20ZEROTIME50NS 0x0
* 14:08 DCAGC20HOLDTIME50NS 0x0
* 06:00 DCAGC20ZEROTIME50NS 0x0
* </pre>
*
* @{
*/
/// Address of the RWNXAGCDCCOMP1 register
#define AGC_RWNXAGCDCCOMP1_ADDR 0x01002048
/// Offset of the RWNXAGCDCCOMP1 register from the base address
#define AGC_RWNXAGCDCCOMP1_OFFSET 0x00002048
/// Index of the RWNXAGCDCCOMP1 register
#define AGC_RWNXAGCDCCOMP1_INDEX 0x00000812
/// Reset value of the RWNXAGCDCCOMP1 register
#define AGC_RWNXAGCDCCOMP1_RESET 0x14000000
/**
* @brief Returns the current value of the RWNXAGCDCCOMP1 register.
* The RWNXAGCDCCOMP1 register will be read and its value returned.
* @return The current value of the RWNXAGCDCCOMP1 register.
*/
__INLINE uint32_t agc_rwnxagcdccomp1_get(void)
{
return REG_PL_RD(AGC_RWNXAGCDCCOMP1_ADDR);
}
/**
* @brief Sets the RWNXAGCDCCOMP1 register to a value.
* The RWNXAGCDCCOMP1 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcdccomp1_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCDCCOMP1_ADDR, value);
}
// field definitions
/// DCMDM20HOLDTIME50NS field mask
#define AGC_DCMDM20HOLDTIME50NS_MASK ((uint32_t)0x7F000000)
/// DCMDM20HOLDTIME50NS field LSB position
#define AGC_DCMDM20HOLDTIME50NS_LSB 24
/// DCMDM20HOLDTIME50NS field width
#define AGC_DCMDM20HOLDTIME50NS_WIDTH ((uint32_t)0x00000007)
/// DCMDM20ZEROTIME50NS field mask
#define AGC_DCMDM20ZEROTIME50NS_MASK ((uint32_t)0x007F0000)
/// DCMDM20ZEROTIME50NS field LSB position
#define AGC_DCMDM20ZEROTIME50NS_LSB 16
/// DCMDM20ZEROTIME50NS field width
#define AGC_DCMDM20ZEROTIME50NS_WIDTH ((uint32_t)0x00000007)
/// DCAGC20HOLDTIME50NS field mask
#define AGC_DCAGC20HOLDTIME50NS_MASK ((uint32_t)0x00007F00)
/// DCAGC20HOLDTIME50NS field LSB position
#define AGC_DCAGC20HOLDTIME50NS_LSB 8
/// DCAGC20HOLDTIME50NS field width
#define AGC_DCAGC20HOLDTIME50NS_WIDTH ((uint32_t)0x00000007)
/// DCAGC20ZEROTIME50NS field mask
#define AGC_DCAGC20ZEROTIME50NS_MASK ((uint32_t)0x0000007F)
/// DCAGC20ZEROTIME50NS field LSB position
#define AGC_DCAGC20ZEROTIME50NS_LSB 0
/// DCAGC20ZEROTIME50NS field width
#define AGC_DCAGC20ZEROTIME50NS_WIDTH ((uint32_t)0x00000007)
/// DCMDM20HOLDTIME50NS field reset value
#define AGC_DCMDM20HOLDTIME50NS_RST 0x14
/// DCMDM20ZEROTIME50NS field reset value
#define AGC_DCMDM20ZEROTIME50NS_RST 0x0
/// DCAGC20HOLDTIME50NS field reset value
#define AGC_DCAGC20HOLDTIME50NS_RST 0x0
/// DCAGC20ZEROTIME50NS field reset value
#define AGC_DCAGC20ZEROTIME50NS_RST 0x0
/**
* @brief Constructs a value for the RWNXAGCDCCOMP1 register given values for its fields
* and writes the value to the register.
*
* @param[in] dcmdm20holdtime50ns - The value to use for the DCMDM20HOLDTIME50NS field.
* @param[in] dcmdm20zerotime50ns - The value to use for the DCMDM20ZEROTIME50NS field.
* @param[in] dcagc20holdtime50ns - The value to use for the DCAGC20HOLDTIME50NS field.
* @param[in] dcagc20zerotime50ns - The value to use for the DCAGC20ZEROTIME50NS field.
*/
__INLINE void agc_rwnxagcdccomp1_pack(uint8_t dcmdm20holdtime50ns, uint8_t dcmdm20zerotime50ns, uint8_t dcagc20holdtime50ns, uint8_t dcagc20zerotime50ns)
{
ASSERT_ERR((((uint32_t)dcmdm20holdtime50ns << 24) & ~((uint32_t)0x7F000000)) == 0);
ASSERT_ERR((((uint32_t)dcmdm20zerotime50ns << 16) & ~((uint32_t)0x007F0000)) == 0);
ASSERT_ERR((((uint32_t)dcagc20holdtime50ns << 8) & ~((uint32_t)0x00007F00)) == 0);
ASSERT_ERR((((uint32_t)dcagc20zerotime50ns << 0) & ~((uint32_t)0x0000007F)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP1_ADDR, ((uint32_t)dcmdm20holdtime50ns << 24) | ((uint32_t)dcmdm20zerotime50ns << 16) | ((uint32_t)dcagc20holdtime50ns << 8) | ((uint32_t)dcagc20zerotime50ns << 0));
}
/**
* @brief Unpacks RWNXAGCDCCOMP1's fields from current value of the RWNXAGCDCCOMP1 register.
*
* Reads the RWNXAGCDCCOMP1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] dcmdm20holdtime50ns - Will be populated with the current value of this field from the register.
* @param[out] dcmdm20zerotime50ns - Will be populated with the current value of this field from the register.
* @param[out] dcagc20holdtime50ns - Will be populated with the current value of this field from the register.
* @param[out] dcagc20zerotime50ns - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcdccomp1_unpack(uint8_t *dcmdm20holdtime50ns, uint8_t *dcmdm20zerotime50ns, uint8_t *dcagc20holdtime50ns, uint8_t *dcagc20zerotime50ns)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP1_ADDR);
*dcmdm20holdtime50ns = (localVal & ((uint32_t)0x7F000000)) >> 24;
*dcmdm20zerotime50ns = (localVal & ((uint32_t)0x007F0000)) >> 16;
*dcagc20holdtime50ns = (localVal & ((uint32_t)0x00007F00)) >> 8;
*dcagc20zerotime50ns = (localVal & ((uint32_t)0x0000007F)) >> 0;
}
/**
* @brief Returns the current value of the DCMDM20HOLDTIME50NS field in the RWNXAGCDCCOMP1 register.
*
* The RWNXAGCDCCOMP1 register will be read and the DCMDM20HOLDTIME50NS field's value will be returned.
*
* @return The current value of the DCMDM20HOLDTIME50NS field in the RWNXAGCDCCOMP1 register.
*/
__INLINE uint8_t agc_dcmdm20holdtime50ns_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP1_ADDR);
return ((localVal & ((uint32_t)0x7F000000)) >> 24);
}
/**
* @brief Sets the DCMDM20HOLDTIME50NS field of the RWNXAGCDCCOMP1 register.
*
* The RWNXAGCDCCOMP1 register will be read, modified to contain the new field value, and written.
*
* @param[in] dcmdm20holdtime50ns - The value to set the field to.
*/
__INLINE void agc_dcmdm20holdtime50ns_setf(uint8_t dcmdm20holdtime50ns)
{
ASSERT_ERR((((uint32_t)dcmdm20holdtime50ns << 24) & ~((uint32_t)0x7F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP1_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP1_ADDR) & ~((uint32_t)0x7F000000)) | ((uint32_t)dcmdm20holdtime50ns << 24));
}
/**
* @brief Returns the current value of the DCMDM20ZEROTIME50NS field in the RWNXAGCDCCOMP1 register.
*
* The RWNXAGCDCCOMP1 register will be read and the DCMDM20ZEROTIME50NS field's value will be returned.
*
* @return The current value of the DCMDM20ZEROTIME50NS field in the RWNXAGCDCCOMP1 register.
*/
__INLINE uint8_t agc_dcmdm20zerotime50ns_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP1_ADDR);
return ((localVal & ((uint32_t)0x007F0000)) >> 16);
}
/**
* @brief Sets the DCMDM20ZEROTIME50NS field of the RWNXAGCDCCOMP1 register.
*
* The RWNXAGCDCCOMP1 register will be read, modified to contain the new field value, and written.
*
* @param[in] dcmdm20zerotime50ns - The value to set the field to.
*/
__INLINE void agc_dcmdm20zerotime50ns_setf(uint8_t dcmdm20zerotime50ns)
{
ASSERT_ERR((((uint32_t)dcmdm20zerotime50ns << 16) & ~((uint32_t)0x007F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP1_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP1_ADDR) & ~((uint32_t)0x007F0000)) | ((uint32_t)dcmdm20zerotime50ns << 16));
}
/**
* @brief Returns the current value of the DCAGC20HOLDTIME50NS field in the RWNXAGCDCCOMP1 register.
*
* The RWNXAGCDCCOMP1 register will be read and the DCAGC20HOLDTIME50NS field's value will be returned.
*
* @return The current value of the DCAGC20HOLDTIME50NS field in the RWNXAGCDCCOMP1 register.
*/
__INLINE uint8_t agc_dcagc20holdtime50ns_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP1_ADDR);
return ((localVal & ((uint32_t)0x00007F00)) >> 8);
}
/**
* @brief Sets the DCAGC20HOLDTIME50NS field of the RWNXAGCDCCOMP1 register.
*
* The RWNXAGCDCCOMP1 register will be read, modified to contain the new field value, and written.
*
* @param[in] dcagc20holdtime50ns - The value to set the field to.
*/
__INLINE void agc_dcagc20holdtime50ns_setf(uint8_t dcagc20holdtime50ns)
{
ASSERT_ERR((((uint32_t)dcagc20holdtime50ns << 8) & ~((uint32_t)0x00007F00)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP1_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP1_ADDR) & ~((uint32_t)0x00007F00)) | ((uint32_t)dcagc20holdtime50ns << 8));
}
/**
* @brief Returns the current value of the DCAGC20ZEROTIME50NS field in the RWNXAGCDCCOMP1 register.
*
* The RWNXAGCDCCOMP1 register will be read and the DCAGC20ZEROTIME50NS field's value will be returned.
*
* @return The current value of the DCAGC20ZEROTIME50NS field in the RWNXAGCDCCOMP1 register.
*/
__INLINE uint8_t agc_dcagc20zerotime50ns_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP1_ADDR);
return ((localVal & ((uint32_t)0x0000007F)) >> 0);
}
/**
* @brief Sets the DCAGC20ZEROTIME50NS field of the RWNXAGCDCCOMP1 register.
*
* The RWNXAGCDCCOMP1 register will be read, modified to contain the new field value, and written.
*
* @param[in] dcagc20zerotime50ns - The value to set the field to.
*/
__INLINE void agc_dcagc20zerotime50ns_setf(uint8_t dcagc20zerotime50ns)
{
ASSERT_ERR((((uint32_t)dcagc20zerotime50ns << 0) & ~((uint32_t)0x0000007F)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP1_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP1_ADDR) & ~((uint32_t)0x0000007F)) | ((uint32_t)dcagc20zerotime50ns << 0));
}
/// @}
/**
* @name RWNXAGCDCCOMP2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 22:16 DCRADARHOLDTIME50NS 0x0
* 14:08 DCRADARZEROTIME50NS 0x0
* 06:00 DELDCSTABLECC 0x0
* </pre>
*
* @{
*/
/// Address of the RWNXAGCDCCOMP2 register
#define AGC_RWNXAGCDCCOMP2_ADDR 0x0100204C
/// Offset of the RWNXAGCDCCOMP2 register from the base address
#define AGC_RWNXAGCDCCOMP2_OFFSET 0x0000204C
/// Index of the RWNXAGCDCCOMP2 register
#define AGC_RWNXAGCDCCOMP2_INDEX 0x00000813
/// Reset value of the RWNXAGCDCCOMP2 register
#define AGC_RWNXAGCDCCOMP2_RESET 0x00000000
/**
* @brief Returns the current value of the RWNXAGCDCCOMP2 register.
* The RWNXAGCDCCOMP2 register will be read and its value returned.
* @return The current value of the RWNXAGCDCCOMP2 register.
*/
__INLINE uint32_t agc_rwnxagcdccomp2_get(void)
{
return REG_PL_RD(AGC_RWNXAGCDCCOMP2_ADDR);
}
/**
* @brief Sets the RWNXAGCDCCOMP2 register to a value.
* The RWNXAGCDCCOMP2 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcdccomp2_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCDCCOMP2_ADDR, value);
}
// field definitions
/// DCRADARHOLDTIME50NS field mask
#define AGC_DCRADARHOLDTIME50NS_MASK ((uint32_t)0x007F0000)
/// DCRADARHOLDTIME50NS field LSB position
#define AGC_DCRADARHOLDTIME50NS_LSB 16
/// DCRADARHOLDTIME50NS field width
#define AGC_DCRADARHOLDTIME50NS_WIDTH ((uint32_t)0x00000007)
/// DCRADARZEROTIME50NS field mask
#define AGC_DCRADARZEROTIME50NS_MASK ((uint32_t)0x00007F00)
/// DCRADARZEROTIME50NS field LSB position
#define AGC_DCRADARZEROTIME50NS_LSB 8
/// DCRADARZEROTIME50NS field width
#define AGC_DCRADARZEROTIME50NS_WIDTH ((uint32_t)0x00000007)
/// DELDCSTABLECC field mask
#define AGC_DELDCSTABLECC_MASK ((uint32_t)0x0000007F)
/// DELDCSTABLECC field LSB position
#define AGC_DELDCSTABLECC_LSB 0
/// DELDCSTABLECC field width
#define AGC_DELDCSTABLECC_WIDTH ((uint32_t)0x00000007)
/// DCRADARHOLDTIME50NS field reset value
#define AGC_DCRADARHOLDTIME50NS_RST 0x0
/// DCRADARZEROTIME50NS field reset value
#define AGC_DCRADARZEROTIME50NS_RST 0x0
/// DELDCSTABLECC field reset value
#define AGC_DELDCSTABLECC_RST 0x0
/**
* @brief Constructs a value for the RWNXAGCDCCOMP2 register given values for its fields
* and writes the value to the register.
*
* @param[in] dcradarholdtime50ns - The value to use for the DCRADARHOLDTIME50NS field.
* @param[in] dcradarzerotime50ns - The value to use for the DCRADARZEROTIME50NS field.
* @param[in] deldcstablecc - The value to use for the DELDCSTABLECC field.
*/
__INLINE void agc_rwnxagcdccomp2_pack(uint8_t dcradarholdtime50ns, uint8_t dcradarzerotime50ns, uint8_t deldcstablecc)
{
ASSERT_ERR((((uint32_t)dcradarholdtime50ns << 16) & ~((uint32_t)0x007F0000)) == 0);
ASSERT_ERR((((uint32_t)dcradarzerotime50ns << 8) & ~((uint32_t)0x00007F00)) == 0);
ASSERT_ERR((((uint32_t)deldcstablecc << 0) & ~((uint32_t)0x0000007F)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP2_ADDR, ((uint32_t)dcradarholdtime50ns << 16) | ((uint32_t)dcradarzerotime50ns << 8) | ((uint32_t)deldcstablecc << 0));
}
/**
* @brief Unpacks RWNXAGCDCCOMP2's fields from current value of the RWNXAGCDCCOMP2 register.
*
* Reads the RWNXAGCDCCOMP2 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] dcradarholdtime50ns - Will be populated with the current value of this field from the register.
* @param[out] dcradarzerotime50ns - Will be populated with the current value of this field from the register.
* @param[out] deldcstablecc - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcdccomp2_unpack(uint8_t *dcradarholdtime50ns, uint8_t *dcradarzerotime50ns, uint8_t *deldcstablecc)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP2_ADDR);
*dcradarholdtime50ns = (localVal & ((uint32_t)0x007F0000)) >> 16;
*dcradarzerotime50ns = (localVal & ((uint32_t)0x00007F00)) >> 8;
*deldcstablecc = (localVal & ((uint32_t)0x0000007F)) >> 0;
}
/**
* @brief Returns the current value of the DCRADARHOLDTIME50NS field in the RWNXAGCDCCOMP2 register.
*
* The RWNXAGCDCCOMP2 register will be read and the DCRADARHOLDTIME50NS field's value will be returned.
*
* @return The current value of the DCRADARHOLDTIME50NS field in the RWNXAGCDCCOMP2 register.
*/
__INLINE uint8_t agc_dcradarholdtime50ns_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP2_ADDR);
return ((localVal & ((uint32_t)0x007F0000)) >> 16);
}
/**
* @brief Sets the DCRADARHOLDTIME50NS field of the RWNXAGCDCCOMP2 register.
*
* The RWNXAGCDCCOMP2 register will be read, modified to contain the new field value, and written.
*
* @param[in] dcradarholdtime50ns - The value to set the field to.
*/
__INLINE void agc_dcradarholdtime50ns_setf(uint8_t dcradarholdtime50ns)
{
ASSERT_ERR((((uint32_t)dcradarholdtime50ns << 16) & ~((uint32_t)0x007F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP2_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP2_ADDR) & ~((uint32_t)0x007F0000)) | ((uint32_t)dcradarholdtime50ns << 16));
}
/**
* @brief Returns the current value of the DCRADARZEROTIME50NS field in the RWNXAGCDCCOMP2 register.
*
* The RWNXAGCDCCOMP2 register will be read and the DCRADARZEROTIME50NS field's value will be returned.
*
* @return The current value of the DCRADARZEROTIME50NS field in the RWNXAGCDCCOMP2 register.
*/
__INLINE uint8_t agc_dcradarzerotime50ns_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP2_ADDR);
return ((localVal & ((uint32_t)0x00007F00)) >> 8);
}
/**
* @brief Sets the DCRADARZEROTIME50NS field of the RWNXAGCDCCOMP2 register.
*
* The RWNXAGCDCCOMP2 register will be read, modified to contain the new field value, and written.
*
* @param[in] dcradarzerotime50ns - The value to set the field to.
*/
__INLINE void agc_dcradarzerotime50ns_setf(uint8_t dcradarzerotime50ns)
{
ASSERT_ERR((((uint32_t)dcradarzerotime50ns << 8) & ~((uint32_t)0x00007F00)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP2_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP2_ADDR) & ~((uint32_t)0x00007F00)) | ((uint32_t)dcradarzerotime50ns << 8));
}
/**
* @brief Returns the current value of the DELDCSTABLECC field in the RWNXAGCDCCOMP2 register.
*
* The RWNXAGCDCCOMP2 register will be read and the DELDCSTABLECC field's value will be returned.
*
* @return The current value of the DELDCSTABLECC field in the RWNXAGCDCCOMP2 register.
*/
__INLINE uint8_t agc_deldcstablecc_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDCCOMP2_ADDR);
return ((localVal & ((uint32_t)0x0000007F)) >> 0);
}
/**
* @brief Sets the DELDCSTABLECC field of the RWNXAGCDCCOMP2 register.
*
* The RWNXAGCDCCOMP2 register will be read, modified to contain the new field value, and written.
*
* @param[in] deldcstablecc - The value to set the field to.
*/
__INLINE void agc_deldcstablecc_setf(uint8_t deldcstablecc)
{
ASSERT_ERR((((uint32_t)deldcstablecc << 0) & ~((uint32_t)0x0000007F)) == 0);
REG_PL_WR(AGC_RWNXAGCDCCOMP2_ADDR, (REG_PL_RD(AGC_RWNXAGCDCCOMP2_ADDR) & ~((uint32_t)0x0000007F)) | ((uint32_t)deldcstablecc << 0));
}
/// @}
/**
* @name RWNXAGCEVTSAT register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:26 EVT0OP3 0x1
* 25:20 EVT0OP2 0x10
* 19:14 EVT0OP1 0x11
* 13 EVT0PATHCOMB 0
* 12:11 EVT0OPCOMB 0x1
* 10:00 EVT0TGTADD 0x4
* </pre>
*
* @{
*/
/// Address of the RWNXAGCEVTSAT register
#define AGC_RWNXAGCEVTSAT_ADDR 0x01002050
/// Offset of the RWNXAGCEVTSAT register from the base address
#define AGC_RWNXAGCEVTSAT_OFFSET 0x00002050
/// Index of the RWNXAGCEVTSAT register
#define AGC_RWNXAGCEVTSAT_INDEX 0x00000814
/// Reset value of the RWNXAGCEVTSAT register
#define AGC_RWNXAGCEVTSAT_RESET 0x05044804
/**
* @brief Returns the current value of the RWNXAGCEVTSAT register.
* The RWNXAGCEVTSAT register will be read and its value returned.
* @return The current value of the RWNXAGCEVTSAT register.
*/
__INLINE uint32_t agc_rwnxagcevtsat_get(void)
{
return REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR);
}
/**
* @brief Sets the RWNXAGCEVTSAT register to a value.
* The RWNXAGCEVTSAT register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcevtsat_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCEVTSAT_ADDR, value);
}
// field definitions
/// EVT0OP3 field mask
#define AGC_EVT0OP3_MASK ((uint32_t)0xFC000000)
/// EVT0OP3 field LSB position
#define AGC_EVT0OP3_LSB 26
/// EVT0OP3 field width
#define AGC_EVT0OP3_WIDTH ((uint32_t)0x00000006)
/// EVT0OP2 field mask
#define AGC_EVT0OP2_MASK ((uint32_t)0x03F00000)
/// EVT0OP2 field LSB position
#define AGC_EVT0OP2_LSB 20
/// EVT0OP2 field width
#define AGC_EVT0OP2_WIDTH ((uint32_t)0x00000006)
/// EVT0OP1 field mask
#define AGC_EVT0OP1_MASK ((uint32_t)0x000FC000)
/// EVT0OP1 field LSB position
#define AGC_EVT0OP1_LSB 14
/// EVT0OP1 field width
#define AGC_EVT0OP1_WIDTH ((uint32_t)0x00000006)
/// EVT0PATHCOMB field bit
#define AGC_EVT0PATHCOMB_BIT ((uint32_t)0x00002000)
/// EVT0PATHCOMB field position
#define AGC_EVT0PATHCOMB_POS 13
/// EVT0OPCOMB field mask
#define AGC_EVT0OPCOMB_MASK ((uint32_t)0x00001800)
/// EVT0OPCOMB field LSB position
#define AGC_EVT0OPCOMB_LSB 11
/// EVT0OPCOMB field width
#define AGC_EVT0OPCOMB_WIDTH ((uint32_t)0x00000002)
/// EVT0TGTADD field mask
#define AGC_EVT0TGTADD_MASK ((uint32_t)0x000007FF)
/// EVT0TGTADD field LSB position
#define AGC_EVT0TGTADD_LSB 0
/// EVT0TGTADD field width
#define AGC_EVT0TGTADD_WIDTH ((uint32_t)0x0000000B)
/// EVT0OP3 field reset value
#define AGC_EVT0OP3_RST 0x1
/// EVT0OP2 field reset value
#define AGC_EVT0OP2_RST 0x10
/// EVT0OP1 field reset value
#define AGC_EVT0OP1_RST 0x11
/// EVT0PATHCOMB field reset value
#define AGC_EVT0PATHCOMB_RST 0x0
/// EVT0OPCOMB field reset value
#define AGC_EVT0OPCOMB_RST 0x1
/// EVT0TGTADD field reset value
#define AGC_EVT0TGTADD_RST 0x4
/**
* @brief Constructs a value for the RWNXAGCEVTSAT register given values for its fields
* and writes the value to the register.
*
* @param[in] evt0op3 - The value to use for the EVT0OP3 field.
* @param[in] evt0op2 - The value to use for the EVT0OP2 field.
* @param[in] evt0op1 - The value to use for the EVT0OP1 field.
* @param[in] evt0pathcomb - The value to use for the EVT0PATHCOMB field.
* @param[in] evt0opcomb - The value to use for the EVT0OPCOMB field.
* @param[in] evt0tgtadd - The value to use for the EVT0TGTADD field.
*/
__INLINE void agc_rwnxagcevtsat_pack(uint8_t evt0op3, uint8_t evt0op2, uint8_t evt0op1, uint8_t evt0pathcomb, uint8_t evt0opcomb, uint16_t evt0tgtadd)
{
ASSERT_ERR((((uint32_t)evt0op3 << 26) & ~((uint32_t)0xFC000000)) == 0);
ASSERT_ERR((((uint32_t)evt0op2 << 20) & ~((uint32_t)0x03F00000)) == 0);
ASSERT_ERR((((uint32_t)evt0op1 << 14) & ~((uint32_t)0x000FC000)) == 0);
ASSERT_ERR((((uint32_t)evt0pathcomb << 13) & ~((uint32_t)0x00002000)) == 0);
ASSERT_ERR((((uint32_t)evt0opcomb << 11) & ~((uint32_t)0x00001800)) == 0);
ASSERT_ERR((((uint32_t)evt0tgtadd << 0) & ~((uint32_t)0x000007FF)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTSAT_ADDR, ((uint32_t)evt0op3 << 26) | ((uint32_t)evt0op2 << 20) | ((uint32_t)evt0op1 << 14) | ((uint32_t)evt0pathcomb << 13) | ((uint32_t)evt0opcomb << 11) | ((uint32_t)evt0tgtadd << 0));
}
/**
* @brief Unpacks RWNXAGCEVTSAT's fields from current value of the RWNXAGCEVTSAT register.
*
* Reads the RWNXAGCEVTSAT register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] evt0op3 - Will be populated with the current value of this field from the register.
* @param[out] evt0op2 - Will be populated with the current value of this field from the register.
* @param[out] evt0op1 - Will be populated with the current value of this field from the register.
* @param[out] evt0pathcomb - Will be populated with the current value of this field from the register.
* @param[out] evt0opcomb - Will be populated with the current value of this field from the register.
* @param[out] evt0tgtadd - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcevtsat_unpack(uint8_t *evt0op3, uint8_t *evt0op2, uint8_t *evt0op1, uint8_t *evt0pathcomb, uint8_t *evt0opcomb, uint16_t *evt0tgtadd)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR);
*evt0op3 = (localVal & ((uint32_t)0xFC000000)) >> 26;
*evt0op2 = (localVal & ((uint32_t)0x03F00000)) >> 20;
*evt0op1 = (localVal & ((uint32_t)0x000FC000)) >> 14;
*evt0pathcomb = (localVal & ((uint32_t)0x00002000)) >> 13;
*evt0opcomb = (localVal & ((uint32_t)0x00001800)) >> 11;
*evt0tgtadd = (localVal & ((uint32_t)0x000007FF)) >> 0;
}
/**
* @brief Returns the current value of the EVT0OP3 field in the RWNXAGCEVTSAT register.
*
* The RWNXAGCEVTSAT register will be read and the EVT0OP3 field's value will be returned.
*
* @return The current value of the EVT0OP3 field in the RWNXAGCEVTSAT register.
*/
__INLINE uint8_t agc_evt0op3_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR);
return ((localVal & ((uint32_t)0xFC000000)) >> 26);
}
/**
* @brief Sets the EVT0OP3 field of the RWNXAGCEVTSAT register.
*
* The RWNXAGCEVTSAT register will be read, modified to contain the new field value, and written.
*
* @param[in] evt0op3 - The value to set the field to.
*/
__INLINE void agc_evt0op3_setf(uint8_t evt0op3)
{
ASSERT_ERR((((uint32_t)evt0op3 << 26) & ~((uint32_t)0xFC000000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTSAT_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR) & ~((uint32_t)0xFC000000)) | ((uint32_t)evt0op3 << 26));
}
/**
* @brief Returns the current value of the EVT0OP2 field in the RWNXAGCEVTSAT register.
*
* The RWNXAGCEVTSAT register will be read and the EVT0OP2 field's value will be returned.
*
* @return The current value of the EVT0OP2 field in the RWNXAGCEVTSAT register.
*/
__INLINE uint8_t agc_evt0op2_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR);
return ((localVal & ((uint32_t)0x03F00000)) >> 20);
}
/**
* @brief Sets the EVT0OP2 field of the RWNXAGCEVTSAT register.
*
* The RWNXAGCEVTSAT register will be read, modified to contain the new field value, and written.
*
* @param[in] evt0op2 - The value to set the field to.
*/
__INLINE void agc_evt0op2_setf(uint8_t evt0op2)
{
ASSERT_ERR((((uint32_t)evt0op2 << 20) & ~((uint32_t)0x03F00000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTSAT_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR) & ~((uint32_t)0x03F00000)) | ((uint32_t)evt0op2 << 20));
}
/**
* @brief Returns the current value of the EVT0OP1 field in the RWNXAGCEVTSAT register.
*
* The RWNXAGCEVTSAT register will be read and the EVT0OP1 field's value will be returned.
*
* @return The current value of the EVT0OP1 field in the RWNXAGCEVTSAT register.
*/
__INLINE uint8_t agc_evt0op1_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR);
return ((localVal & ((uint32_t)0x000FC000)) >> 14);
}
/**
* @brief Sets the EVT0OP1 field of the RWNXAGCEVTSAT register.
*
* The RWNXAGCEVTSAT register will be read, modified to contain the new field value, and written.
*
* @param[in] evt0op1 - The value to set the field to.
*/
__INLINE void agc_evt0op1_setf(uint8_t evt0op1)
{
ASSERT_ERR((((uint32_t)evt0op1 << 14) & ~((uint32_t)0x000FC000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTSAT_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR) & ~((uint32_t)0x000FC000)) | ((uint32_t)evt0op1 << 14));
}
/**
* @brief Returns the current value of the EVT0PATHCOMB field in the RWNXAGCEVTSAT register.
*
* The RWNXAGCEVTSAT register will be read and the EVT0PATHCOMB field's value will be returned.
*
* @return The current value of the EVT0PATHCOMB field in the RWNXAGCEVTSAT register.
*/
__INLINE uint8_t agc_evt0pathcomb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR);
return ((localVal & ((uint32_t)0x00002000)) >> 13);
}
/**
* @brief Sets the EVT0PATHCOMB field of the RWNXAGCEVTSAT register.
*
* The RWNXAGCEVTSAT register will be read, modified to contain the new field value, and written.
*
* @param[in] evt0pathcomb - The value to set the field to.
*/
__INLINE void agc_evt0pathcomb_setf(uint8_t evt0pathcomb)
{
ASSERT_ERR((((uint32_t)evt0pathcomb << 13) & ~((uint32_t)0x00002000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTSAT_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR) & ~((uint32_t)0x00002000)) | ((uint32_t)evt0pathcomb << 13));
}
/**
* @brief Returns the current value of the EVT0OPCOMB field in the RWNXAGCEVTSAT register.
*
* The RWNXAGCEVTSAT register will be read and the EVT0OPCOMB field's value will be returned.
*
* @return The current value of the EVT0OPCOMB field in the RWNXAGCEVTSAT register.
*/
__INLINE uint8_t agc_evt0opcomb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR);
return ((localVal & ((uint32_t)0x00001800)) >> 11);
}
/**
* @brief Sets the EVT0OPCOMB field of the RWNXAGCEVTSAT register.
*
* The RWNXAGCEVTSAT register will be read, modified to contain the new field value, and written.
*
* @param[in] evt0opcomb - The value to set the field to.
*/
__INLINE void agc_evt0opcomb_setf(uint8_t evt0opcomb)
{
ASSERT_ERR((((uint32_t)evt0opcomb << 11) & ~((uint32_t)0x00001800)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTSAT_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR) & ~((uint32_t)0x00001800)) | ((uint32_t)evt0opcomb << 11));
}
/**
* @brief Returns the current value of the EVT0TGTADD field in the RWNXAGCEVTSAT register.
*
* The RWNXAGCEVTSAT register will be read and the EVT0TGTADD field's value will be returned.
*
* @return The current value of the EVT0TGTADD field in the RWNXAGCEVTSAT register.
*/
__INLINE uint16_t agc_evt0tgtadd_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR);
return ((localVal & ((uint32_t)0x000007FF)) >> 0);
}
/**
* @brief Sets the EVT0TGTADD field of the RWNXAGCEVTSAT register.
*
* The RWNXAGCEVTSAT register will be read, modified to contain the new field value, and written.
*
* @param[in] evt0tgtadd - The value to set the field to.
*/
__INLINE void agc_evt0tgtadd_setf(uint16_t evt0tgtadd)
{
ASSERT_ERR((((uint32_t)evt0tgtadd << 0) & ~((uint32_t)0x000007FF)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTSAT_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTSAT_ADDR) & ~((uint32_t)0x000007FF)) | ((uint32_t)evt0tgtadd << 0));
}
/// @}
/**
* @name RWNXAGCEVTDET register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:26 EVT1OP3 0xF
* 25:20 EVT1OP2 0x14
* 19:14 EVT1OP1 0x12
* 13 EVT1PATHCOMB 0
* 12:11 EVT1OPCOMB 0x2
* 10:00 EVT1TGTADD 0x8
* </pre>
*
* @{
*/
/// Address of the RWNXAGCEVTDET register
#define AGC_RWNXAGCEVTDET_ADDR 0x01002054
/// Offset of the RWNXAGCEVTDET register from the base address
#define AGC_RWNXAGCEVTDET_OFFSET 0x00002054
/// Index of the RWNXAGCEVTDET register
#define AGC_RWNXAGCEVTDET_INDEX 0x00000815
/// Reset value of the RWNXAGCEVTDET register
#define AGC_RWNXAGCEVTDET_RESET 0x3D449008
/**
* @brief Returns the current value of the RWNXAGCEVTDET register.
* The RWNXAGCEVTDET register will be read and its value returned.
* @return The current value of the RWNXAGCEVTDET register.
*/
__INLINE uint32_t agc_rwnxagcevtdet_get(void)
{
return REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR);
}
/**
* @brief Sets the RWNXAGCEVTDET register to a value.
* The RWNXAGCEVTDET register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcevtdet_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCEVTDET_ADDR, value);
}
// field definitions
/// EVT1OP3 field mask
#define AGC_EVT1OP3_MASK ((uint32_t)0xFC000000)
/// EVT1OP3 field LSB position
#define AGC_EVT1OP3_LSB 26
/// EVT1OP3 field width
#define AGC_EVT1OP3_WIDTH ((uint32_t)0x00000006)
/// EVT1OP2 field mask
#define AGC_EVT1OP2_MASK ((uint32_t)0x03F00000)
/// EVT1OP2 field LSB position
#define AGC_EVT1OP2_LSB 20
/// EVT1OP2 field width
#define AGC_EVT1OP2_WIDTH ((uint32_t)0x00000006)
/// EVT1OP1 field mask
#define AGC_EVT1OP1_MASK ((uint32_t)0x000FC000)
/// EVT1OP1 field LSB position
#define AGC_EVT1OP1_LSB 14
/// EVT1OP1 field width
#define AGC_EVT1OP1_WIDTH ((uint32_t)0x00000006)
/// EVT1PATHCOMB field bit
#define AGC_EVT1PATHCOMB_BIT ((uint32_t)0x00002000)
/// EVT1PATHCOMB field position
#define AGC_EVT1PATHCOMB_POS 13
/// EVT1OPCOMB field mask
#define AGC_EVT1OPCOMB_MASK ((uint32_t)0x00001800)
/// EVT1OPCOMB field LSB position
#define AGC_EVT1OPCOMB_LSB 11
/// EVT1OPCOMB field width
#define AGC_EVT1OPCOMB_WIDTH ((uint32_t)0x00000002)
/// EVT1TGTADD field mask
#define AGC_EVT1TGTADD_MASK ((uint32_t)0x000007FF)
/// EVT1TGTADD field LSB position
#define AGC_EVT1TGTADD_LSB 0
/// EVT1TGTADD field width
#define AGC_EVT1TGTADD_WIDTH ((uint32_t)0x0000000B)
/// EVT1OP3 field reset value
#define AGC_EVT1OP3_RST 0xF
/// EVT1OP2 field reset value
#define AGC_EVT1OP2_RST 0x14
/// EVT1OP1 field reset value
#define AGC_EVT1OP1_RST 0x12
/// EVT1PATHCOMB field reset value
#define AGC_EVT1PATHCOMB_RST 0x0
/// EVT1OPCOMB field reset value
#define AGC_EVT1OPCOMB_RST 0x2
/// EVT1TGTADD field reset value
#define AGC_EVT1TGTADD_RST 0x8
/**
* @brief Constructs a value for the RWNXAGCEVTDET register given values for its fields
* and writes the value to the register.
*
* @param[in] evt1op3 - The value to use for the EVT1OP3 field.
* @param[in] evt1op2 - The value to use for the EVT1OP2 field.
* @param[in] evt1op1 - The value to use for the EVT1OP1 field.
* @param[in] evt1pathcomb - The value to use for the EVT1PATHCOMB field.
* @param[in] evt1opcomb - The value to use for the EVT1OPCOMB field.
* @param[in] evt1tgtadd - The value to use for the EVT1TGTADD field.
*/
__INLINE void agc_rwnxagcevtdet_pack(uint8_t evt1op3, uint8_t evt1op2, uint8_t evt1op1, uint8_t evt1pathcomb, uint8_t evt1opcomb, uint16_t evt1tgtadd)
{
ASSERT_ERR((((uint32_t)evt1op3 << 26) & ~((uint32_t)0xFC000000)) == 0);
ASSERT_ERR((((uint32_t)evt1op2 << 20) & ~((uint32_t)0x03F00000)) == 0);
ASSERT_ERR((((uint32_t)evt1op1 << 14) & ~((uint32_t)0x000FC000)) == 0);
ASSERT_ERR((((uint32_t)evt1pathcomb << 13) & ~((uint32_t)0x00002000)) == 0);
ASSERT_ERR((((uint32_t)evt1opcomb << 11) & ~((uint32_t)0x00001800)) == 0);
ASSERT_ERR((((uint32_t)evt1tgtadd << 0) & ~((uint32_t)0x000007FF)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDET_ADDR, ((uint32_t)evt1op3 << 26) | ((uint32_t)evt1op2 << 20) | ((uint32_t)evt1op1 << 14) | ((uint32_t)evt1pathcomb << 13) | ((uint32_t)evt1opcomb << 11) | ((uint32_t)evt1tgtadd << 0));
}
/**
* @brief Unpacks RWNXAGCEVTDET's fields from current value of the RWNXAGCEVTDET register.
*
* Reads the RWNXAGCEVTDET register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] evt1op3 - Will be populated with the current value of this field from the register.
* @param[out] evt1op2 - Will be populated with the current value of this field from the register.
* @param[out] evt1op1 - Will be populated with the current value of this field from the register.
* @param[out] evt1pathcomb - Will be populated with the current value of this field from the register.
* @param[out] evt1opcomb - Will be populated with the current value of this field from the register.
* @param[out] evt1tgtadd - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcevtdet_unpack(uint8_t *evt1op3, uint8_t *evt1op2, uint8_t *evt1op1, uint8_t *evt1pathcomb, uint8_t *evt1opcomb, uint16_t *evt1tgtadd)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR);
*evt1op3 = (localVal & ((uint32_t)0xFC000000)) >> 26;
*evt1op2 = (localVal & ((uint32_t)0x03F00000)) >> 20;
*evt1op1 = (localVal & ((uint32_t)0x000FC000)) >> 14;
*evt1pathcomb = (localVal & ((uint32_t)0x00002000)) >> 13;
*evt1opcomb = (localVal & ((uint32_t)0x00001800)) >> 11;
*evt1tgtadd = (localVal & ((uint32_t)0x000007FF)) >> 0;
}
/**
* @brief Returns the current value of the EVT1OP3 field in the RWNXAGCEVTDET register.
*
* The RWNXAGCEVTDET register will be read and the EVT1OP3 field's value will be returned.
*
* @return The current value of the EVT1OP3 field in the RWNXAGCEVTDET register.
*/
__INLINE uint8_t agc_evt1op3_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR);
return ((localVal & ((uint32_t)0xFC000000)) >> 26);
}
/**
* @brief Sets the EVT1OP3 field of the RWNXAGCEVTDET register.
*
* The RWNXAGCEVTDET register will be read, modified to contain the new field value, and written.
*
* @param[in] evt1op3 - The value to set the field to.
*/
__INLINE void agc_evt1op3_setf(uint8_t evt1op3)
{
ASSERT_ERR((((uint32_t)evt1op3 << 26) & ~((uint32_t)0xFC000000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDET_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR) & ~((uint32_t)0xFC000000)) | ((uint32_t)evt1op3 << 26));
}
/**
* @brief Returns the current value of the EVT1OP2 field in the RWNXAGCEVTDET register.
*
* The RWNXAGCEVTDET register will be read and the EVT1OP2 field's value will be returned.
*
* @return The current value of the EVT1OP2 field in the RWNXAGCEVTDET register.
*/
__INLINE uint8_t agc_evt1op2_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR);
return ((localVal & ((uint32_t)0x03F00000)) >> 20);
}
/**
* @brief Sets the EVT1OP2 field of the RWNXAGCEVTDET register.
*
* The RWNXAGCEVTDET register will be read, modified to contain the new field value, and written.
*
* @param[in] evt1op2 - The value to set the field to.
*/
__INLINE void agc_evt1op2_setf(uint8_t evt1op2)
{
ASSERT_ERR((((uint32_t)evt1op2 << 20) & ~((uint32_t)0x03F00000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDET_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR) & ~((uint32_t)0x03F00000)) | ((uint32_t)evt1op2 << 20));
}
/**
* @brief Returns the current value of the EVT1OP1 field in the RWNXAGCEVTDET register.
*
* The RWNXAGCEVTDET register will be read and the EVT1OP1 field's value will be returned.
*
* @return The current value of the EVT1OP1 field in the RWNXAGCEVTDET register.
*/
__INLINE uint8_t agc_evt1op1_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR);
return ((localVal & ((uint32_t)0x000FC000)) >> 14);
}
/**
* @brief Sets the EVT1OP1 field of the RWNXAGCEVTDET register.
*
* The RWNXAGCEVTDET register will be read, modified to contain the new field value, and written.
*
* @param[in] evt1op1 - The value to set the field to.
*/
__INLINE void agc_evt1op1_setf(uint8_t evt1op1)
{
ASSERT_ERR((((uint32_t)evt1op1 << 14) & ~((uint32_t)0x000FC000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDET_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR) & ~((uint32_t)0x000FC000)) | ((uint32_t)evt1op1 << 14));
}
/**
* @brief Returns the current value of the EVT1PATHCOMB field in the RWNXAGCEVTDET register.
*
* The RWNXAGCEVTDET register will be read and the EVT1PATHCOMB field's value will be returned.
*
* @return The current value of the EVT1PATHCOMB field in the RWNXAGCEVTDET register.
*/
__INLINE uint8_t agc_evt1pathcomb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR);
return ((localVal & ((uint32_t)0x00002000)) >> 13);
}
/**
* @brief Sets the EVT1PATHCOMB field of the RWNXAGCEVTDET register.
*
* The RWNXAGCEVTDET register will be read, modified to contain the new field value, and written.
*
* @param[in] evt1pathcomb - The value to set the field to.
*/
__INLINE void agc_evt1pathcomb_setf(uint8_t evt1pathcomb)
{
ASSERT_ERR((((uint32_t)evt1pathcomb << 13) & ~((uint32_t)0x00002000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDET_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR) & ~((uint32_t)0x00002000)) | ((uint32_t)evt1pathcomb << 13));
}
/**
* @brief Returns the current value of the EVT1OPCOMB field in the RWNXAGCEVTDET register.
*
* The RWNXAGCEVTDET register will be read and the EVT1OPCOMB field's value will be returned.
*
* @return The current value of the EVT1OPCOMB field in the RWNXAGCEVTDET register.
*/
__INLINE uint8_t agc_evt1opcomb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR);
return ((localVal & ((uint32_t)0x00001800)) >> 11);
}
/**
* @brief Sets the EVT1OPCOMB field of the RWNXAGCEVTDET register.
*
* The RWNXAGCEVTDET register will be read, modified to contain the new field value, and written.
*
* @param[in] evt1opcomb - The value to set the field to.
*/
__INLINE void agc_evt1opcomb_setf(uint8_t evt1opcomb)
{
ASSERT_ERR((((uint32_t)evt1opcomb << 11) & ~((uint32_t)0x00001800)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDET_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR) & ~((uint32_t)0x00001800)) | ((uint32_t)evt1opcomb << 11));
}
/**
* @brief Returns the current value of the EVT1TGTADD field in the RWNXAGCEVTDET register.
*
* The RWNXAGCEVTDET register will be read and the EVT1TGTADD field's value will be returned.
*
* @return The current value of the EVT1TGTADD field in the RWNXAGCEVTDET register.
*/
__INLINE uint16_t agc_evt1tgtadd_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR);
return ((localVal & ((uint32_t)0x000007FF)) >> 0);
}
/**
* @brief Sets the EVT1TGTADD field of the RWNXAGCEVTDET register.
*
* The RWNXAGCEVTDET register will be read, modified to contain the new field value, and written.
*
* @param[in] evt1tgtadd - The value to set the field to.
*/
__INLINE void agc_evt1tgtadd_setf(uint16_t evt1tgtadd)
{
ASSERT_ERR((((uint32_t)evt1tgtadd << 0) & ~((uint32_t)0x000007FF)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDET_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDET_ADDR) & ~((uint32_t)0x000007FF)) | ((uint32_t)evt1tgtadd << 0));
}
/// @}
/**
* @name RWNXAGCEVTDIS register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:26 EVT2OP3 0xE
* 25:20 EVT2OP2 0x15
* 19:14 EVT2OP1 0x16
* 13 EVT2PATHCOMB 0
* 12:11 EVT2OPCOMB 0x2
* 10:00 EVT2TGTADD 0xB
* </pre>
*
* @{
*/
/// Address of the RWNXAGCEVTDIS register
#define AGC_RWNXAGCEVTDIS_ADDR 0x01002058
/// Offset of the RWNXAGCEVTDIS register from the base address
#define AGC_RWNXAGCEVTDIS_OFFSET 0x00002058
/// Index of the RWNXAGCEVTDIS register
#define AGC_RWNXAGCEVTDIS_INDEX 0x00000816
/// Reset value of the RWNXAGCEVTDIS register
#define AGC_RWNXAGCEVTDIS_RESET 0x3955900B
/**
* @brief Returns the current value of the RWNXAGCEVTDIS register.
* The RWNXAGCEVTDIS register will be read and its value returned.
* @return The current value of the RWNXAGCEVTDIS register.
*/
__INLINE uint32_t agc_rwnxagcevtdis_get(void)
{
return REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR);
}
/**
* @brief Sets the RWNXAGCEVTDIS register to a value.
* The RWNXAGCEVTDIS register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcevtdis_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCEVTDIS_ADDR, value);
}
// field definitions
/// EVT2OP3 field mask
#define AGC_EVT2OP3_MASK ((uint32_t)0xFC000000)
/// EVT2OP3 field LSB position
#define AGC_EVT2OP3_LSB 26
/// EVT2OP3 field width
#define AGC_EVT2OP3_WIDTH ((uint32_t)0x00000006)
/// EVT2OP2 field mask
#define AGC_EVT2OP2_MASK ((uint32_t)0x03F00000)
/// EVT2OP2 field LSB position
#define AGC_EVT2OP2_LSB 20
/// EVT2OP2 field width
#define AGC_EVT2OP2_WIDTH ((uint32_t)0x00000006)
/// EVT2OP1 field mask
#define AGC_EVT2OP1_MASK ((uint32_t)0x000FC000)
/// EVT2OP1 field LSB position
#define AGC_EVT2OP1_LSB 14
/// EVT2OP1 field width
#define AGC_EVT2OP1_WIDTH ((uint32_t)0x00000006)
/// EVT2PATHCOMB field bit
#define AGC_EVT2PATHCOMB_BIT ((uint32_t)0x00002000)
/// EVT2PATHCOMB field position
#define AGC_EVT2PATHCOMB_POS 13
/// EVT2OPCOMB field mask
#define AGC_EVT2OPCOMB_MASK ((uint32_t)0x00001800)
/// EVT2OPCOMB field LSB position
#define AGC_EVT2OPCOMB_LSB 11
/// EVT2OPCOMB field width
#define AGC_EVT2OPCOMB_WIDTH ((uint32_t)0x00000002)
/// EVT2TGTADD field mask
#define AGC_EVT2TGTADD_MASK ((uint32_t)0x000007FF)
/// EVT2TGTADD field LSB position
#define AGC_EVT2TGTADD_LSB 0
/// EVT2TGTADD field width
#define AGC_EVT2TGTADD_WIDTH ((uint32_t)0x0000000B)
/// EVT2OP3 field reset value
#define AGC_EVT2OP3_RST 0xE
/// EVT2OP2 field reset value
#define AGC_EVT2OP2_RST 0x15
/// EVT2OP1 field reset value
#define AGC_EVT2OP1_RST 0x16
/// EVT2PATHCOMB field reset value
#define AGC_EVT2PATHCOMB_RST 0x0
/// EVT2OPCOMB field reset value
#define AGC_EVT2OPCOMB_RST 0x2
/// EVT2TGTADD field reset value
#define AGC_EVT2TGTADD_RST 0xB
/**
* @brief Constructs a value for the RWNXAGCEVTDIS register given values for its fields
* and writes the value to the register.
*
* @param[in] evt2op3 - The value to use for the EVT2OP3 field.
* @param[in] evt2op2 - The value to use for the EVT2OP2 field.
* @param[in] evt2op1 - The value to use for the EVT2OP1 field.
* @param[in] evt2pathcomb - The value to use for the EVT2PATHCOMB field.
* @param[in] evt2opcomb - The value to use for the EVT2OPCOMB field.
* @param[in] evt2tgtadd - The value to use for the EVT2TGTADD field.
*/
__INLINE void agc_rwnxagcevtdis_pack(uint8_t evt2op3, uint8_t evt2op2, uint8_t evt2op1, uint8_t evt2pathcomb, uint8_t evt2opcomb, uint16_t evt2tgtadd)
{
ASSERT_ERR((((uint32_t)evt2op3 << 26) & ~((uint32_t)0xFC000000)) == 0);
ASSERT_ERR((((uint32_t)evt2op2 << 20) & ~((uint32_t)0x03F00000)) == 0);
ASSERT_ERR((((uint32_t)evt2op1 << 14) & ~((uint32_t)0x000FC000)) == 0);
ASSERT_ERR((((uint32_t)evt2pathcomb << 13) & ~((uint32_t)0x00002000)) == 0);
ASSERT_ERR((((uint32_t)evt2opcomb << 11) & ~((uint32_t)0x00001800)) == 0);
ASSERT_ERR((((uint32_t)evt2tgtadd << 0) & ~((uint32_t)0x000007FF)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDIS_ADDR, ((uint32_t)evt2op3 << 26) | ((uint32_t)evt2op2 << 20) | ((uint32_t)evt2op1 << 14) | ((uint32_t)evt2pathcomb << 13) | ((uint32_t)evt2opcomb << 11) | ((uint32_t)evt2tgtadd << 0));
}
/**
* @brief Unpacks RWNXAGCEVTDIS's fields from current value of the RWNXAGCEVTDIS register.
*
* Reads the RWNXAGCEVTDIS register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] evt2op3 - Will be populated with the current value of this field from the register.
* @param[out] evt2op2 - Will be populated with the current value of this field from the register.
* @param[out] evt2op1 - Will be populated with the current value of this field from the register.
* @param[out] evt2pathcomb - Will be populated with the current value of this field from the register.
* @param[out] evt2opcomb - Will be populated with the current value of this field from the register.
* @param[out] evt2tgtadd - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcevtdis_unpack(uint8_t *evt2op3, uint8_t *evt2op2, uint8_t *evt2op1, uint8_t *evt2pathcomb, uint8_t *evt2opcomb, uint16_t *evt2tgtadd)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR);
*evt2op3 = (localVal & ((uint32_t)0xFC000000)) >> 26;
*evt2op2 = (localVal & ((uint32_t)0x03F00000)) >> 20;
*evt2op1 = (localVal & ((uint32_t)0x000FC000)) >> 14;
*evt2pathcomb = (localVal & ((uint32_t)0x00002000)) >> 13;
*evt2opcomb = (localVal & ((uint32_t)0x00001800)) >> 11;
*evt2tgtadd = (localVal & ((uint32_t)0x000007FF)) >> 0;
}
/**
* @brief Returns the current value of the EVT2OP3 field in the RWNXAGCEVTDIS register.
*
* The RWNXAGCEVTDIS register will be read and the EVT2OP3 field's value will be returned.
*
* @return The current value of the EVT2OP3 field in the RWNXAGCEVTDIS register.
*/
__INLINE uint8_t agc_evt2op3_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR);
return ((localVal & ((uint32_t)0xFC000000)) >> 26);
}
/**
* @brief Sets the EVT2OP3 field of the RWNXAGCEVTDIS register.
*
* The RWNXAGCEVTDIS register will be read, modified to contain the new field value, and written.
*
* @param[in] evt2op3 - The value to set the field to.
*/
__INLINE void agc_evt2op3_setf(uint8_t evt2op3)
{
ASSERT_ERR((((uint32_t)evt2op3 << 26) & ~((uint32_t)0xFC000000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDIS_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR) & ~((uint32_t)0xFC000000)) | ((uint32_t)evt2op3 << 26));
}
/**
* @brief Returns the current value of the EVT2OP2 field in the RWNXAGCEVTDIS register.
*
* The RWNXAGCEVTDIS register will be read and the EVT2OP2 field's value will be returned.
*
* @return The current value of the EVT2OP2 field in the RWNXAGCEVTDIS register.
*/
__INLINE uint8_t agc_evt2op2_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR);
return ((localVal & ((uint32_t)0x03F00000)) >> 20);
}
/**
* @brief Sets the EVT2OP2 field of the RWNXAGCEVTDIS register.
*
* The RWNXAGCEVTDIS register will be read, modified to contain the new field value, and written.
*
* @param[in] evt2op2 - The value to set the field to.
*/
__INLINE void agc_evt2op2_setf(uint8_t evt2op2)
{
ASSERT_ERR((((uint32_t)evt2op2 << 20) & ~((uint32_t)0x03F00000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDIS_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR) & ~((uint32_t)0x03F00000)) | ((uint32_t)evt2op2 << 20));
}
/**
* @brief Returns the current value of the EVT2OP1 field in the RWNXAGCEVTDIS register.
*
* The RWNXAGCEVTDIS register will be read and the EVT2OP1 field's value will be returned.
*
* @return The current value of the EVT2OP1 field in the RWNXAGCEVTDIS register.
*/
__INLINE uint8_t agc_evt2op1_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR);
return ((localVal & ((uint32_t)0x000FC000)) >> 14);
}
/**
* @brief Sets the EVT2OP1 field of the RWNXAGCEVTDIS register.
*
* The RWNXAGCEVTDIS register will be read, modified to contain the new field value, and written.
*
* @param[in] evt2op1 - The value to set the field to.
*/
__INLINE void agc_evt2op1_setf(uint8_t evt2op1)
{
ASSERT_ERR((((uint32_t)evt2op1 << 14) & ~((uint32_t)0x000FC000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDIS_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR) & ~((uint32_t)0x000FC000)) | ((uint32_t)evt2op1 << 14));
}
/**
* @brief Returns the current value of the EVT2PATHCOMB field in the RWNXAGCEVTDIS register.
*
* The RWNXAGCEVTDIS register will be read and the EVT2PATHCOMB field's value will be returned.
*
* @return The current value of the EVT2PATHCOMB field in the RWNXAGCEVTDIS register.
*/
__INLINE uint8_t agc_evt2pathcomb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR);
return ((localVal & ((uint32_t)0x00002000)) >> 13);
}
/**
* @brief Sets the EVT2PATHCOMB field of the RWNXAGCEVTDIS register.
*
* The RWNXAGCEVTDIS register will be read, modified to contain the new field value, and written.
*
* @param[in] evt2pathcomb - The value to set the field to.
*/
__INLINE void agc_evt2pathcomb_setf(uint8_t evt2pathcomb)
{
ASSERT_ERR((((uint32_t)evt2pathcomb << 13) & ~((uint32_t)0x00002000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDIS_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR) & ~((uint32_t)0x00002000)) | ((uint32_t)evt2pathcomb << 13));
}
/**
* @brief Returns the current value of the EVT2OPCOMB field in the RWNXAGCEVTDIS register.
*
* The RWNXAGCEVTDIS register will be read and the EVT2OPCOMB field's value will be returned.
*
* @return The current value of the EVT2OPCOMB field in the RWNXAGCEVTDIS register.
*/
__INLINE uint8_t agc_evt2opcomb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR);
return ((localVal & ((uint32_t)0x00001800)) >> 11);
}
/**
* @brief Sets the EVT2OPCOMB field of the RWNXAGCEVTDIS register.
*
* The RWNXAGCEVTDIS register will be read, modified to contain the new field value, and written.
*
* @param[in] evt2opcomb - The value to set the field to.
*/
__INLINE void agc_evt2opcomb_setf(uint8_t evt2opcomb)
{
ASSERT_ERR((((uint32_t)evt2opcomb << 11) & ~((uint32_t)0x00001800)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDIS_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR) & ~((uint32_t)0x00001800)) | ((uint32_t)evt2opcomb << 11));
}
/**
* @brief Returns the current value of the EVT2TGTADD field in the RWNXAGCEVTDIS register.
*
* The RWNXAGCEVTDIS register will be read and the EVT2TGTADD field's value will be returned.
*
* @return The current value of the EVT2TGTADD field in the RWNXAGCEVTDIS register.
*/
__INLINE uint16_t agc_evt2tgtadd_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR);
return ((localVal & ((uint32_t)0x000007FF)) >> 0);
}
/**
* @brief Sets the EVT2TGTADD field of the RWNXAGCEVTDIS register.
*
* The RWNXAGCEVTDIS register will be read, modified to contain the new field value, and written.
*
* @param[in] evt2tgtadd - The value to set the field to.
*/
__INLINE void agc_evt2tgtadd_setf(uint16_t evt2tgtadd)
{
ASSERT_ERR((((uint32_t)evt2tgtadd << 0) & ~((uint32_t)0x000007FF)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDIS_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDIS_ADDR) & ~((uint32_t)0x000007FF)) | ((uint32_t)evt2tgtadd << 0));
}
/// @}
/**
* @name RWNXAGCEVTDSSSDET register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:26 EVT3OP3 0x1
* 25:20 EVT3OP2 0xF
* 19:14 EVT3OP1 0x1D
* 13 EVT3PATHCOMB 0
* 12:11 EVT3OPCOMB 0x1
* 10:00 EVT3TGTADD 0xF
* </pre>
*
* @{
*/
/// Address of the RWNXAGCEVTDSSSDET register
#define AGC_RWNXAGCEVTDSSSDET_ADDR 0x0100205C
/// Offset of the RWNXAGCEVTDSSSDET register from the base address
#define AGC_RWNXAGCEVTDSSSDET_OFFSET 0x0000205C
/// Index of the RWNXAGCEVTDSSSDET register
#define AGC_RWNXAGCEVTDSSSDET_INDEX 0x00000817
/// Reset value of the RWNXAGCEVTDSSSDET register
#define AGC_RWNXAGCEVTDSSSDET_RESET 0x04F7480F
/**
* @brief Returns the current value of the RWNXAGCEVTDSSSDET register.
* The RWNXAGCEVTDSSSDET register will be read and its value returned.
* @return The current value of the RWNXAGCEVTDSSSDET register.
*/
__INLINE uint32_t agc_rwnxagcevtdsssdet_get(void)
{
return REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR);
}
/**
* @brief Sets the RWNXAGCEVTDSSSDET register to a value.
* The RWNXAGCEVTDSSSDET register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcevtdsssdet_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCEVTDSSSDET_ADDR, value);
}
// field definitions
/// EVT3OP3 field mask
#define AGC_EVT3OP3_MASK ((uint32_t)0xFC000000)
/// EVT3OP3 field LSB position
#define AGC_EVT3OP3_LSB 26
/// EVT3OP3 field width
#define AGC_EVT3OP3_WIDTH ((uint32_t)0x00000006)
/// EVT3OP2 field mask
#define AGC_EVT3OP2_MASK ((uint32_t)0x03F00000)
/// EVT3OP2 field LSB position
#define AGC_EVT3OP2_LSB 20
/// EVT3OP2 field width
#define AGC_EVT3OP2_WIDTH ((uint32_t)0x00000006)
/// EVT3OP1 field mask
#define AGC_EVT3OP1_MASK ((uint32_t)0x000FC000)
/// EVT3OP1 field LSB position
#define AGC_EVT3OP1_LSB 14
/// EVT3OP1 field width
#define AGC_EVT3OP1_WIDTH ((uint32_t)0x00000006)
/// EVT3PATHCOMB field bit
#define AGC_EVT3PATHCOMB_BIT ((uint32_t)0x00002000)
/// EVT3PATHCOMB field position
#define AGC_EVT3PATHCOMB_POS 13
/// EVT3OPCOMB field mask
#define AGC_EVT3OPCOMB_MASK ((uint32_t)0x00001800)
/// EVT3OPCOMB field LSB position
#define AGC_EVT3OPCOMB_LSB 11
/// EVT3OPCOMB field width
#define AGC_EVT3OPCOMB_WIDTH ((uint32_t)0x00000002)
/// EVT3TGTADD field mask
#define AGC_EVT3TGTADD_MASK ((uint32_t)0x000007FF)
/// EVT3TGTADD field LSB position
#define AGC_EVT3TGTADD_LSB 0
/// EVT3TGTADD field width
#define AGC_EVT3TGTADD_WIDTH ((uint32_t)0x0000000B)
/// EVT3OP3 field reset value
#define AGC_EVT3OP3_RST 0x1
/// EVT3OP2 field reset value
#define AGC_EVT3OP2_RST 0xF
/// EVT3OP1 field reset value
#define AGC_EVT3OP1_RST 0x1D
/// EVT3PATHCOMB field reset value
#define AGC_EVT3PATHCOMB_RST 0x0
/// EVT3OPCOMB field reset value
#define AGC_EVT3OPCOMB_RST 0x1
/// EVT3TGTADD field reset value
#define AGC_EVT3TGTADD_RST 0xF
/**
* @brief Constructs a value for the RWNXAGCEVTDSSSDET register given values for its fields
* and writes the value to the register.
*
* @param[in] evt3op3 - The value to use for the EVT3OP3 field.
* @param[in] evt3op2 - The value to use for the EVT3OP2 field.
* @param[in] evt3op1 - The value to use for the EVT3OP1 field.
* @param[in] evt3pathcomb - The value to use for the EVT3PATHCOMB field.
* @param[in] evt3opcomb - The value to use for the EVT3OPCOMB field.
* @param[in] evt3tgtadd - The value to use for the EVT3TGTADD field.
*/
__INLINE void agc_rwnxagcevtdsssdet_pack(uint8_t evt3op3, uint8_t evt3op2, uint8_t evt3op1, uint8_t evt3pathcomb, uint8_t evt3opcomb, uint16_t evt3tgtadd)
{
ASSERT_ERR((((uint32_t)evt3op3 << 26) & ~((uint32_t)0xFC000000)) == 0);
ASSERT_ERR((((uint32_t)evt3op2 << 20) & ~((uint32_t)0x03F00000)) == 0);
ASSERT_ERR((((uint32_t)evt3op1 << 14) & ~((uint32_t)0x000FC000)) == 0);
ASSERT_ERR((((uint32_t)evt3pathcomb << 13) & ~((uint32_t)0x00002000)) == 0);
ASSERT_ERR((((uint32_t)evt3opcomb << 11) & ~((uint32_t)0x00001800)) == 0);
ASSERT_ERR((((uint32_t)evt3tgtadd << 0) & ~((uint32_t)0x000007FF)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDSSSDET_ADDR, ((uint32_t)evt3op3 << 26) | ((uint32_t)evt3op2 << 20) | ((uint32_t)evt3op1 << 14) | ((uint32_t)evt3pathcomb << 13) | ((uint32_t)evt3opcomb << 11) | ((uint32_t)evt3tgtadd << 0));
}
/**
* @brief Unpacks RWNXAGCEVTDSSSDET's fields from current value of the RWNXAGCEVTDSSSDET register.
*
* Reads the RWNXAGCEVTDSSSDET register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] evt3op3 - Will be populated with the current value of this field from the register.
* @param[out] evt3op2 - Will be populated with the current value of this field from the register.
* @param[out] evt3op1 - Will be populated with the current value of this field from the register.
* @param[out] evt3pathcomb - Will be populated with the current value of this field from the register.
* @param[out] evt3opcomb - Will be populated with the current value of this field from the register.
* @param[out] evt3tgtadd - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcevtdsssdet_unpack(uint8_t *evt3op3, uint8_t *evt3op2, uint8_t *evt3op1, uint8_t *evt3pathcomb, uint8_t *evt3opcomb, uint16_t *evt3tgtadd)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR);
*evt3op3 = (localVal & ((uint32_t)0xFC000000)) >> 26;
*evt3op2 = (localVal & ((uint32_t)0x03F00000)) >> 20;
*evt3op1 = (localVal & ((uint32_t)0x000FC000)) >> 14;
*evt3pathcomb = (localVal & ((uint32_t)0x00002000)) >> 13;
*evt3opcomb = (localVal & ((uint32_t)0x00001800)) >> 11;
*evt3tgtadd = (localVal & ((uint32_t)0x000007FF)) >> 0;
}
/**
* @brief Returns the current value of the EVT3OP3 field in the RWNXAGCEVTDSSSDET register.
*
* The RWNXAGCEVTDSSSDET register will be read and the EVT3OP3 field's value will be returned.
*
* @return The current value of the EVT3OP3 field in the RWNXAGCEVTDSSSDET register.
*/
__INLINE uint8_t agc_evt3op3_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR);
return ((localVal & ((uint32_t)0xFC000000)) >> 26);
}
/**
* @brief Sets the EVT3OP3 field of the RWNXAGCEVTDSSSDET register.
*
* The RWNXAGCEVTDSSSDET register will be read, modified to contain the new field value, and written.
*
* @param[in] evt3op3 - The value to set the field to.
*/
__INLINE void agc_evt3op3_setf(uint8_t evt3op3)
{
ASSERT_ERR((((uint32_t)evt3op3 << 26) & ~((uint32_t)0xFC000000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDSSSDET_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR) & ~((uint32_t)0xFC000000)) | ((uint32_t)evt3op3 << 26));
}
/**
* @brief Returns the current value of the EVT3OP2 field in the RWNXAGCEVTDSSSDET register.
*
* The RWNXAGCEVTDSSSDET register will be read and the EVT3OP2 field's value will be returned.
*
* @return The current value of the EVT3OP2 field in the RWNXAGCEVTDSSSDET register.
*/
__INLINE uint8_t agc_evt3op2_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR);
return ((localVal & ((uint32_t)0x03F00000)) >> 20);
}
/**
* @brief Sets the EVT3OP2 field of the RWNXAGCEVTDSSSDET register.
*
* The RWNXAGCEVTDSSSDET register will be read, modified to contain the new field value, and written.
*
* @param[in] evt3op2 - The value to set the field to.
*/
__INLINE void agc_evt3op2_setf(uint8_t evt3op2)
{
ASSERT_ERR((((uint32_t)evt3op2 << 20) & ~((uint32_t)0x03F00000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDSSSDET_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR) & ~((uint32_t)0x03F00000)) | ((uint32_t)evt3op2 << 20));
}
/**
* @brief Returns the current value of the EVT3OP1 field in the RWNXAGCEVTDSSSDET register.
*
* The RWNXAGCEVTDSSSDET register will be read and the EVT3OP1 field's value will be returned.
*
* @return The current value of the EVT3OP1 field in the RWNXAGCEVTDSSSDET register.
*/
__INLINE uint8_t agc_evt3op1_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR);
return ((localVal & ((uint32_t)0x000FC000)) >> 14);
}
/**
* @brief Sets the EVT3OP1 field of the RWNXAGCEVTDSSSDET register.
*
* The RWNXAGCEVTDSSSDET register will be read, modified to contain the new field value, and written.
*
* @param[in] evt3op1 - The value to set the field to.
*/
__INLINE void agc_evt3op1_setf(uint8_t evt3op1)
{
ASSERT_ERR((((uint32_t)evt3op1 << 14) & ~((uint32_t)0x000FC000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDSSSDET_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR) & ~((uint32_t)0x000FC000)) | ((uint32_t)evt3op1 << 14));
}
/**
* @brief Returns the current value of the EVT3PATHCOMB field in the RWNXAGCEVTDSSSDET register.
*
* The RWNXAGCEVTDSSSDET register will be read and the EVT3PATHCOMB field's value will be returned.
*
* @return The current value of the EVT3PATHCOMB field in the RWNXAGCEVTDSSSDET register.
*/
__INLINE uint8_t agc_evt3pathcomb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR);
return ((localVal & ((uint32_t)0x00002000)) >> 13);
}
/**
* @brief Sets the EVT3PATHCOMB field of the RWNXAGCEVTDSSSDET register.
*
* The RWNXAGCEVTDSSSDET register will be read, modified to contain the new field value, and written.
*
* @param[in] evt3pathcomb - The value to set the field to.
*/
__INLINE void agc_evt3pathcomb_setf(uint8_t evt3pathcomb)
{
ASSERT_ERR((((uint32_t)evt3pathcomb << 13) & ~((uint32_t)0x00002000)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDSSSDET_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR) & ~((uint32_t)0x00002000)) | ((uint32_t)evt3pathcomb << 13));
}
/**
* @brief Returns the current value of the EVT3OPCOMB field in the RWNXAGCEVTDSSSDET register.
*
* The RWNXAGCEVTDSSSDET register will be read and the EVT3OPCOMB field's value will be returned.
*
* @return The current value of the EVT3OPCOMB field in the RWNXAGCEVTDSSSDET register.
*/
__INLINE uint8_t agc_evt3opcomb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR);
return ((localVal & ((uint32_t)0x00001800)) >> 11);
}
/**
* @brief Sets the EVT3OPCOMB field of the RWNXAGCEVTDSSSDET register.
*
* The RWNXAGCEVTDSSSDET register will be read, modified to contain the new field value, and written.
*
* @param[in] evt3opcomb - The value to set the field to.
*/
__INLINE void agc_evt3opcomb_setf(uint8_t evt3opcomb)
{
ASSERT_ERR((((uint32_t)evt3opcomb << 11) & ~((uint32_t)0x00001800)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDSSSDET_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR) & ~((uint32_t)0x00001800)) | ((uint32_t)evt3opcomb << 11));
}
/**
* @brief Returns the current value of the EVT3TGTADD field in the RWNXAGCEVTDSSSDET register.
*
* The RWNXAGCEVTDSSSDET register will be read and the EVT3TGTADD field's value will be returned.
*
* @return The current value of the EVT3TGTADD field in the RWNXAGCEVTDSSSDET register.
*/
__INLINE uint16_t agc_evt3tgtadd_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR);
return ((localVal & ((uint32_t)0x000007FF)) >> 0);
}
/**
* @brief Sets the EVT3TGTADD field of the RWNXAGCEVTDSSSDET register.
*
* The RWNXAGCEVTDSSSDET register will be read, modified to contain the new field value, and written.
*
* @param[in] evt3tgtadd - The value to set the field to.
*/
__INLINE void agc_evt3tgtadd_setf(uint16_t evt3tgtadd)
{
ASSERT_ERR((((uint32_t)evt3tgtadd << 0) & ~((uint32_t)0x000007FF)) == 0);
REG_PL_WR(AGC_RWNXAGCEVTDSSSDET_ADDR, (REG_PL_RD(AGC_RWNXAGCEVTDSSSDET_ADDR) & ~((uint32_t)0x000007FF)) | ((uint32_t)evt3tgtadd << 0));
}
/// @}
/**
* @name RWNXAGCCNTL register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 16 HTSTFGAINEN 1
* 12 AGCFSMRESET 0
* 11 RADARDETEN 0
* 10 RIFSDETEN 1
* 09 DSSSONLY 0
* 08 OFDMONLY 0
* 07:04 GPSTATUS 0x0
* 03:00 COMBPATHSEL 0xF
* </pre>
*
* @{
*/
/// Address of the RWNXAGCCNTL register
#define AGC_RWNXAGCCNTL_ADDR 0x01002060
/// Offset of the RWNXAGCCNTL register from the base address
#define AGC_RWNXAGCCNTL_OFFSET 0x00002060
/// Index of the RWNXAGCCNTL register
#define AGC_RWNXAGCCNTL_INDEX 0x00000818
/// Reset value of the RWNXAGCCNTL register
#define AGC_RWNXAGCCNTL_RESET 0x0001040F
/**
* @brief Returns the current value of the RWNXAGCCNTL register.
* The RWNXAGCCNTL register will be read and its value returned.
* @return The current value of the RWNXAGCCNTL register.
*/
__INLINE uint32_t agc_rwnxagccntl_get(void)
{
return REG_PL_RD(AGC_RWNXAGCCNTL_ADDR);
}
/**
* @brief Sets the RWNXAGCCNTL register to a value.
* The RWNXAGCCNTL register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagccntl_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCCNTL_ADDR, value);
}
// field definitions
/// HTSTFGAINEN field bit
#define AGC_HTSTFGAINEN_BIT ((uint32_t)0x00010000)
/// HTSTFGAINEN field position
#define AGC_HTSTFGAINEN_POS 16
/// AGCFSMRESET field bit
#define AGC_AGCFSMRESET_BIT ((uint32_t)0x00001000)
/// AGCFSMRESET field position
#define AGC_AGCFSMRESET_POS 12
/// RADARDETEN field bit
#define AGC_RADARDETEN_BIT ((uint32_t)0x00000800)
/// RADARDETEN field position
#define AGC_RADARDETEN_POS 11
/// RIFSDETEN field bit
#define AGC_RIFSDETEN_BIT ((uint32_t)0x00000400)
/// RIFSDETEN field position
#define AGC_RIFSDETEN_POS 10
/// DSSSONLY field bit
#define AGC_DSSSONLY_BIT ((uint32_t)0x00000200)
/// DSSSONLY field position
#define AGC_DSSSONLY_POS 9
/// OFDMONLY field bit
#define AGC_OFDMONLY_BIT ((uint32_t)0x00000100)
/// OFDMONLY field position
#define AGC_OFDMONLY_POS 8
/// GPSTATUS field mask
#define AGC_GPSTATUS_MASK ((uint32_t)0x000000F0)
/// GPSTATUS field LSB position
#define AGC_GPSTATUS_LSB 4
/// GPSTATUS field width
#define AGC_GPSTATUS_WIDTH ((uint32_t)0x00000004)
/// COMBPATHSEL field mask
#define AGC_COMBPATHSEL_MASK ((uint32_t)0x0000000F)
/// COMBPATHSEL field LSB position
#define AGC_COMBPATHSEL_LSB 0
/// COMBPATHSEL field width
#define AGC_COMBPATHSEL_WIDTH ((uint32_t)0x00000004)
/// HTSTFGAINEN field reset value
#define AGC_HTSTFGAINEN_RST 0x1
/// AGCFSMRESET field reset value
#define AGC_AGCFSMRESET_RST 0x0
/// RADARDETEN field reset value
#define AGC_RADARDETEN_RST 0x0
/// RIFSDETEN field reset value
#define AGC_RIFSDETEN_RST 0x1
/// DSSSONLY field reset value
#define AGC_DSSSONLY_RST 0x0
/// OFDMONLY field reset value
#define AGC_OFDMONLY_RST 0x0
/// GPSTATUS field reset value
#define AGC_GPSTATUS_RST 0x0
/// COMBPATHSEL field reset value
#define AGC_COMBPATHSEL_RST 0xF
/**
* @brief Constructs a value for the RWNXAGCCNTL register given values for its fields
* and writes the value to the register.
*
* @param[in] htstfgainen - The value to use for the HTSTFGAINEN field.
* @param[in] agcfsmreset - The value to use for the AGCFSMRESET field.
* @param[in] radardeten - The value to use for the RADARDETEN field.
* @param[in] rifsdeten - The value to use for the RIFSDETEN field.
* @param[in] dsssonly - The value to use for the DSSSONLY field.
* @param[in] ofdmonly - The value to use for the OFDMONLY field.
* @param[in] gpstatus - The value to use for the GPSTATUS field.
* @param[in] combpathsel - The value to use for the COMBPATHSEL field.
*/
__INLINE void agc_rwnxagccntl_pack(uint8_t htstfgainen, uint8_t agcfsmreset, uint8_t radardeten, uint8_t rifsdeten, uint8_t dsssonly, uint8_t ofdmonly, uint8_t gpstatus, uint8_t combpathsel)
{
ASSERT_ERR((((uint32_t)htstfgainen << 16) & ~((uint32_t)0x00010000)) == 0);
ASSERT_ERR((((uint32_t)agcfsmreset << 12) & ~((uint32_t)0x00001000)) == 0);
ASSERT_ERR((((uint32_t)radardeten << 11) & ~((uint32_t)0x00000800)) == 0);
ASSERT_ERR((((uint32_t)rifsdeten << 10) & ~((uint32_t)0x00000400)) == 0);
ASSERT_ERR((((uint32_t)dsssonly << 9) & ~((uint32_t)0x00000200)) == 0);
ASSERT_ERR((((uint32_t)ofdmonly << 8) & ~((uint32_t)0x00000100)) == 0);
ASSERT_ERR((((uint32_t)gpstatus << 4) & ~((uint32_t)0x000000F0)) == 0);
ASSERT_ERR((((uint32_t)combpathsel << 0) & ~((uint32_t)0x0000000F)) == 0);
REG_PL_WR(AGC_RWNXAGCCNTL_ADDR, ((uint32_t)htstfgainen << 16) | ((uint32_t)agcfsmreset << 12) | ((uint32_t)radardeten << 11) | ((uint32_t)rifsdeten << 10) | ((uint32_t)dsssonly << 9) | ((uint32_t)ofdmonly << 8) | ((uint32_t)gpstatus << 4) | ((uint32_t)combpathsel << 0));
}
/**
* @brief Unpacks RWNXAGCCNTL's fields from current value of the RWNXAGCCNTL register.
*
* Reads the RWNXAGCCNTL register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] htstfgainen - Will be populated with the current value of this field from the register.
* @param[out] agcfsmreset - Will be populated with the current value of this field from the register.
* @param[out] radardeten - Will be populated with the current value of this field from the register.
* @param[out] rifsdeten - Will be populated with the current value of this field from the register.
* @param[out] dsssonly - Will be populated with the current value of this field from the register.
* @param[out] ofdmonly - Will be populated with the current value of this field from the register.
* @param[out] gpstatus - Will be populated with the current value of this field from the register.
* @param[out] combpathsel - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagccntl_unpack(uint8_t *htstfgainen, uint8_t *agcfsmreset, uint8_t *radardeten, uint8_t *rifsdeten, uint8_t *dsssonly, uint8_t *ofdmonly, uint8_t *gpstatus, uint8_t *combpathsel)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCNTL_ADDR);
*htstfgainen = (localVal & ((uint32_t)0x00010000)) >> 16;
*agcfsmreset = (localVal & ((uint32_t)0x00001000)) >> 12;
*radardeten = (localVal & ((uint32_t)0x00000800)) >> 11;
*rifsdeten = (localVal & ((uint32_t)0x00000400)) >> 10;
*dsssonly = (localVal & ((uint32_t)0x00000200)) >> 9;
*ofdmonly = (localVal & ((uint32_t)0x00000100)) >> 8;
*gpstatus = (localVal & ((uint32_t)0x000000F0)) >> 4;
*combpathsel = (localVal & ((uint32_t)0x0000000F)) >> 0;
}
/**
* @brief Returns the current value of the HTSTFGAINEN field in the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read and the HTSTFGAINEN field's value will be returned.
*
* @return The current value of the HTSTFGAINEN field in the RWNXAGCCNTL register.
*/
__INLINE uint8_t agc_htstfgainen_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCNTL_ADDR);
return ((localVal & ((uint32_t)0x00010000)) >> 16);
}
/**
* @brief Sets the HTSTFGAINEN field of the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read, modified to contain the new field value, and written.
*
* @param[in] htstfgainen - The value to set the field to.
*/
__INLINE void agc_htstfgainen_setf(uint8_t htstfgainen)
{
ASSERT_ERR((((uint32_t)htstfgainen << 16) & ~((uint32_t)0x00010000)) == 0);
REG_PL_WR(AGC_RWNXAGCCNTL_ADDR, (REG_PL_RD(AGC_RWNXAGCCNTL_ADDR) & ~((uint32_t)0x00010000)) | ((uint32_t)htstfgainen << 16));
}
/**
* @brief Returns the current value of the AGCFSMRESET field in the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read and the AGCFSMRESET field's value will be returned.
*
* @return The current value of the AGCFSMRESET field in the RWNXAGCCNTL register.
*/
__INLINE uint8_t agc_agcfsmreset_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCNTL_ADDR);
return ((localVal & ((uint32_t)0x00001000)) >> 12);
}
/**
* @brief Sets the AGCFSMRESET field of the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read, modified to contain the new field value, and written.
*
* @param[in] agcfsmreset - The value to set the field to.
*/
__INLINE void agc_agcfsmreset_setf(uint8_t agcfsmreset)
{
ASSERT_ERR((((uint32_t)agcfsmreset << 12) & ~((uint32_t)0x00001000)) == 0);
REG_PL_WR(AGC_RWNXAGCCNTL_ADDR, (REG_PL_RD(AGC_RWNXAGCCNTL_ADDR) & ~((uint32_t)0x00001000)) | ((uint32_t)agcfsmreset << 12));
}
/**
* @brief Returns the current value of the RADARDETEN field in the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read and the RADARDETEN field's value will be returned.
*
* @return The current value of the RADARDETEN field in the RWNXAGCCNTL register.
*/
__INLINE uint8_t agc_radardeten_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCNTL_ADDR);
return ((localVal & ((uint32_t)0x00000800)) >> 11);
}
/**
* @brief Sets the RADARDETEN field of the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read, modified to contain the new field value, and written.
*
* @param[in] radardeten - The value to set the field to.
*/
__INLINE void agc_radardeten_setf(uint8_t radardeten)
{
ASSERT_ERR((((uint32_t)radardeten << 11) & ~((uint32_t)0x00000800)) == 0);
REG_PL_WR(AGC_RWNXAGCCNTL_ADDR, (REG_PL_RD(AGC_RWNXAGCCNTL_ADDR) & ~((uint32_t)0x00000800)) | ((uint32_t)radardeten << 11));
}
/**
* @brief Returns the current value of the RIFSDETEN field in the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read and the RIFSDETEN field's value will be returned.
*
* @return The current value of the RIFSDETEN field in the RWNXAGCCNTL register.
*/
__INLINE uint8_t agc_rifsdeten_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCNTL_ADDR);
return ((localVal & ((uint32_t)0x00000400)) >> 10);
}
/**
* @brief Sets the RIFSDETEN field of the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read, modified to contain the new field value, and written.
*
* @param[in] rifsdeten - The value to set the field to.
*/
__INLINE void agc_rifsdeten_setf(uint8_t rifsdeten)
{
ASSERT_ERR((((uint32_t)rifsdeten << 10) & ~((uint32_t)0x00000400)) == 0);
REG_PL_WR(AGC_RWNXAGCCNTL_ADDR, (REG_PL_RD(AGC_RWNXAGCCNTL_ADDR) & ~((uint32_t)0x00000400)) | ((uint32_t)rifsdeten << 10));
}
/**
* @brief Returns the current value of the DSSSONLY field in the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read and the DSSSONLY field's value will be returned.
*
* @return The current value of the DSSSONLY field in the RWNXAGCCNTL register.
*/
__INLINE uint8_t agc_dsssonly_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCNTL_ADDR);
return ((localVal & ((uint32_t)0x00000200)) >> 9);
}
/**
* @brief Sets the DSSSONLY field of the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read, modified to contain the new field value, and written.
*
* @param[in] dsssonly - The value to set the field to.
*/
__INLINE void agc_dsssonly_setf(uint8_t dsssonly)
{
ASSERT_ERR((((uint32_t)dsssonly << 9) & ~((uint32_t)0x00000200)) == 0);
REG_PL_WR(AGC_RWNXAGCCNTL_ADDR, (REG_PL_RD(AGC_RWNXAGCCNTL_ADDR) & ~((uint32_t)0x00000200)) | ((uint32_t)dsssonly << 9));
}
/**
* @brief Returns the current value of the OFDMONLY field in the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read and the OFDMONLY field's value will be returned.
*
* @return The current value of the OFDMONLY field in the RWNXAGCCNTL register.
*/
__INLINE uint8_t agc_ofdmonly_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCNTL_ADDR);
return ((localVal & ((uint32_t)0x00000100)) >> 8);
}
/**
* @brief Sets the OFDMONLY field of the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read, modified to contain the new field value, and written.
*
* @param[in] ofdmonly - The value to set the field to.
*/
__INLINE void agc_ofdmonly_setf(uint8_t ofdmonly)
{
ASSERT_ERR((((uint32_t)ofdmonly << 8) & ~((uint32_t)0x00000100)) == 0);
REG_PL_WR(AGC_RWNXAGCCNTL_ADDR, (REG_PL_RD(AGC_RWNXAGCCNTL_ADDR) & ~((uint32_t)0x00000100)) | ((uint32_t)ofdmonly << 8));
}
/**
* @brief Returns the current value of the GPSTATUS field in the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read and the GPSTATUS field's value will be returned.
*
* @return The current value of the GPSTATUS field in the RWNXAGCCNTL register.
*/
__INLINE uint8_t agc_gpstatus_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCNTL_ADDR);
return ((localVal & ((uint32_t)0x000000F0)) >> 4);
}
/**
* @brief Sets the GPSTATUS field of the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read, modified to contain the new field value, and written.
*
* @param[in] gpstatus - The value to set the field to.
*/
__INLINE void agc_gpstatus_setf(uint8_t gpstatus)
{
ASSERT_ERR((((uint32_t)gpstatus << 4) & ~((uint32_t)0x000000F0)) == 0);
REG_PL_WR(AGC_RWNXAGCCNTL_ADDR, (REG_PL_RD(AGC_RWNXAGCCNTL_ADDR) & ~((uint32_t)0x000000F0)) | ((uint32_t)gpstatus << 4));
}
/**
* @brief Returns the current value of the COMBPATHSEL field in the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read and the COMBPATHSEL field's value will be returned.
*
* @return The current value of the COMBPATHSEL field in the RWNXAGCCNTL register.
*/
__INLINE uint8_t agc_combpathsel_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCNTL_ADDR);
return ((localVal & ((uint32_t)0x0000000F)) >> 0);
}
/**
* @brief Sets the COMBPATHSEL field of the RWNXAGCCNTL register.
*
* The RWNXAGCCNTL register will be read, modified to contain the new field value, and written.
*
* @param[in] combpathsel - The value to set the field to.
*/
__INLINE void agc_combpathsel_setf(uint8_t combpathsel)
{
ASSERT_ERR((((uint32_t)combpathsel << 0) & ~((uint32_t)0x0000000F)) == 0);
REG_PL_WR(AGC_RWNXAGCCNTL_ADDR, (REG_PL_RD(AGC_RWNXAGCCNTL_ADDR) & ~((uint32_t)0x0000000F)) | ((uint32_t)combpathsel << 0));
}
/// @}
/**
* @name RWNXAGCDSP0 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 27:24 NBITADC 0xC
* 23:16 VPEAKADCQDBV 0xE8
* 15:08 ADCPOWMINDBV 0xCE
* 07:00 ADCPOWBIASQDB 0x0
* </pre>
*
* @{
*/
/// Address of the RWNXAGCDSP0 register
#define AGC_RWNXAGCDSP0_ADDR 0x01002064
/// Offset of the RWNXAGCDSP0 register from the base address
#define AGC_RWNXAGCDSP0_OFFSET 0x00002064
/// Index of the RWNXAGCDSP0 register
#define AGC_RWNXAGCDSP0_INDEX 0x00000819
/// Reset value of the RWNXAGCDSP0 register
#define AGC_RWNXAGCDSP0_RESET 0x0CE8CE00
/**
* @brief Returns the current value of the RWNXAGCDSP0 register.
* The RWNXAGCDSP0 register will be read and its value returned.
* @return The current value of the RWNXAGCDSP0 register.
*/
__INLINE uint32_t agc_rwnxagcdsp0_get(void)
{
return REG_PL_RD(AGC_RWNXAGCDSP0_ADDR);
}
/**
* @brief Sets the RWNXAGCDSP0 register to a value.
* The RWNXAGCDSP0 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcdsp0_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCDSP0_ADDR, value);
}
// field definitions
/// NBITADC field mask
#define AGC_NBITADC_MASK ((uint32_t)0x0F000000)
/// NBITADC field LSB position
#define AGC_NBITADC_LSB 24
/// NBITADC field width
#define AGC_NBITADC_WIDTH ((uint32_t)0x00000004)
/// VPEAKADCQDBV field mask
#define AGC_VPEAKADCQDBV_MASK ((uint32_t)0x00FF0000)
/// VPEAKADCQDBV field LSB position
#define AGC_VPEAKADCQDBV_LSB 16
/// VPEAKADCQDBV field width
#define AGC_VPEAKADCQDBV_WIDTH ((uint32_t)0x00000008)
/// ADCPOWMINDBV field mask
#define AGC_ADCPOWMINDBV_MASK ((uint32_t)0x0000FF00)
/// ADCPOWMINDBV field LSB position
#define AGC_ADCPOWMINDBV_LSB 8
/// ADCPOWMINDBV field width
#define AGC_ADCPOWMINDBV_WIDTH ((uint32_t)0x00000008)
/// ADCPOWBIASQDB field mask
#define AGC_ADCPOWBIASQDB_MASK ((uint32_t)0x000000FF)
/// ADCPOWBIASQDB field LSB position
#define AGC_ADCPOWBIASQDB_LSB 0
/// ADCPOWBIASQDB field width
#define AGC_ADCPOWBIASQDB_WIDTH ((uint32_t)0x00000008)
/// NBITADC field reset value
#define AGC_NBITADC_RST 0xC
/// VPEAKADCQDBV field reset value
#define AGC_VPEAKADCQDBV_RST 0xE8
/// ADCPOWMINDBV field reset value
#define AGC_ADCPOWMINDBV_RST 0xCE
/// ADCPOWBIASQDB field reset value
#define AGC_ADCPOWBIASQDB_RST 0x0
/**
* @brief Constructs a value for the RWNXAGCDSP0 register given values for its fields
* and writes the value to the register.
*
* @param[in] nbitadc - The value to use for the NBITADC field.
* @param[in] vpeakadcqdbv - The value to use for the VPEAKADCQDBV field.
* @param[in] adcpowmindbv - The value to use for the ADCPOWMINDBV field.
* @param[in] adcpowbiasqdb - The value to use for the ADCPOWBIASQDB field.
*/
__INLINE void agc_rwnxagcdsp0_pack(uint8_t nbitadc, uint8_t vpeakadcqdbv, uint8_t adcpowmindbv, uint8_t adcpowbiasqdb)
{
ASSERT_ERR((((uint32_t)nbitadc << 24) & ~((uint32_t)0x0F000000)) == 0);
ASSERT_ERR((((uint32_t)vpeakadcqdbv << 16) & ~((uint32_t)0x00FF0000)) == 0);
ASSERT_ERR((((uint32_t)adcpowmindbv << 8) & ~((uint32_t)0x0000FF00)) == 0);
ASSERT_ERR((((uint32_t)adcpowbiasqdb << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP0_ADDR, ((uint32_t)nbitadc << 24) | ((uint32_t)vpeakadcqdbv << 16) | ((uint32_t)adcpowmindbv << 8) | ((uint32_t)adcpowbiasqdb << 0));
}
/**
* @brief Unpacks RWNXAGCDSP0's fields from current value of the RWNXAGCDSP0 register.
*
* Reads the RWNXAGCDSP0 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] nbitadc - Will be populated with the current value of this field from the register.
* @param[out] vpeakadcqdbv - Will be populated with the current value of this field from the register.
* @param[out] adcpowmindbv - Will be populated with the current value of this field from the register.
* @param[out] adcpowbiasqdb - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcdsp0_unpack(uint8_t *nbitadc, uint8_t *vpeakadcqdbv, uint8_t *adcpowmindbv, uint8_t *adcpowbiasqdb)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP0_ADDR);
*nbitadc = (localVal & ((uint32_t)0x0F000000)) >> 24;
*vpeakadcqdbv = (localVal & ((uint32_t)0x00FF0000)) >> 16;
*adcpowmindbv = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*adcpowbiasqdb = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the NBITADC field in the RWNXAGCDSP0 register.
*
* The RWNXAGCDSP0 register will be read and the NBITADC field's value will be returned.
*
* @return The current value of the NBITADC field in the RWNXAGCDSP0 register.
*/
__INLINE uint8_t agc_nbitadc_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP0_ADDR);
return ((localVal & ((uint32_t)0x0F000000)) >> 24);
}
/**
* @brief Sets the NBITADC field of the RWNXAGCDSP0 register.
*
* The RWNXAGCDSP0 register will be read, modified to contain the new field value, and written.
*
* @param[in] nbitadc - The value to set the field to.
*/
__INLINE void agc_nbitadc_setf(uint8_t nbitadc)
{
ASSERT_ERR((((uint32_t)nbitadc << 24) & ~((uint32_t)0x0F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP0_ADDR, (REG_PL_RD(AGC_RWNXAGCDSP0_ADDR) & ~((uint32_t)0x0F000000)) | ((uint32_t)nbitadc << 24));
}
/**
* @brief Returns the current value of the VPEAKADCQDBV field in the RWNXAGCDSP0 register.
*
* The RWNXAGCDSP0 register will be read and the VPEAKADCQDBV field's value will be returned.
*
* @return The current value of the VPEAKADCQDBV field in the RWNXAGCDSP0 register.
*/
__INLINE uint8_t agc_vpeakadcqdbv_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP0_ADDR);
return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
}
/**
* @brief Sets the VPEAKADCQDBV field of the RWNXAGCDSP0 register.
*
* The RWNXAGCDSP0 register will be read, modified to contain the new field value, and written.
*
* @param[in] vpeakadcqdbv - The value to set the field to.
*/
__INLINE void agc_vpeakadcqdbv_setf(uint8_t vpeakadcqdbv)
{
ASSERT_ERR((((uint32_t)vpeakadcqdbv << 16) & ~((uint32_t)0x00FF0000)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP0_ADDR, (REG_PL_RD(AGC_RWNXAGCDSP0_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)vpeakadcqdbv << 16));
}
/**
* @brief Returns the current value of the ADCPOWMINDBV field in the RWNXAGCDSP0 register.
*
* The RWNXAGCDSP0 register will be read and the ADCPOWMINDBV field's value will be returned.
*
* @return The current value of the ADCPOWMINDBV field in the RWNXAGCDSP0 register.
*/
__INLINE uint8_t agc_adcpowmindbv_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP0_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Sets the ADCPOWMINDBV field of the RWNXAGCDSP0 register.
*
* The RWNXAGCDSP0 register will be read, modified to contain the new field value, and written.
*
* @param[in] adcpowmindbv - The value to set the field to.
*/
__INLINE void agc_adcpowmindbv_setf(uint8_t adcpowmindbv)
{
ASSERT_ERR((((uint32_t)adcpowmindbv << 8) & ~((uint32_t)0x0000FF00)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP0_ADDR, (REG_PL_RD(AGC_RWNXAGCDSP0_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)adcpowmindbv << 8));
}
/**
* @brief Returns the current value of the ADCPOWBIASQDB field in the RWNXAGCDSP0 register.
*
* The RWNXAGCDSP0 register will be read and the ADCPOWBIASQDB field's value will be returned.
*
* @return The current value of the ADCPOWBIASQDB field in the RWNXAGCDSP0 register.
*/
__INLINE uint8_t agc_adcpowbiasqdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP0_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the ADCPOWBIASQDB field of the RWNXAGCDSP0 register.
*
* The RWNXAGCDSP0 register will be read, modified to contain the new field value, and written.
*
* @param[in] adcpowbiasqdb - The value to set the field to.
*/
__INLINE void agc_adcpowbiasqdb_setf(uint8_t adcpowbiasqdb)
{
ASSERT_ERR((((uint32_t)adcpowbiasqdb << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP0_ADDR, (REG_PL_RD(AGC_RWNXAGCDSP0_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)adcpowbiasqdb << 0));
}
/// @}
/**
* @name RWNXAGCDSP1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:28 INBDRND 0x3
* 23:16 INBDPOW40SBIASQDB 0x0
* 15:08 INBDPOW20SBIASQDB 0x0
* 07:00 INBDPOW20PBIASQDB 0x0
* </pre>
*
* @{
*/
/// Address of the RWNXAGCDSP1 register
#define AGC_RWNXAGCDSP1_ADDR 0x01002068
/// Offset of the RWNXAGCDSP1 register from the base address
#define AGC_RWNXAGCDSP1_OFFSET 0x00002068
/// Index of the RWNXAGCDSP1 register
#define AGC_RWNXAGCDSP1_INDEX 0x0000081A
/// Reset value of the RWNXAGCDSP1 register
#define AGC_RWNXAGCDSP1_RESET 0x30000000
/**
* @brief Returns the current value of the RWNXAGCDSP1 register.
* The RWNXAGCDSP1 register will be read and its value returned.
* @return The current value of the RWNXAGCDSP1 register.
*/
__INLINE uint32_t agc_rwnxagcdsp1_get(void)
{
return REG_PL_RD(AGC_RWNXAGCDSP1_ADDR);
}
/**
* @brief Sets the RWNXAGCDSP1 register to a value.
* The RWNXAGCDSP1 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcdsp1_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCDSP1_ADDR, value);
}
// field definitions
/// INBDRND field mask
#define AGC_INBDRND_MASK ((uint32_t)0x30000000)
/// INBDRND field LSB position
#define AGC_INBDRND_LSB 28
/// INBDRND field width
#define AGC_INBDRND_WIDTH ((uint32_t)0x00000002)
/// INBDPOW40SBIASQDB field mask
#define AGC_INBDPOW40SBIASQDB_MASK ((uint32_t)0x00FF0000)
/// INBDPOW40SBIASQDB field LSB position
#define AGC_INBDPOW40SBIASQDB_LSB 16
/// INBDPOW40SBIASQDB field width
#define AGC_INBDPOW40SBIASQDB_WIDTH ((uint32_t)0x00000008)
/// INBDPOW20SBIASQDB field mask
#define AGC_INBDPOW20SBIASQDB_MASK ((uint32_t)0x0000FF00)
/// INBDPOW20SBIASQDB field LSB position
#define AGC_INBDPOW20SBIASQDB_LSB 8
/// INBDPOW20SBIASQDB field width
#define AGC_INBDPOW20SBIASQDB_WIDTH ((uint32_t)0x00000008)
/// INBDPOW20PBIASQDB field mask
#define AGC_INBDPOW20PBIASQDB_MASK ((uint32_t)0x000000FF)
/// INBDPOW20PBIASQDB field LSB position
#define AGC_INBDPOW20PBIASQDB_LSB 0
/// INBDPOW20PBIASQDB field width
#define AGC_INBDPOW20PBIASQDB_WIDTH ((uint32_t)0x00000008)
/// INBDRND field reset value
#define AGC_INBDRND_RST 0x3
/// INBDPOW40SBIASQDB field reset value
#define AGC_INBDPOW40SBIASQDB_RST 0x0
/// INBDPOW20SBIASQDB field reset value
#define AGC_INBDPOW20SBIASQDB_RST 0x0
/// INBDPOW20PBIASQDB field reset value
#define AGC_INBDPOW20PBIASQDB_RST 0x0
/**
* @brief Constructs a value for the RWNXAGCDSP1 register given values for its fields
* and writes the value to the register.
*
* @param[in] inbdrnd - The value to use for the INBDRND field.
* @param[in] inbdpow40sbiasqdb - The value to use for the INBDPOW40SBIASQDB field.
* @param[in] inbdpow20sbiasqdb - The value to use for the INBDPOW20SBIASQDB field.
* @param[in] inbdpow20pbiasqdb - The value to use for the INBDPOW20PBIASQDB field.
*/
__INLINE void agc_rwnxagcdsp1_pack(uint8_t inbdrnd, uint8_t inbdpow40sbiasqdb, uint8_t inbdpow20sbiasqdb, uint8_t inbdpow20pbiasqdb)
{
ASSERT_ERR((((uint32_t)inbdrnd << 28) & ~((uint32_t)0x30000000)) == 0);
ASSERT_ERR((((uint32_t)inbdpow40sbiasqdb << 16) & ~((uint32_t)0x00FF0000)) == 0);
ASSERT_ERR((((uint32_t)inbdpow20sbiasqdb << 8) & ~((uint32_t)0x0000FF00)) == 0);
ASSERT_ERR((((uint32_t)inbdpow20pbiasqdb << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP1_ADDR, ((uint32_t)inbdrnd << 28) | ((uint32_t)inbdpow40sbiasqdb << 16) | ((uint32_t)inbdpow20sbiasqdb << 8) | ((uint32_t)inbdpow20pbiasqdb << 0));
}
/**
* @brief Unpacks RWNXAGCDSP1's fields from current value of the RWNXAGCDSP1 register.
*
* Reads the RWNXAGCDSP1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] inbdrnd - Will be populated with the current value of this field from the register.
* @param[out] inbdpow40sbiasqdb - Will be populated with the current value of this field from the register.
* @param[out] inbdpow20sbiasqdb - Will be populated with the current value of this field from the register.
* @param[out] inbdpow20pbiasqdb - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcdsp1_unpack(uint8_t *inbdrnd, uint8_t *inbdpow40sbiasqdb, uint8_t *inbdpow20sbiasqdb, uint8_t *inbdpow20pbiasqdb)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP1_ADDR);
*inbdrnd = (localVal & ((uint32_t)0x30000000)) >> 28;
*inbdpow40sbiasqdb = (localVal & ((uint32_t)0x00FF0000)) >> 16;
*inbdpow20sbiasqdb = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*inbdpow20pbiasqdb = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the INBDRND field in the RWNXAGCDSP1 register.
*
* The RWNXAGCDSP1 register will be read and the INBDRND field's value will be returned.
*
* @return The current value of the INBDRND field in the RWNXAGCDSP1 register.
*/
__INLINE uint8_t agc_inbdrnd_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP1_ADDR);
return ((localVal & ((uint32_t)0x30000000)) >> 28);
}
/**
* @brief Sets the INBDRND field of the RWNXAGCDSP1 register.
*
* The RWNXAGCDSP1 register will be read, modified to contain the new field value, and written.
*
* @param[in] inbdrnd - The value to set the field to.
*/
__INLINE void agc_inbdrnd_setf(uint8_t inbdrnd)
{
ASSERT_ERR((((uint32_t)inbdrnd << 28) & ~((uint32_t)0x30000000)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP1_ADDR, (REG_PL_RD(AGC_RWNXAGCDSP1_ADDR) & ~((uint32_t)0x30000000)) | ((uint32_t)inbdrnd << 28));
}
/**
* @brief Returns the current value of the INBDPOW40SBIASQDB field in the RWNXAGCDSP1 register.
*
* The RWNXAGCDSP1 register will be read and the INBDPOW40SBIASQDB field's value will be returned.
*
* @return The current value of the INBDPOW40SBIASQDB field in the RWNXAGCDSP1 register.
*/
__INLINE uint8_t agc_inbdpow40sbiasqdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP1_ADDR);
return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
}
/**
* @brief Sets the INBDPOW40SBIASQDB field of the RWNXAGCDSP1 register.
*
* The RWNXAGCDSP1 register will be read, modified to contain the new field value, and written.
*
* @param[in] inbdpow40sbiasqdb - The value to set the field to.
*/
__INLINE void agc_inbdpow40sbiasqdb_setf(uint8_t inbdpow40sbiasqdb)
{
ASSERT_ERR((((uint32_t)inbdpow40sbiasqdb << 16) & ~((uint32_t)0x00FF0000)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP1_ADDR, (REG_PL_RD(AGC_RWNXAGCDSP1_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)inbdpow40sbiasqdb << 16));
}
/**
* @brief Returns the current value of the INBDPOW20SBIASQDB field in the RWNXAGCDSP1 register.
*
* The RWNXAGCDSP1 register will be read and the INBDPOW20SBIASQDB field's value will be returned.
*
* @return The current value of the INBDPOW20SBIASQDB field in the RWNXAGCDSP1 register.
*/
__INLINE uint8_t agc_inbdpow20sbiasqdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP1_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Sets the INBDPOW20SBIASQDB field of the RWNXAGCDSP1 register.
*
* The RWNXAGCDSP1 register will be read, modified to contain the new field value, and written.
*
* @param[in] inbdpow20sbiasqdb - The value to set the field to.
*/
__INLINE void agc_inbdpow20sbiasqdb_setf(uint8_t inbdpow20sbiasqdb)
{
ASSERT_ERR((((uint32_t)inbdpow20sbiasqdb << 8) & ~((uint32_t)0x0000FF00)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP1_ADDR, (REG_PL_RD(AGC_RWNXAGCDSP1_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)inbdpow20sbiasqdb << 8));
}
/**
* @brief Returns the current value of the INBDPOW20PBIASQDB field in the RWNXAGCDSP1 register.
*
* The RWNXAGCDSP1 register will be read and the INBDPOW20PBIASQDB field's value will be returned.
*
* @return The current value of the INBDPOW20PBIASQDB field in the RWNXAGCDSP1 register.
*/
__INLINE uint8_t agc_inbdpow20pbiasqdb_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP1_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the INBDPOW20PBIASQDB field of the RWNXAGCDSP1 register.
*
* The RWNXAGCDSP1 register will be read, modified to contain the new field value, and written.
*
* @param[in] inbdpow20pbiasqdb - The value to set the field to.
*/
__INLINE void agc_inbdpow20pbiasqdb_setf(uint8_t inbdpow20pbiasqdb)
{
ASSERT_ERR((((uint32_t)inbdpow20pbiasqdb << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP1_ADDR, (REG_PL_RD(AGC_RWNXAGCDSP1_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)inbdpow20pbiasqdb << 0));
}
/// @}
/**
* @name RWNXAGCDSP2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 24:16 INBDPOWMINDBM 0x19C
* 15:08 FE40GAIN 0x2
* 07:00 FE20GAIN 0x2
* </pre>
*
* @{
*/
/// Address of the RWNXAGCDSP2 register
#define AGC_RWNXAGCDSP2_ADDR 0x0100206C
/// Offset of the RWNXAGCDSP2 register from the base address
#define AGC_RWNXAGCDSP2_OFFSET 0x0000206C
/// Index of the RWNXAGCDSP2 register
#define AGC_RWNXAGCDSP2_INDEX 0x0000081B
/// Reset value of the RWNXAGCDSP2 register
#define AGC_RWNXAGCDSP2_RESET 0x019C0202
/**
* @brief Returns the current value of the RWNXAGCDSP2 register.
* The RWNXAGCDSP2 register will be read and its value returned.
* @return The current value of the RWNXAGCDSP2 register.
*/
__INLINE uint32_t agc_rwnxagcdsp2_get(void)
{
return REG_PL_RD(AGC_RWNXAGCDSP2_ADDR);
}
/**
* @brief Sets the RWNXAGCDSP2 register to a value.
* The RWNXAGCDSP2 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcdsp2_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCDSP2_ADDR, value);
}
// field definitions
/// INBDPOWMINDBM field mask
#define AGC_INBDPOWMINDBM_MASK ((uint32_t)0x01FF0000)
/// INBDPOWMINDBM field LSB position
#define AGC_INBDPOWMINDBM_LSB 16
/// INBDPOWMINDBM field width
#define AGC_INBDPOWMINDBM_WIDTH ((uint32_t)0x00000009)
/// FE40GAIN field mask
#define AGC_FE40GAIN_MASK ((uint32_t)0x0000FF00)
/// FE40GAIN field LSB position
#define AGC_FE40GAIN_LSB 8
/// FE40GAIN field width
#define AGC_FE40GAIN_WIDTH ((uint32_t)0x00000008)
/// FE20GAIN field mask
#define AGC_FE20GAIN_MASK ((uint32_t)0x000000FF)
/// FE20GAIN field LSB position
#define AGC_FE20GAIN_LSB 0
/// FE20GAIN field width
#define AGC_FE20GAIN_WIDTH ((uint32_t)0x00000008)
/// INBDPOWMINDBM field reset value
#define AGC_INBDPOWMINDBM_RST 0x19C
/// FE40GAIN field reset value
#define AGC_FE40GAIN_RST 0x2
/// FE20GAIN field reset value
#define AGC_FE20GAIN_RST 0x2
/**
* @brief Constructs a value for the RWNXAGCDSP2 register given values for its fields
* and writes the value to the register.
*
* @param[in] inbdpowmindbm - The value to use for the INBDPOWMINDBM field.
* @param[in] fe40gain - The value to use for the FE40GAIN field.
* @param[in] fe20gain - The value to use for the FE20GAIN field.
*/
__INLINE void agc_rwnxagcdsp2_pack(uint16_t inbdpowmindbm, uint8_t fe40gain, uint8_t fe20gain)
{
ASSERT_ERR((((uint32_t)inbdpowmindbm << 16) & ~((uint32_t)0x01FF0000)) == 0);
ASSERT_ERR((((uint32_t)fe40gain << 8) & ~((uint32_t)0x0000FF00)) == 0);
ASSERT_ERR((((uint32_t)fe20gain << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP2_ADDR, ((uint32_t)inbdpowmindbm << 16) | ((uint32_t)fe40gain << 8) | ((uint32_t)fe20gain << 0));
}
/**
* @brief Unpacks RWNXAGCDSP2's fields from current value of the RWNXAGCDSP2 register.
*
* Reads the RWNXAGCDSP2 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] inbdpowmindbm - Will be populated with the current value of this field from the register.
* @param[out] fe40gain - Will be populated with the current value of this field from the register.
* @param[out] fe20gain - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcdsp2_unpack(uint16_t *inbdpowmindbm, uint8_t *fe40gain, uint8_t *fe20gain)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP2_ADDR);
*inbdpowmindbm = (localVal & ((uint32_t)0x01FF0000)) >> 16;
*fe40gain = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*fe20gain = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the INBDPOWMINDBM field in the RWNXAGCDSP2 register.
*
* The RWNXAGCDSP2 register will be read and the INBDPOWMINDBM field's value will be returned.
*
* @return The current value of the INBDPOWMINDBM field in the RWNXAGCDSP2 register.
*/
__INLINE uint16_t agc_inbdpowmindbm_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP2_ADDR);
return ((localVal & ((uint32_t)0x01FF0000)) >> 16);
}
/**
* @brief Sets the INBDPOWMINDBM field of the RWNXAGCDSP2 register.
*
* The RWNXAGCDSP2 register will be read, modified to contain the new field value, and written.
*
* @param[in] inbdpowmindbm - The value to set the field to.
*/
__INLINE void agc_inbdpowmindbm_setf(uint16_t inbdpowmindbm)
{
ASSERT_ERR((((uint32_t)inbdpowmindbm << 16) & ~((uint32_t)0x01FF0000)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP2_ADDR, (REG_PL_RD(AGC_RWNXAGCDSP2_ADDR) & ~((uint32_t)0x01FF0000)) | ((uint32_t)inbdpowmindbm << 16));
}
/**
* @brief Returns the current value of the FE40GAIN field in the RWNXAGCDSP2 register.
*
* The RWNXAGCDSP2 register will be read and the FE40GAIN field's value will be returned.
*
* @return The current value of the FE40GAIN field in the RWNXAGCDSP2 register.
*/
__INLINE uint8_t agc_fe40gain_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP2_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Sets the FE40GAIN field of the RWNXAGCDSP2 register.
*
* The RWNXAGCDSP2 register will be read, modified to contain the new field value, and written.
*
* @param[in] fe40gain - The value to set the field to.
*/
__INLINE void agc_fe40gain_setf(uint8_t fe40gain)
{
ASSERT_ERR((((uint32_t)fe40gain << 8) & ~((uint32_t)0x0000FF00)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP2_ADDR, (REG_PL_RD(AGC_RWNXAGCDSP2_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)fe40gain << 8));
}
/**
* @brief Returns the current value of the FE20GAIN field in the RWNXAGCDSP2 register.
*
* The RWNXAGCDSP2 register will be read and the FE20GAIN field's value will be returned.
*
* @return The current value of the FE20GAIN field in the RWNXAGCDSP2 register.
*/
__INLINE uint8_t agc_fe20gain_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP2_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the FE20GAIN field of the RWNXAGCDSP2 register.
*
* The RWNXAGCDSP2 register will be read, modified to contain the new field value, and written.
*
* @param[in] fe20gain - The value to set the field to.
*/
__INLINE void agc_fe20gain_setf(uint8_t fe20gain)
{
ASSERT_ERR((((uint32_t)fe20gain << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP2_ADDR, (REG_PL_RD(AGC_RWNXAGCDSP2_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)fe20gain << 0));
}
/// @}
/**
* @name RWNXAGCCCA0 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 22:20 DELCCARAMPDNTAP 0x5
* 18:16 DELCCARAMPUPTAP 0x5
* 13:08 CCADETRAMPDN 0x9
* 05:00 CCADETRAMPUP 0x9
* </pre>
*
* @{
*/
/// Address of the RWNXAGCCCA0 register
#define AGC_RWNXAGCCCA0_ADDR 0x01002070
/// Offset of the RWNXAGCCCA0 register from the base address
#define AGC_RWNXAGCCCA0_OFFSET 0x00002070
/// Index of the RWNXAGCCCA0 register
#define AGC_RWNXAGCCCA0_INDEX 0x0000081C
/// Reset value of the RWNXAGCCCA0 register
#define AGC_RWNXAGCCCA0_RESET 0x00550909
/**
* @brief Returns the current value of the RWNXAGCCCA0 register.
* The RWNXAGCCCA0 register will be read and its value returned.
* @return The current value of the RWNXAGCCCA0 register.
*/
__INLINE uint32_t agc_rwnxagccca0_get(void)
{
return REG_PL_RD(AGC_RWNXAGCCCA0_ADDR);
}
/**
* @brief Sets the RWNXAGCCCA0 register to a value.
* The RWNXAGCCCA0 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagccca0_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCCCA0_ADDR, value);
}
// field definitions
/// DELCCARAMPDNTAP field mask
#define AGC_DELCCARAMPDNTAP_MASK ((uint32_t)0x00700000)
/// DELCCARAMPDNTAP field LSB position
#define AGC_DELCCARAMPDNTAP_LSB 20
/// DELCCARAMPDNTAP field width
#define AGC_DELCCARAMPDNTAP_WIDTH ((uint32_t)0x00000003)
/// DELCCARAMPUPTAP field mask
#define AGC_DELCCARAMPUPTAP_MASK ((uint32_t)0x00070000)
/// DELCCARAMPUPTAP field LSB position
#define AGC_DELCCARAMPUPTAP_LSB 16
/// DELCCARAMPUPTAP field width
#define AGC_DELCCARAMPUPTAP_WIDTH ((uint32_t)0x00000003)
/// CCADETRAMPDN field mask
#define AGC_CCADETRAMPDN_MASK ((uint32_t)0x00003F00)
/// CCADETRAMPDN field LSB position
#define AGC_CCADETRAMPDN_LSB 8
/// CCADETRAMPDN field width
#define AGC_CCADETRAMPDN_WIDTH ((uint32_t)0x00000006)
/// CCADETRAMPUP field mask
#define AGC_CCADETRAMPUP_MASK ((uint32_t)0x0000003F)
/// CCADETRAMPUP field LSB position
#define AGC_CCADETRAMPUP_LSB 0
/// CCADETRAMPUP field width
#define AGC_CCADETRAMPUP_WIDTH ((uint32_t)0x00000006)
/// DELCCARAMPDNTAP field reset value
#define AGC_DELCCARAMPDNTAP_RST 0x5
/// DELCCARAMPUPTAP field reset value
#define AGC_DELCCARAMPUPTAP_RST 0x5
/// CCADETRAMPDN field reset value
#define AGC_CCADETRAMPDN_RST 0x9
/// CCADETRAMPUP field reset value
#define AGC_CCADETRAMPUP_RST 0x9
/**
* @brief Constructs a value for the RWNXAGCCCA0 register given values for its fields
* and writes the value to the register.
*
* @param[in] delccarampdntap - The value to use for the DELCCARAMPDNTAP field.
* @param[in] delccarampuptap - The value to use for the DELCCARAMPUPTAP field.
* @param[in] ccadetrampdn - The value to use for the CCADETRAMPDN field.
* @param[in] ccadetrampup - The value to use for the CCADETRAMPUP field.
*/
__INLINE void agc_rwnxagccca0_pack(uint8_t delccarampdntap, uint8_t delccarampuptap, uint8_t ccadetrampdn, uint8_t ccadetrampup)
{
ASSERT_ERR((((uint32_t)delccarampdntap << 20) & ~((uint32_t)0x00700000)) == 0);
ASSERT_ERR((((uint32_t)delccarampuptap << 16) & ~((uint32_t)0x00070000)) == 0);
ASSERT_ERR((((uint32_t)ccadetrampdn << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)ccadetrampup << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCCCA0_ADDR, ((uint32_t)delccarampdntap << 20) | ((uint32_t)delccarampuptap << 16) | ((uint32_t)ccadetrampdn << 8) | ((uint32_t)ccadetrampup << 0));
}
/**
* @brief Unpacks RWNXAGCCCA0's fields from current value of the RWNXAGCCCA0 register.
*
* Reads the RWNXAGCCCA0 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] delccarampdntap - Will be populated with the current value of this field from the register.
* @param[out] delccarampuptap - Will be populated with the current value of this field from the register.
* @param[out] ccadetrampdn - Will be populated with the current value of this field from the register.
* @param[out] ccadetrampup - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagccca0_unpack(uint8_t *delccarampdntap, uint8_t *delccarampuptap, uint8_t *ccadetrampdn, uint8_t *ccadetrampup)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCA0_ADDR);
*delccarampdntap = (localVal & ((uint32_t)0x00700000)) >> 20;
*delccarampuptap = (localVal & ((uint32_t)0x00070000)) >> 16;
*ccadetrampdn = (localVal & ((uint32_t)0x00003F00)) >> 8;
*ccadetrampup = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the DELCCARAMPDNTAP field in the RWNXAGCCCA0 register.
*
* The RWNXAGCCCA0 register will be read and the DELCCARAMPDNTAP field's value will be returned.
*
* @return The current value of the DELCCARAMPDNTAP field in the RWNXAGCCCA0 register.
*/
__INLINE uint8_t agc_delccarampdntap_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCA0_ADDR);
return ((localVal & ((uint32_t)0x00700000)) >> 20);
}
/**
* @brief Sets the DELCCARAMPDNTAP field of the RWNXAGCCCA0 register.
*
* The RWNXAGCCCA0 register will be read, modified to contain the new field value, and written.
*
* @param[in] delccarampdntap - The value to set the field to.
*/
__INLINE void agc_delccarampdntap_setf(uint8_t delccarampdntap)
{
ASSERT_ERR((((uint32_t)delccarampdntap << 20) & ~((uint32_t)0x00700000)) == 0);
REG_PL_WR(AGC_RWNXAGCCCA0_ADDR, (REG_PL_RD(AGC_RWNXAGCCCA0_ADDR) & ~((uint32_t)0x00700000)) | ((uint32_t)delccarampdntap << 20));
}
/**
* @brief Returns the current value of the DELCCARAMPUPTAP field in the RWNXAGCCCA0 register.
*
* The RWNXAGCCCA0 register will be read and the DELCCARAMPUPTAP field's value will be returned.
*
* @return The current value of the DELCCARAMPUPTAP field in the RWNXAGCCCA0 register.
*/
__INLINE uint8_t agc_delccarampuptap_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCA0_ADDR);
return ((localVal & ((uint32_t)0x00070000)) >> 16);
}
/**
* @brief Sets the DELCCARAMPUPTAP field of the RWNXAGCCCA0 register.
*
* The RWNXAGCCCA0 register will be read, modified to contain the new field value, and written.
*
* @param[in] delccarampuptap - The value to set the field to.
*/
__INLINE void agc_delccarampuptap_setf(uint8_t delccarampuptap)
{
ASSERT_ERR((((uint32_t)delccarampuptap << 16) & ~((uint32_t)0x00070000)) == 0);
REG_PL_WR(AGC_RWNXAGCCCA0_ADDR, (REG_PL_RD(AGC_RWNXAGCCCA0_ADDR) & ~((uint32_t)0x00070000)) | ((uint32_t)delccarampuptap << 16));
}
/**
* @brief Returns the current value of the CCADETRAMPDN field in the RWNXAGCCCA0 register.
*
* The RWNXAGCCCA0 register will be read and the CCADETRAMPDN field's value will be returned.
*
* @return The current value of the CCADETRAMPDN field in the RWNXAGCCCA0 register.
*/
__INLINE uint8_t agc_ccadetrampdn_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCA0_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the CCADETRAMPDN field of the RWNXAGCCCA0 register.
*
* The RWNXAGCCCA0 register will be read, modified to contain the new field value, and written.
*
* @param[in] ccadetrampdn - The value to set the field to.
*/
__INLINE void agc_ccadetrampdn_setf(uint8_t ccadetrampdn)
{
ASSERT_ERR((((uint32_t)ccadetrampdn << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCCCA0_ADDR, (REG_PL_RD(AGC_RWNXAGCCCA0_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)ccadetrampdn << 8));
}
/**
* @brief Returns the current value of the CCADETRAMPUP field in the RWNXAGCCCA0 register.
*
* The RWNXAGCCCA0 register will be read and the CCADETRAMPUP field's value will be returned.
*
* @return The current value of the CCADETRAMPUP field in the RWNXAGCCCA0 register.
*/
__INLINE uint8_t agc_ccadetrampup_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCA0_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the CCADETRAMPUP field of the RWNXAGCCCA0 register.
*
* The RWNXAGCCCA0 register will be read, modified to contain the new field value, and written.
*
* @param[in] ccadetrampup - The value to set the field to.
*/
__INLINE void agc_ccadetrampup_setf(uint8_t ccadetrampup)
{
ASSERT_ERR((((uint32_t)ccadetrampup << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCCCA0_ADDR, (REG_PL_RD(AGC_RWNXAGCCCA0_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)ccadetrampup << 0));
}
/// @}
/**
* @name RWNXAGCCCA1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 28:20 INBDCCAPOWMINDBM 0x1B5
* 19:12 CCAFALLTHRDBM 0xBF
* 09 DISCCAEN 1
* 08 SATCCAEN 1
* 07:00 CCARISETHRDBM 0xC2
* </pre>
*
* @{
*/
/// Address of the RWNXAGCCCA1 register
#define AGC_RWNXAGCCCA1_ADDR 0x01002074
/// Offset of the RWNXAGCCCA1 register from the base address
#define AGC_RWNXAGCCCA1_OFFSET 0x00002074
/// Index of the RWNXAGCCCA1 register
#define AGC_RWNXAGCCCA1_INDEX 0x0000081D
/// Reset value of the RWNXAGCCCA1 register
#define AGC_RWNXAGCCCA1_RESET 0x1B5BF3C2
/**
* @brief Returns the current value of the RWNXAGCCCA1 register.
* The RWNXAGCCCA1 register will be read and its value returned.
* @return The current value of the RWNXAGCCCA1 register.
*/
__INLINE uint32_t agc_rwnxagccca1_get(void)
{
return REG_PL_RD(AGC_RWNXAGCCCA1_ADDR);
}
/**
* @brief Sets the RWNXAGCCCA1 register to a value.
* The RWNXAGCCCA1 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagccca1_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCCCA1_ADDR, value);
}
// field definitions
/// INBDCCAPOWMINDBM field mask
#define AGC_INBDCCAPOWMINDBM_MASK ((uint32_t)0x1FF00000)
/// INBDCCAPOWMINDBM field LSB position
#define AGC_INBDCCAPOWMINDBM_LSB 20
/// INBDCCAPOWMINDBM field width
#define AGC_INBDCCAPOWMINDBM_WIDTH ((uint32_t)0x00000009)
/// CCAFALLTHRDBM field mask
#define AGC_CCAFALLTHRDBM_MASK ((uint32_t)0x000FF000)
/// CCAFALLTHRDBM field LSB position
#define AGC_CCAFALLTHRDBM_LSB 12
/// CCAFALLTHRDBM field width
#define AGC_CCAFALLTHRDBM_WIDTH ((uint32_t)0x00000008)
/// DISCCAEN field bit
#define AGC_DISCCAEN_BIT ((uint32_t)0x00000200)
/// DISCCAEN field position
#define AGC_DISCCAEN_POS 9
/// SATCCAEN field bit
#define AGC_SATCCAEN_BIT ((uint32_t)0x00000100)
/// SATCCAEN field position
#define AGC_SATCCAEN_POS 8
/// CCARISETHRDBM field mask
#define AGC_CCARISETHRDBM_MASK ((uint32_t)0x000000FF)
/// CCARISETHRDBM field LSB position
#define AGC_CCARISETHRDBM_LSB 0
/// CCARISETHRDBM field width
#define AGC_CCARISETHRDBM_WIDTH ((uint32_t)0x00000008)
/// INBDCCAPOWMINDBM field reset value
#define AGC_INBDCCAPOWMINDBM_RST 0x1B5
/// CCAFALLTHRDBM field reset value
#define AGC_CCAFALLTHRDBM_RST 0xBF
/// DISCCAEN field reset value
#define AGC_DISCCAEN_RST 0x1
/// SATCCAEN field reset value
#define AGC_SATCCAEN_RST 0x1
/// CCARISETHRDBM field reset value
#define AGC_CCARISETHRDBM_RST 0xC2
/**
* @brief Constructs a value for the RWNXAGCCCA1 register given values for its fields
* and writes the value to the register.
*
* @param[in] inbdccapowmindbm - The value to use for the INBDCCAPOWMINDBM field.
* @param[in] ccafallthrdbm - The value to use for the CCAFALLTHRDBM field.
* @param[in] disccaen - The value to use for the DISCCAEN field.
* @param[in] satccaen - The value to use for the SATCCAEN field.
* @param[in] ccarisethrdbm - The value to use for the CCARISETHRDBM field.
*/
__INLINE void agc_rwnxagccca1_pack(uint16_t inbdccapowmindbm, uint8_t ccafallthrdbm, uint8_t disccaen, uint8_t satccaen, uint8_t ccarisethrdbm)
{
ASSERT_ERR((((uint32_t)inbdccapowmindbm << 20) & ~((uint32_t)0x1FF00000)) == 0);
ASSERT_ERR((((uint32_t)ccafallthrdbm << 12) & ~((uint32_t)0x000FF000)) == 0);
ASSERT_ERR((((uint32_t)disccaen << 9) & ~((uint32_t)0x00000200)) == 0);
ASSERT_ERR((((uint32_t)satccaen << 8) & ~((uint32_t)0x00000100)) == 0);
ASSERT_ERR((((uint32_t)ccarisethrdbm << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCCCA1_ADDR, ((uint32_t)inbdccapowmindbm << 20) | ((uint32_t)ccafallthrdbm << 12) | ((uint32_t)disccaen << 9) | ((uint32_t)satccaen << 8) | ((uint32_t)ccarisethrdbm << 0));
}
/**
* @brief Unpacks RWNXAGCCCA1's fields from current value of the RWNXAGCCCA1 register.
*
* Reads the RWNXAGCCCA1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] inbdccapowmindbm - Will be populated with the current value of this field from the register.
* @param[out] ccafallthrdbm - Will be populated with the current value of this field from the register.
* @param[out] disccaen - Will be populated with the current value of this field from the register.
* @param[out] satccaen - Will be populated with the current value of this field from the register.
* @param[out] ccarisethrdbm - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagccca1_unpack(uint16_t *inbdccapowmindbm, uint8_t *ccafallthrdbm, uint8_t *disccaen, uint8_t *satccaen, uint8_t *ccarisethrdbm)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCA1_ADDR);
*inbdccapowmindbm = (localVal & ((uint32_t)0x1FF00000)) >> 20;
*ccafallthrdbm = (localVal & ((uint32_t)0x000FF000)) >> 12;
*disccaen = (localVal & ((uint32_t)0x00000200)) >> 9;
*satccaen = (localVal & ((uint32_t)0x00000100)) >> 8;
*ccarisethrdbm = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the INBDCCAPOWMINDBM field in the RWNXAGCCCA1 register.
*
* The RWNXAGCCCA1 register will be read and the INBDCCAPOWMINDBM field's value will be returned.
*
* @return The current value of the INBDCCAPOWMINDBM field in the RWNXAGCCCA1 register.
*/
__INLINE uint16_t agc_inbdccapowmindbm_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCA1_ADDR);
return ((localVal & ((uint32_t)0x1FF00000)) >> 20);
}
/**
* @brief Sets the INBDCCAPOWMINDBM field of the RWNXAGCCCA1 register.
*
* The RWNXAGCCCA1 register will be read, modified to contain the new field value, and written.
*
* @param[in] inbdccapowmindbm - The value to set the field to.
*/
__INLINE void agc_inbdccapowmindbm_setf(uint16_t inbdccapowmindbm)
{
ASSERT_ERR((((uint32_t)inbdccapowmindbm << 20) & ~((uint32_t)0x1FF00000)) == 0);
REG_PL_WR(AGC_RWNXAGCCCA1_ADDR, (REG_PL_RD(AGC_RWNXAGCCCA1_ADDR) & ~((uint32_t)0x1FF00000)) | ((uint32_t)inbdccapowmindbm << 20));
}
/**
* @brief Returns the current value of the CCAFALLTHRDBM field in the RWNXAGCCCA1 register.
*
* The RWNXAGCCCA1 register will be read and the CCAFALLTHRDBM field's value will be returned.
*
* @return The current value of the CCAFALLTHRDBM field in the RWNXAGCCCA1 register.
*/
__INLINE uint8_t agc_ccafallthrdbm_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCA1_ADDR);
return ((localVal & ((uint32_t)0x000FF000)) >> 12);
}
/**
* @brief Sets the CCAFALLTHRDBM field of the RWNXAGCCCA1 register.
*
* The RWNXAGCCCA1 register will be read, modified to contain the new field value, and written.
*
* @param[in] ccafallthrdbm - The value to set the field to.
*/
__INLINE void agc_ccafallthrdbm_setf(uint8_t ccafallthrdbm)
{
ASSERT_ERR((((uint32_t)ccafallthrdbm << 12) & ~((uint32_t)0x000FF000)) == 0);
REG_PL_WR(AGC_RWNXAGCCCA1_ADDR, (REG_PL_RD(AGC_RWNXAGCCCA1_ADDR) & ~((uint32_t)0x000FF000)) | ((uint32_t)ccafallthrdbm << 12));
}
/**
* @brief Returns the current value of the DISCCAEN field in the RWNXAGCCCA1 register.
*
* The RWNXAGCCCA1 register will be read and the DISCCAEN field's value will be returned.
*
* @return The current value of the DISCCAEN field in the RWNXAGCCCA1 register.
*/
__INLINE uint8_t agc_disccaen_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCA1_ADDR);
return ((localVal & ((uint32_t)0x00000200)) >> 9);
}
/**
* @brief Sets the DISCCAEN field of the RWNXAGCCCA1 register.
*
* The RWNXAGCCCA1 register will be read, modified to contain the new field value, and written.
*
* @param[in] disccaen - The value to set the field to.
*/
__INLINE void agc_disccaen_setf(uint8_t disccaen)
{
ASSERT_ERR((((uint32_t)disccaen << 9) & ~((uint32_t)0x00000200)) == 0);
REG_PL_WR(AGC_RWNXAGCCCA1_ADDR, (REG_PL_RD(AGC_RWNXAGCCCA1_ADDR) & ~((uint32_t)0x00000200)) | ((uint32_t)disccaen << 9));
}
/**
* @brief Returns the current value of the SATCCAEN field in the RWNXAGCCCA1 register.
*
* The RWNXAGCCCA1 register will be read and the SATCCAEN field's value will be returned.
*
* @return The current value of the SATCCAEN field in the RWNXAGCCCA1 register.
*/
__INLINE uint8_t agc_satccaen_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCA1_ADDR);
return ((localVal & ((uint32_t)0x00000100)) >> 8);
}
/**
* @brief Sets the SATCCAEN field of the RWNXAGCCCA1 register.
*
* The RWNXAGCCCA1 register will be read, modified to contain the new field value, and written.
*
* @param[in] satccaen - The value to set the field to.
*/
__INLINE void agc_satccaen_setf(uint8_t satccaen)
{
ASSERT_ERR((((uint32_t)satccaen << 8) & ~((uint32_t)0x00000100)) == 0);
REG_PL_WR(AGC_RWNXAGCCCA1_ADDR, (REG_PL_RD(AGC_RWNXAGCCCA1_ADDR) & ~((uint32_t)0x00000100)) | ((uint32_t)satccaen << 8));
}
/**
* @brief Returns the current value of the CCARISETHRDBM field in the RWNXAGCCCA1 register.
*
* The RWNXAGCCCA1 register will be read and the CCARISETHRDBM field's value will be returned.
*
* @return The current value of the CCARISETHRDBM field in the RWNXAGCCCA1 register.
*/
__INLINE uint8_t agc_ccarisethrdbm_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCA1_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the CCARISETHRDBM field of the RWNXAGCCCA1 register.
*
* The RWNXAGCCCA1 register will be read, modified to contain the new field value, and written.
*
* @param[in] ccarisethrdbm - The value to set the field to.
*/
__INLINE void agc_ccarisethrdbm_setf(uint8_t ccarisethrdbm)
{
ASSERT_ERR((((uint32_t)ccarisethrdbm << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCCCA1_ADDR, (REG_PL_RD(AGC_RWNXAGCCCA1_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)ccarisethrdbm << 0));
}
/// @}
/**
* @name RWNXAGCCCACTRL register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:28 CCAFLAG3CTRL 0xA
* 27:24 CCAFLAG2CTRL 0xA
* 23:20 CCAFLAG1CTRL 0xA
* 19:16 CCAFLAG0CTRL 0xA
* 09 CCADEMOD 1
* 08 CCACSEN 1
* 06:04 CCARAMPUDEN 0x7
* 02:00 CCAENERGYEN 0x7
* </pre>
*
* @{
*/
/// Address of the RWNXAGCCCACTRL register
#define AGC_RWNXAGCCCACTRL_ADDR 0x01002078
/// Offset of the RWNXAGCCCACTRL register from the base address
#define AGC_RWNXAGCCCACTRL_OFFSET 0x00002078
/// Index of the RWNXAGCCCACTRL register
#define AGC_RWNXAGCCCACTRL_INDEX 0x0000081E
/// Reset value of the RWNXAGCCCACTRL register
#define AGC_RWNXAGCCCACTRL_RESET 0xAAAA0377
/**
* @brief Returns the current value of the RWNXAGCCCACTRL register.
* The RWNXAGCCCACTRL register will be read and its value returned.
* @return The current value of the RWNXAGCCCACTRL register.
*/
__INLINE uint32_t agc_rwnxagcccactrl_get(void)
{
return REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR);
}
/**
* @brief Sets the RWNXAGCCCACTRL register to a value.
* The RWNXAGCCCACTRL register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcccactrl_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCCCACTRL_ADDR, value);
}
// field definitions
/// CCAFLAG3CTRL field mask
#define AGC_CCAFLAG3CTRL_MASK ((uint32_t)0xF0000000)
/// CCAFLAG3CTRL field LSB position
#define AGC_CCAFLAG3CTRL_LSB 28
/// CCAFLAG3CTRL field width
#define AGC_CCAFLAG3CTRL_WIDTH ((uint32_t)0x00000004)
/// CCAFLAG2CTRL field mask
#define AGC_CCAFLAG2CTRL_MASK ((uint32_t)0x0F000000)
/// CCAFLAG2CTRL field LSB position
#define AGC_CCAFLAG2CTRL_LSB 24
/// CCAFLAG2CTRL field width
#define AGC_CCAFLAG2CTRL_WIDTH ((uint32_t)0x00000004)
/// CCAFLAG1CTRL field mask
#define AGC_CCAFLAG1CTRL_MASK ((uint32_t)0x00F00000)
/// CCAFLAG1CTRL field LSB position
#define AGC_CCAFLAG1CTRL_LSB 20
/// CCAFLAG1CTRL field width
#define AGC_CCAFLAG1CTRL_WIDTH ((uint32_t)0x00000004)
/// CCAFLAG0CTRL field mask
#define AGC_CCAFLAG0CTRL_MASK ((uint32_t)0x000F0000)
/// CCAFLAG0CTRL field LSB position
#define AGC_CCAFLAG0CTRL_LSB 16
/// CCAFLAG0CTRL field width
#define AGC_CCAFLAG0CTRL_WIDTH ((uint32_t)0x00000004)
/// CCADEMOD field bit
#define AGC_CCADEMOD_BIT ((uint32_t)0x00000200)
/// CCADEMOD field position
#define AGC_CCADEMOD_POS 9
/// CCACSEN field bit
#define AGC_CCACSEN_BIT ((uint32_t)0x00000100)
/// CCACSEN field position
#define AGC_CCACSEN_POS 8
/// CCARAMPUDEN field mask
#define AGC_CCARAMPUDEN_MASK ((uint32_t)0x00000070)
/// CCARAMPUDEN field LSB position
#define AGC_CCARAMPUDEN_LSB 4
/// CCARAMPUDEN field width
#define AGC_CCARAMPUDEN_WIDTH ((uint32_t)0x00000003)
/// CCAENERGYEN field mask
#define AGC_CCAENERGYEN_MASK ((uint32_t)0x00000007)
/// CCAENERGYEN field LSB position
#define AGC_CCAENERGYEN_LSB 0
/// CCAENERGYEN field width
#define AGC_CCAENERGYEN_WIDTH ((uint32_t)0x00000003)
/// CCAFLAG3CTRL field reset value
#define AGC_CCAFLAG3CTRL_RST 0xA
/// CCAFLAG2CTRL field reset value
#define AGC_CCAFLAG2CTRL_RST 0xA
/// CCAFLAG1CTRL field reset value
#define AGC_CCAFLAG1CTRL_RST 0xA
/// CCAFLAG0CTRL field reset value
#define AGC_CCAFLAG0CTRL_RST 0xA
/// CCADEMOD field reset value
#define AGC_CCADEMOD_RST 0x1
/// CCACSEN field reset value
#define AGC_CCACSEN_RST 0x1
/// CCARAMPUDEN field reset value
#define AGC_CCARAMPUDEN_RST 0x7
/// CCAENERGYEN field reset value
#define AGC_CCAENERGYEN_RST 0x7
/**
* @brief Constructs a value for the RWNXAGCCCACTRL register given values for its fields
* and writes the value to the register.
*
* @param[in] ccaflag3ctrl - The value to use for the CCAFLAG3CTRL field.
* @param[in] ccaflag2ctrl - The value to use for the CCAFLAG2CTRL field.
* @param[in] ccaflag1ctrl - The value to use for the CCAFLAG1CTRL field.
* @param[in] ccaflag0ctrl - The value to use for the CCAFLAG0CTRL field.
* @param[in] ccademod - The value to use for the CCADEMOD field.
* @param[in] ccacsen - The value to use for the CCACSEN field.
* @param[in] ccarampuden - The value to use for the CCARAMPUDEN field.
* @param[in] ccaenergyen - The value to use for the CCAENERGYEN field.
*/
__INLINE void agc_rwnxagcccactrl_pack(uint8_t ccaflag3ctrl, uint8_t ccaflag2ctrl, uint8_t ccaflag1ctrl, uint8_t ccaflag0ctrl, uint8_t ccademod, uint8_t ccacsen, uint8_t ccarampuden, uint8_t ccaenergyen)
{
ASSERT_ERR((((uint32_t)ccaflag3ctrl << 28) & ~((uint32_t)0xF0000000)) == 0);
ASSERT_ERR((((uint32_t)ccaflag2ctrl << 24) & ~((uint32_t)0x0F000000)) == 0);
ASSERT_ERR((((uint32_t)ccaflag1ctrl << 20) & ~((uint32_t)0x00F00000)) == 0);
ASSERT_ERR((((uint32_t)ccaflag0ctrl << 16) & ~((uint32_t)0x000F0000)) == 0);
ASSERT_ERR((((uint32_t)ccademod << 9) & ~((uint32_t)0x00000200)) == 0);
ASSERT_ERR((((uint32_t)ccacsen << 8) & ~((uint32_t)0x00000100)) == 0);
ASSERT_ERR((((uint32_t)ccarampuden << 4) & ~((uint32_t)0x00000070)) == 0);
ASSERT_ERR((((uint32_t)ccaenergyen << 0) & ~((uint32_t)0x00000007)) == 0);
REG_PL_WR(AGC_RWNXAGCCCACTRL_ADDR, ((uint32_t)ccaflag3ctrl << 28) | ((uint32_t)ccaflag2ctrl << 24) | ((uint32_t)ccaflag1ctrl << 20) | ((uint32_t)ccaflag0ctrl << 16) | ((uint32_t)ccademod << 9) | ((uint32_t)ccacsen << 8) | ((uint32_t)ccarampuden << 4) | ((uint32_t)ccaenergyen << 0));
}
/**
* @brief Unpacks RWNXAGCCCACTRL's fields from current value of the RWNXAGCCCACTRL register.
*
* Reads the RWNXAGCCCACTRL register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] ccaflag3ctrl - Will be populated with the current value of this field from the register.
* @param[out] ccaflag2ctrl - Will be populated with the current value of this field from the register.
* @param[out] ccaflag1ctrl - Will be populated with the current value of this field from the register.
* @param[out] ccaflag0ctrl - Will be populated with the current value of this field from the register.
* @param[out] ccademod - Will be populated with the current value of this field from the register.
* @param[out] ccacsen - Will be populated with the current value of this field from the register.
* @param[out] ccarampuden - Will be populated with the current value of this field from the register.
* @param[out] ccaenergyen - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcccactrl_unpack(uint8_t *ccaflag3ctrl, uint8_t *ccaflag2ctrl, uint8_t *ccaflag1ctrl, uint8_t *ccaflag0ctrl, uint8_t *ccademod, uint8_t *ccacsen, uint8_t *ccarampuden, uint8_t *ccaenergyen)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR);
*ccaflag3ctrl = (localVal & ((uint32_t)0xF0000000)) >> 28;
*ccaflag2ctrl = (localVal & ((uint32_t)0x0F000000)) >> 24;
*ccaflag1ctrl = (localVal & ((uint32_t)0x00F00000)) >> 20;
*ccaflag0ctrl = (localVal & ((uint32_t)0x000F0000)) >> 16;
*ccademod = (localVal & ((uint32_t)0x00000200)) >> 9;
*ccacsen = (localVal & ((uint32_t)0x00000100)) >> 8;
*ccarampuden = (localVal & ((uint32_t)0x00000070)) >> 4;
*ccaenergyen = (localVal & ((uint32_t)0x00000007)) >> 0;
}
/**
* @brief Returns the current value of the CCAFLAG3CTRL field in the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read and the CCAFLAG3CTRL field's value will be returned.
*
* @return The current value of the CCAFLAG3CTRL field in the RWNXAGCCCACTRL register.
*/
__INLINE uint8_t agc_ccaflag3ctrl_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR);
return ((localVal & ((uint32_t)0xF0000000)) >> 28);
}
/**
* @brief Sets the CCAFLAG3CTRL field of the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] ccaflag3ctrl - The value to set the field to.
*/
__INLINE void agc_ccaflag3ctrl_setf(uint8_t ccaflag3ctrl)
{
ASSERT_ERR((((uint32_t)ccaflag3ctrl << 28) & ~((uint32_t)0xF0000000)) == 0);
REG_PL_WR(AGC_RWNXAGCCCACTRL_ADDR, (REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR) & ~((uint32_t)0xF0000000)) | ((uint32_t)ccaflag3ctrl << 28));
}
/**
* @brief Returns the current value of the CCAFLAG2CTRL field in the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read and the CCAFLAG2CTRL field's value will be returned.
*
* @return The current value of the CCAFLAG2CTRL field in the RWNXAGCCCACTRL register.
*/
__INLINE uint8_t agc_ccaflag2ctrl_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR);
return ((localVal & ((uint32_t)0x0F000000)) >> 24);
}
/**
* @brief Sets the CCAFLAG2CTRL field of the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] ccaflag2ctrl - The value to set the field to.
*/
__INLINE void agc_ccaflag2ctrl_setf(uint8_t ccaflag2ctrl)
{
ASSERT_ERR((((uint32_t)ccaflag2ctrl << 24) & ~((uint32_t)0x0F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCCCACTRL_ADDR, (REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR) & ~((uint32_t)0x0F000000)) | ((uint32_t)ccaflag2ctrl << 24));
}
/**
* @brief Returns the current value of the CCAFLAG1CTRL field in the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read and the CCAFLAG1CTRL field's value will be returned.
*
* @return The current value of the CCAFLAG1CTRL field in the RWNXAGCCCACTRL register.
*/
__INLINE uint8_t agc_ccaflag1ctrl_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR);
return ((localVal & ((uint32_t)0x00F00000)) >> 20);
}
/**
* @brief Sets the CCAFLAG1CTRL field of the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] ccaflag1ctrl - The value to set the field to.
*/
__INLINE void agc_ccaflag1ctrl_setf(uint8_t ccaflag1ctrl)
{
ASSERT_ERR((((uint32_t)ccaflag1ctrl << 20) & ~((uint32_t)0x00F00000)) == 0);
REG_PL_WR(AGC_RWNXAGCCCACTRL_ADDR, (REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR) & ~((uint32_t)0x00F00000)) | ((uint32_t)ccaflag1ctrl << 20));
}
/**
* @brief Returns the current value of the CCAFLAG0CTRL field in the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read and the CCAFLAG0CTRL field's value will be returned.
*
* @return The current value of the CCAFLAG0CTRL field in the RWNXAGCCCACTRL register.
*/
__INLINE uint8_t agc_ccaflag0ctrl_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR);
return ((localVal & ((uint32_t)0x000F0000)) >> 16);
}
/**
* @brief Sets the CCAFLAG0CTRL field of the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] ccaflag0ctrl - The value to set the field to.
*/
__INLINE void agc_ccaflag0ctrl_setf(uint8_t ccaflag0ctrl)
{
ASSERT_ERR((((uint32_t)ccaflag0ctrl << 16) & ~((uint32_t)0x000F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCCCACTRL_ADDR, (REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR) & ~((uint32_t)0x000F0000)) | ((uint32_t)ccaflag0ctrl << 16));
}
/**
* @brief Returns the current value of the CCADEMOD field in the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read and the CCADEMOD field's value will be returned.
*
* @return The current value of the CCADEMOD field in the RWNXAGCCCACTRL register.
*/
__INLINE uint8_t agc_ccademod_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR);
return ((localVal & ((uint32_t)0x00000200)) >> 9);
}
/**
* @brief Sets the CCADEMOD field of the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] ccademod - The value to set the field to.
*/
__INLINE void agc_ccademod_setf(uint8_t ccademod)
{
ASSERT_ERR((((uint32_t)ccademod << 9) & ~((uint32_t)0x00000200)) == 0);
REG_PL_WR(AGC_RWNXAGCCCACTRL_ADDR, (REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR) & ~((uint32_t)0x00000200)) | ((uint32_t)ccademod << 9));
}
/**
* @brief Returns the current value of the CCACSEN field in the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read and the CCACSEN field's value will be returned.
*
* @return The current value of the CCACSEN field in the RWNXAGCCCACTRL register.
*/
__INLINE uint8_t agc_ccacsen_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR);
return ((localVal & ((uint32_t)0x00000100)) >> 8);
}
/**
* @brief Sets the CCACSEN field of the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] ccacsen - The value to set the field to.
*/
__INLINE void agc_ccacsen_setf(uint8_t ccacsen)
{
ASSERT_ERR((((uint32_t)ccacsen << 8) & ~((uint32_t)0x00000100)) == 0);
REG_PL_WR(AGC_RWNXAGCCCACTRL_ADDR, (REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR) & ~((uint32_t)0x00000100)) | ((uint32_t)ccacsen << 8));
}
/**
* @brief Returns the current value of the CCARAMPUDEN field in the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read and the CCARAMPUDEN field's value will be returned.
*
* @return The current value of the CCARAMPUDEN field in the RWNXAGCCCACTRL register.
*/
__INLINE uint8_t agc_ccarampuden_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR);
return ((localVal & ((uint32_t)0x00000070)) >> 4);
}
/**
* @brief Sets the CCARAMPUDEN field of the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] ccarampuden - The value to set the field to.
*/
__INLINE void agc_ccarampuden_setf(uint8_t ccarampuden)
{
ASSERT_ERR((((uint32_t)ccarampuden << 4) & ~((uint32_t)0x00000070)) == 0);
REG_PL_WR(AGC_RWNXAGCCCACTRL_ADDR, (REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR) & ~((uint32_t)0x00000070)) | ((uint32_t)ccarampuden << 4));
}
/**
* @brief Returns the current value of the CCAENERGYEN field in the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read and the CCAENERGYEN field's value will be returned.
*
* @return The current value of the CCAENERGYEN field in the RWNXAGCCCACTRL register.
*/
__INLINE uint8_t agc_ccaenergyen_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR);
return ((localVal & ((uint32_t)0x00000007)) >> 0);
}
/**
* @brief Sets the CCAENERGYEN field of the RWNXAGCCCACTRL register.
*
* The RWNXAGCCCACTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] ccaenergyen - The value to set the field to.
*/
__INLINE void agc_ccaenergyen_setf(uint8_t ccaenergyen)
{
ASSERT_ERR((((uint32_t)ccaenergyen << 0) & ~((uint32_t)0x00000007)) == 0);
REG_PL_WR(AGC_RWNXAGCCCACTRL_ADDR, (REG_PL_RD(AGC_RWNXAGCCCACTRL_ADDR) & ~((uint32_t)0x00000007)) | ((uint32_t)ccaenergyen << 0));
}
/// @}
/**
* @name RWNXAGCCCASTATE0 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 26:16 RXSTATECCA20SSEL 0xD4
* 10:00 RXSTATECCA20PSEL 0x6FE
* </pre>
*
* @{
*/
/// Address of the RWNXAGCCCASTATE0 register
#define AGC_RWNXAGCCCASTATE0_ADDR 0x0100207C
/// Offset of the RWNXAGCCCASTATE0 register from the base address
#define AGC_RWNXAGCCCASTATE0_OFFSET 0x0000207C
/// Index of the RWNXAGCCCASTATE0 register
#define AGC_RWNXAGCCCASTATE0_INDEX 0x0000081F
/// Reset value of the RWNXAGCCCASTATE0 register
#define AGC_RWNXAGCCCASTATE0_RESET 0x00D406FE
/**
* @brief Returns the current value of the RWNXAGCCCASTATE0 register.
* The RWNXAGCCCASTATE0 register will be read and its value returned.
* @return The current value of the RWNXAGCCCASTATE0 register.
*/
__INLINE uint32_t agc_rwnxagcccastate0_get(void)
{
return REG_PL_RD(AGC_RWNXAGCCCASTATE0_ADDR);
}
/**
* @brief Sets the RWNXAGCCCASTATE0 register to a value.
* The RWNXAGCCCASTATE0 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcccastate0_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCCCASTATE0_ADDR, value);
}
// field definitions
/// RXSTATECCA20SSEL field mask
#define AGC_RXSTATECCA20SSEL_MASK ((uint32_t)0x07FF0000)
/// RXSTATECCA20SSEL field LSB position
#define AGC_RXSTATECCA20SSEL_LSB 16
/// RXSTATECCA20SSEL field width
#define AGC_RXSTATECCA20SSEL_WIDTH ((uint32_t)0x0000000B)
/// RXSTATECCA20PSEL field mask
#define AGC_RXSTATECCA20PSEL_MASK ((uint32_t)0x000007FF)
/// RXSTATECCA20PSEL field LSB position
#define AGC_RXSTATECCA20PSEL_LSB 0
/// RXSTATECCA20PSEL field width
#define AGC_RXSTATECCA20PSEL_WIDTH ((uint32_t)0x0000000B)
/// RXSTATECCA20SSEL field reset value
#define AGC_RXSTATECCA20SSEL_RST 0xD4
/// RXSTATECCA20PSEL field reset value
#define AGC_RXSTATECCA20PSEL_RST 0x6FE
/**
* @brief Constructs a value for the RWNXAGCCCASTATE0 register given values for its fields
* and writes the value to the register.
*
* @param[in] rxstatecca20ssel - The value to use for the RXSTATECCA20SSEL field.
* @param[in] rxstatecca20psel - The value to use for the RXSTATECCA20PSEL field.
*/
__INLINE void agc_rwnxagcccastate0_pack(uint16_t rxstatecca20ssel, uint16_t rxstatecca20psel)
{
ASSERT_ERR((((uint32_t)rxstatecca20ssel << 16) & ~((uint32_t)0x07FF0000)) == 0);
ASSERT_ERR((((uint32_t)rxstatecca20psel << 0) & ~((uint32_t)0x000007FF)) == 0);
REG_PL_WR(AGC_RWNXAGCCCASTATE0_ADDR, ((uint32_t)rxstatecca20ssel << 16) | ((uint32_t)rxstatecca20psel << 0));
}
/**
* @brief Unpacks RWNXAGCCCASTATE0's fields from current value of the RWNXAGCCCASTATE0 register.
*
* Reads the RWNXAGCCCASTATE0 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] rxstatecca20ssel - Will be populated with the current value of this field from the register.
* @param[out] rxstatecca20psel - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcccastate0_unpack(uint16_t *rxstatecca20ssel, uint16_t *rxstatecca20psel)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCASTATE0_ADDR);
*rxstatecca20ssel = (localVal & ((uint32_t)0x07FF0000)) >> 16;
*rxstatecca20psel = (localVal & ((uint32_t)0x000007FF)) >> 0;
}
/**
* @brief Returns the current value of the RXSTATECCA20SSEL field in the RWNXAGCCCASTATE0 register.
*
* The RWNXAGCCCASTATE0 register will be read and the RXSTATECCA20SSEL field's value will be returned.
*
* @return The current value of the RXSTATECCA20SSEL field in the RWNXAGCCCASTATE0 register.
*/
__INLINE uint16_t agc_rxstatecca20ssel_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCASTATE0_ADDR);
return ((localVal & ((uint32_t)0x07FF0000)) >> 16);
}
/**
* @brief Sets the RXSTATECCA20SSEL field of the RWNXAGCCCASTATE0 register.
*
* The RWNXAGCCCASTATE0 register will be read, modified to contain the new field value, and written.
*
* @param[in] rxstatecca20ssel - The value to set the field to.
*/
__INLINE void agc_rxstatecca20ssel_setf(uint16_t rxstatecca20ssel)
{
ASSERT_ERR((((uint32_t)rxstatecca20ssel << 16) & ~((uint32_t)0x07FF0000)) == 0);
REG_PL_WR(AGC_RWNXAGCCCASTATE0_ADDR, (REG_PL_RD(AGC_RWNXAGCCCASTATE0_ADDR) & ~((uint32_t)0x07FF0000)) | ((uint32_t)rxstatecca20ssel << 16));
}
/**
* @brief Returns the current value of the RXSTATECCA20PSEL field in the RWNXAGCCCASTATE0 register.
*
* The RWNXAGCCCASTATE0 register will be read and the RXSTATECCA20PSEL field's value will be returned.
*
* @return The current value of the RXSTATECCA20PSEL field in the RWNXAGCCCASTATE0 register.
*/
__INLINE uint16_t agc_rxstatecca20psel_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCASTATE0_ADDR);
return ((localVal & ((uint32_t)0x000007FF)) >> 0);
}
/**
* @brief Sets the RXSTATECCA20PSEL field of the RWNXAGCCCASTATE0 register.
*
* The RWNXAGCCCASTATE0 register will be read, modified to contain the new field value, and written.
*
* @param[in] rxstatecca20psel - The value to set the field to.
*/
__INLINE void agc_rxstatecca20psel_setf(uint16_t rxstatecca20psel)
{
ASSERT_ERR((((uint32_t)rxstatecca20psel << 0) & ~((uint32_t)0x000007FF)) == 0);
REG_PL_WR(AGC_RWNXAGCCCASTATE0_ADDR, (REG_PL_RD(AGC_RWNXAGCCCASTATE0_ADDR) & ~((uint32_t)0x000007FF)) | ((uint32_t)rxstatecca20psel << 0));
}
/// @}
/**
* @name RWNXAGCCCASTATE1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 10:00 RXSTATECCA40SSEL 0x80
* </pre>
*
* @{
*/
/// Address of the RWNXAGCCCASTATE1 register
#define AGC_RWNXAGCCCASTATE1_ADDR 0x01002080
/// Offset of the RWNXAGCCCASTATE1 register from the base address
#define AGC_RWNXAGCCCASTATE1_OFFSET 0x00002080
/// Index of the RWNXAGCCCASTATE1 register
#define AGC_RWNXAGCCCASTATE1_INDEX 0x00000820
/// Reset value of the RWNXAGCCCASTATE1 register
#define AGC_RWNXAGCCCASTATE1_RESET 0x00000080
/**
* @brief Returns the current value of the RWNXAGCCCASTATE1 register.
* The RWNXAGCCCASTATE1 register will be read and its value returned.
* @return The current value of the RWNXAGCCCASTATE1 register.
*/
__INLINE uint32_t agc_rwnxagcccastate1_get(void)
{
return REG_PL_RD(AGC_RWNXAGCCCASTATE1_ADDR);
}
/**
* @brief Sets the RWNXAGCCCASTATE1 register to a value.
* The RWNXAGCCCASTATE1 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcccastate1_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCCCASTATE1_ADDR, value);
}
// field definitions
/// RXSTATECCA40SSEL field mask
#define AGC_RXSTATECCA40SSEL_MASK ((uint32_t)0x000007FF)
/// RXSTATECCA40SSEL field LSB position
#define AGC_RXSTATECCA40SSEL_LSB 0
/// RXSTATECCA40SSEL field width
#define AGC_RXSTATECCA40SSEL_WIDTH ((uint32_t)0x0000000B)
/// RXSTATECCA40SSEL field reset value
#define AGC_RXSTATECCA40SSEL_RST 0x80
/**
* @brief Returns the current value of the RXSTATECCA40SSEL field in the RWNXAGCCCASTATE1 register.
*
* The RWNXAGCCCASTATE1 register will be read and the RXSTATECCA40SSEL field's value will be returned.
*
* @return The current value of the RXSTATECCA40SSEL field in the RWNXAGCCCASTATE1 register.
*/
__INLINE uint16_t agc_rxstatecca40ssel_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCASTATE1_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0x000007FF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the RXSTATECCA40SSEL field of the RWNXAGCCCASTATE1 register.
*
* The RWNXAGCCCASTATE1 register will be read, modified to contain the new field value, and written.
*
* @param[in] rxstatecca40ssel - The value to set the field to.
*/
__INLINE void agc_rxstatecca40ssel_setf(uint16_t rxstatecca40ssel)
{
ASSERT_ERR((((uint32_t)rxstatecca40ssel << 0) & ~((uint32_t)0x000007FF)) == 0);
REG_PL_WR(AGC_RWNXAGCCCASTATE1_ADDR, (uint32_t)rxstatecca40ssel << 0);
}
/// @}
/**
* @name RWNXAGCCCATIMEOUT register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 CCATIMEOUT 0x9312A
* </pre>
*
* @{
*/
/// Address of the RWNXAGCCCATIMEOUT register
#define AGC_RWNXAGCCCATIMEOUT_ADDR 0x01002084
/// Offset of the RWNXAGCCCATIMEOUT register from the base address
#define AGC_RWNXAGCCCATIMEOUT_OFFSET 0x00002084
/// Index of the RWNXAGCCCATIMEOUT register
#define AGC_RWNXAGCCCATIMEOUT_INDEX 0x00000821
/// Reset value of the RWNXAGCCCATIMEOUT register
#define AGC_RWNXAGCCCATIMEOUT_RESET 0x0009312A
/**
* @brief Returns the current value of the RWNXAGCCCATIMEOUT register.
* The RWNXAGCCCATIMEOUT register will be read and its value returned.
* @return The current value of the RWNXAGCCCATIMEOUT register.
*/
__INLINE uint32_t agc_rwnxagcccatimeout_get(void)
{
return REG_PL_RD(AGC_RWNXAGCCCATIMEOUT_ADDR);
}
/**
* @brief Sets the RWNXAGCCCATIMEOUT register to a value.
* The RWNXAGCCCATIMEOUT register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcccatimeout_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCCCATIMEOUT_ADDR, value);
}
// field definitions
/// CCATIMEOUT field mask
#define AGC_CCATIMEOUT_MASK ((uint32_t)0xFFFFFFFF)
/// CCATIMEOUT field LSB position
#define AGC_CCATIMEOUT_LSB 0
/// CCATIMEOUT field width
#define AGC_CCATIMEOUT_WIDTH ((uint32_t)0x00000020)
/// CCATIMEOUT field reset value
#define AGC_CCATIMEOUT_RST 0x9312A
/**
* @brief Returns the current value of the CCATIMEOUT field in the RWNXAGCCCATIMEOUT register.
*
* The RWNXAGCCCATIMEOUT register will be read and the CCATIMEOUT field's value will be returned.
*
* @return The current value of the CCATIMEOUT field in the RWNXAGCCCATIMEOUT register.
*/
__INLINE uint32_t agc_ccatimeout_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCCATIMEOUT_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the CCATIMEOUT field of the RWNXAGCCCATIMEOUT register.
*
* The RWNXAGCCCATIMEOUT register will be read, modified to contain the new field value, and written.
*
* @param[in] ccatimeout - The value to set the field to.
*/
__INLINE void agc_ccatimeout_setf(uint32_t ccatimeout)
{
ASSERT_ERR((((uint32_t)ccatimeout << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(AGC_RWNXAGCCCATIMEOUT_ADDR, (uint32_t)ccatimeout << 0);
}
/// @}
/**
* @name RWNXAGCSNR0 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23:20 NFVGATHRM2 0xA
* 19:16 NFVGATHRM1 0x8
* 15:12 NFVGATHRM0 0x6
* 11:08 NFVGATHRL2 0xA
* 07:04 NFVGATHRL1 0x8
* 03:00 NFVGATHRL0 0x6
* </pre>
*
* @{
*/
/// Address of the RWNXAGCSNR0 register
#define AGC_RWNXAGCSNR0_ADDR 0x01002088
/// Offset of the RWNXAGCSNR0 register from the base address
#define AGC_RWNXAGCSNR0_OFFSET 0x00002088
/// Index of the RWNXAGCSNR0 register
#define AGC_RWNXAGCSNR0_INDEX 0x00000822
/// Reset value of the RWNXAGCSNR0 register
#define AGC_RWNXAGCSNR0_RESET 0x00A86A86
/**
* @brief Returns the current value of the RWNXAGCSNR0 register.
* The RWNXAGCSNR0 register will be read and its value returned.
* @return The current value of the RWNXAGCSNR0 register.
*/
__INLINE uint32_t agc_rwnxagcsnr0_get(void)
{
return REG_PL_RD(AGC_RWNXAGCSNR0_ADDR);
}
/**
* @brief Sets the RWNXAGCSNR0 register to a value.
* The RWNXAGCSNR0 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcsnr0_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCSNR0_ADDR, value);
}
// field definitions
/// NFVGATHRM2 field mask
#define AGC_NFVGATHRM2_MASK ((uint32_t)0x00F00000)
/// NFVGATHRM2 field LSB position
#define AGC_NFVGATHRM2_LSB 20
/// NFVGATHRM2 field width
#define AGC_NFVGATHRM2_WIDTH ((uint32_t)0x00000004)
/// NFVGATHRM1 field mask
#define AGC_NFVGATHRM1_MASK ((uint32_t)0x000F0000)
/// NFVGATHRM1 field LSB position
#define AGC_NFVGATHRM1_LSB 16
/// NFVGATHRM1 field width
#define AGC_NFVGATHRM1_WIDTH ((uint32_t)0x00000004)
/// NFVGATHRM0 field mask
#define AGC_NFVGATHRM0_MASK ((uint32_t)0x0000F000)
/// NFVGATHRM0 field LSB position
#define AGC_NFVGATHRM0_LSB 12
/// NFVGATHRM0 field width
#define AGC_NFVGATHRM0_WIDTH ((uint32_t)0x00000004)
/// NFVGATHRL2 field mask
#define AGC_NFVGATHRL2_MASK ((uint32_t)0x00000F00)
/// NFVGATHRL2 field LSB position
#define AGC_NFVGATHRL2_LSB 8
/// NFVGATHRL2 field width
#define AGC_NFVGATHRL2_WIDTH ((uint32_t)0x00000004)
/// NFVGATHRL1 field mask
#define AGC_NFVGATHRL1_MASK ((uint32_t)0x000000F0)
/// NFVGATHRL1 field LSB position
#define AGC_NFVGATHRL1_LSB 4
/// NFVGATHRL1 field width
#define AGC_NFVGATHRL1_WIDTH ((uint32_t)0x00000004)
/// NFVGATHRL0 field mask
#define AGC_NFVGATHRL0_MASK ((uint32_t)0x0000000F)
/// NFVGATHRL0 field LSB position
#define AGC_NFVGATHRL0_LSB 0
/// NFVGATHRL0 field width
#define AGC_NFVGATHRL0_WIDTH ((uint32_t)0x00000004)
/// NFVGATHRM2 field reset value
#define AGC_NFVGATHRM2_RST 0xA
/// NFVGATHRM1 field reset value
#define AGC_NFVGATHRM1_RST 0x8
/// NFVGATHRM0 field reset value
#define AGC_NFVGATHRM0_RST 0x6
/// NFVGATHRL2 field reset value
#define AGC_NFVGATHRL2_RST 0xA
/// NFVGATHRL1 field reset value
#define AGC_NFVGATHRL1_RST 0x8
/// NFVGATHRL0 field reset value
#define AGC_NFVGATHRL0_RST 0x6
/**
* @brief Constructs a value for the RWNXAGCSNR0 register given values for its fields
* and writes the value to the register.
*
* @param[in] nfvgathrm2 - The value to use for the NFVGATHRM2 field.
* @param[in] nfvgathrm1 - The value to use for the NFVGATHRM1 field.
* @param[in] nfvgathrm0 - The value to use for the NFVGATHRM0 field.
* @param[in] nfvgathrl2 - The value to use for the NFVGATHRL2 field.
* @param[in] nfvgathrl1 - The value to use for the NFVGATHRL1 field.
* @param[in] nfvgathrl0 - The value to use for the NFVGATHRL0 field.
*/
__INLINE void agc_rwnxagcsnr0_pack(uint8_t nfvgathrm2, uint8_t nfvgathrm1, uint8_t nfvgathrm0, uint8_t nfvgathrl2, uint8_t nfvgathrl1, uint8_t nfvgathrl0)
{
ASSERT_ERR((((uint32_t)nfvgathrm2 << 20) & ~((uint32_t)0x00F00000)) == 0);
ASSERT_ERR((((uint32_t)nfvgathrm1 << 16) & ~((uint32_t)0x000F0000)) == 0);
ASSERT_ERR((((uint32_t)nfvgathrm0 << 12) & ~((uint32_t)0x0000F000)) == 0);
ASSERT_ERR((((uint32_t)nfvgathrl2 << 8) & ~((uint32_t)0x00000F00)) == 0);
ASSERT_ERR((((uint32_t)nfvgathrl1 << 4) & ~((uint32_t)0x000000F0)) == 0);
ASSERT_ERR((((uint32_t)nfvgathrl0 << 0) & ~((uint32_t)0x0000000F)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR0_ADDR, ((uint32_t)nfvgathrm2 << 20) | ((uint32_t)nfvgathrm1 << 16) | ((uint32_t)nfvgathrm0 << 12) | ((uint32_t)nfvgathrl2 << 8) | ((uint32_t)nfvgathrl1 << 4) | ((uint32_t)nfvgathrl0 << 0));
}
/**
* @brief Unpacks RWNXAGCSNR0's fields from current value of the RWNXAGCSNR0 register.
*
* Reads the RWNXAGCSNR0 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] nfvgathrm2 - Will be populated with the current value of this field from the register.
* @param[out] nfvgathrm1 - Will be populated with the current value of this field from the register.
* @param[out] nfvgathrm0 - Will be populated with the current value of this field from the register.
* @param[out] nfvgathrl2 - Will be populated with the current value of this field from the register.
* @param[out] nfvgathrl1 - Will be populated with the current value of this field from the register.
* @param[out] nfvgathrl0 - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcsnr0_unpack(uint8_t *nfvgathrm2, uint8_t *nfvgathrm1, uint8_t *nfvgathrm0, uint8_t *nfvgathrl2, uint8_t *nfvgathrl1, uint8_t *nfvgathrl0)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR0_ADDR);
*nfvgathrm2 = (localVal & ((uint32_t)0x00F00000)) >> 20;
*nfvgathrm1 = (localVal & ((uint32_t)0x000F0000)) >> 16;
*nfvgathrm0 = (localVal & ((uint32_t)0x0000F000)) >> 12;
*nfvgathrl2 = (localVal & ((uint32_t)0x00000F00)) >> 8;
*nfvgathrl1 = (localVal & ((uint32_t)0x000000F0)) >> 4;
*nfvgathrl0 = (localVal & ((uint32_t)0x0000000F)) >> 0;
}
/**
* @brief Returns the current value of the NFVGATHRM2 field in the RWNXAGCSNR0 register.
*
* The RWNXAGCSNR0 register will be read and the NFVGATHRM2 field's value will be returned.
*
* @return The current value of the NFVGATHRM2 field in the RWNXAGCSNR0 register.
*/
__INLINE uint8_t agc_nfvgathrm2_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR0_ADDR);
return ((localVal & ((uint32_t)0x00F00000)) >> 20);
}
/**
* @brief Sets the NFVGATHRM2 field of the RWNXAGCSNR0 register.
*
* The RWNXAGCSNR0 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvgathrm2 - The value to set the field to.
*/
__INLINE void agc_nfvgathrm2_setf(uint8_t nfvgathrm2)
{
ASSERT_ERR((((uint32_t)nfvgathrm2 << 20) & ~((uint32_t)0x00F00000)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR0_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR0_ADDR) & ~((uint32_t)0x00F00000)) | ((uint32_t)nfvgathrm2 << 20));
}
/**
* @brief Returns the current value of the NFVGATHRM1 field in the RWNXAGCSNR0 register.
*
* The RWNXAGCSNR0 register will be read and the NFVGATHRM1 field's value will be returned.
*
* @return The current value of the NFVGATHRM1 field in the RWNXAGCSNR0 register.
*/
__INLINE uint8_t agc_nfvgathrm1_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR0_ADDR);
return ((localVal & ((uint32_t)0x000F0000)) >> 16);
}
/**
* @brief Sets the NFVGATHRM1 field of the RWNXAGCSNR0 register.
*
* The RWNXAGCSNR0 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvgathrm1 - The value to set the field to.
*/
__INLINE void agc_nfvgathrm1_setf(uint8_t nfvgathrm1)
{
ASSERT_ERR((((uint32_t)nfvgathrm1 << 16) & ~((uint32_t)0x000F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR0_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR0_ADDR) & ~((uint32_t)0x000F0000)) | ((uint32_t)nfvgathrm1 << 16));
}
/**
* @brief Returns the current value of the NFVGATHRM0 field in the RWNXAGCSNR0 register.
*
* The RWNXAGCSNR0 register will be read and the NFVGATHRM0 field's value will be returned.
*
* @return The current value of the NFVGATHRM0 field in the RWNXAGCSNR0 register.
*/
__INLINE uint8_t agc_nfvgathrm0_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR0_ADDR);
return ((localVal & ((uint32_t)0x0000F000)) >> 12);
}
/**
* @brief Sets the NFVGATHRM0 field of the RWNXAGCSNR0 register.
*
* The RWNXAGCSNR0 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvgathrm0 - The value to set the field to.
*/
__INLINE void agc_nfvgathrm0_setf(uint8_t nfvgathrm0)
{
ASSERT_ERR((((uint32_t)nfvgathrm0 << 12) & ~((uint32_t)0x0000F000)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR0_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR0_ADDR) & ~((uint32_t)0x0000F000)) | ((uint32_t)nfvgathrm0 << 12));
}
/**
* @brief Returns the current value of the NFVGATHRL2 field in the RWNXAGCSNR0 register.
*
* The RWNXAGCSNR0 register will be read and the NFVGATHRL2 field's value will be returned.
*
* @return The current value of the NFVGATHRL2 field in the RWNXAGCSNR0 register.
*/
__INLINE uint8_t agc_nfvgathrl2_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR0_ADDR);
return ((localVal & ((uint32_t)0x00000F00)) >> 8);
}
/**
* @brief Sets the NFVGATHRL2 field of the RWNXAGCSNR0 register.
*
* The RWNXAGCSNR0 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvgathrl2 - The value to set the field to.
*/
__INLINE void agc_nfvgathrl2_setf(uint8_t nfvgathrl2)
{
ASSERT_ERR((((uint32_t)nfvgathrl2 << 8) & ~((uint32_t)0x00000F00)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR0_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR0_ADDR) & ~((uint32_t)0x00000F00)) | ((uint32_t)nfvgathrl2 << 8));
}
/**
* @brief Returns the current value of the NFVGATHRL1 field in the RWNXAGCSNR0 register.
*
* The RWNXAGCSNR0 register will be read and the NFVGATHRL1 field's value will be returned.
*
* @return The current value of the NFVGATHRL1 field in the RWNXAGCSNR0 register.
*/
__INLINE uint8_t agc_nfvgathrl1_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR0_ADDR);
return ((localVal & ((uint32_t)0x000000F0)) >> 4);
}
/**
* @brief Sets the NFVGATHRL1 field of the RWNXAGCSNR0 register.
*
* The RWNXAGCSNR0 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvgathrl1 - The value to set the field to.
*/
__INLINE void agc_nfvgathrl1_setf(uint8_t nfvgathrl1)
{
ASSERT_ERR((((uint32_t)nfvgathrl1 << 4) & ~((uint32_t)0x000000F0)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR0_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR0_ADDR) & ~((uint32_t)0x000000F0)) | ((uint32_t)nfvgathrl1 << 4));
}
/**
* @brief Returns the current value of the NFVGATHRL0 field in the RWNXAGCSNR0 register.
*
* The RWNXAGCSNR0 register will be read and the NFVGATHRL0 field's value will be returned.
*
* @return The current value of the NFVGATHRL0 field in the RWNXAGCSNR0 register.
*/
__INLINE uint8_t agc_nfvgathrl0_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR0_ADDR);
return ((localVal & ((uint32_t)0x0000000F)) >> 0);
}
/**
* @brief Sets the NFVGATHRL0 field of the RWNXAGCSNR0 register.
*
* The RWNXAGCSNR0 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvgathrl0 - The value to set the field to.
*/
__INLINE void agc_nfvgathrl0_setf(uint8_t nfvgathrl0)
{
ASSERT_ERR((((uint32_t)nfvgathrl0 << 0) & ~((uint32_t)0x0000000F)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR0_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR0_ADDR) & ~((uint32_t)0x0000000F)) | ((uint32_t)nfvgathrl0 << 0));
}
/// @}
/**
* @name RWNXAGCSNR1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 24 SNRMEASSEL 0
* 11:08 NFVGATHRH2 0xA
* 07:04 NFVGATHRH1 0x8
* 03:00 NFVGATHRH0 0x6
* </pre>
*
* @{
*/
/// Address of the RWNXAGCSNR1 register
#define AGC_RWNXAGCSNR1_ADDR 0x0100208C
/// Offset of the RWNXAGCSNR1 register from the base address
#define AGC_RWNXAGCSNR1_OFFSET 0x0000208C
/// Index of the RWNXAGCSNR1 register
#define AGC_RWNXAGCSNR1_INDEX 0x00000823
/// Reset value of the RWNXAGCSNR1 register
#define AGC_RWNXAGCSNR1_RESET 0x00000A86
/**
* @brief Returns the current value of the RWNXAGCSNR1 register.
* The RWNXAGCSNR1 register will be read and its value returned.
* @return The current value of the RWNXAGCSNR1 register.
*/
__INLINE uint32_t agc_rwnxagcsnr1_get(void)
{
return REG_PL_RD(AGC_RWNXAGCSNR1_ADDR);
}
/**
* @brief Sets the RWNXAGCSNR1 register to a value.
* The RWNXAGCSNR1 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcsnr1_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCSNR1_ADDR, value);
}
// field definitions
/// SNRMEASSEL field bit
#define AGC_SNRMEASSEL_BIT ((uint32_t)0x01000000)
/// SNRMEASSEL field position
#define AGC_SNRMEASSEL_POS 24
/// NFVGATHRH2 field mask
#define AGC_NFVGATHRH2_MASK ((uint32_t)0x00000F00)
/// NFVGATHRH2 field LSB position
#define AGC_NFVGATHRH2_LSB 8
/// NFVGATHRH2 field width
#define AGC_NFVGATHRH2_WIDTH ((uint32_t)0x00000004)
/// NFVGATHRH1 field mask
#define AGC_NFVGATHRH1_MASK ((uint32_t)0x000000F0)
/// NFVGATHRH1 field LSB position
#define AGC_NFVGATHRH1_LSB 4
/// NFVGATHRH1 field width
#define AGC_NFVGATHRH1_WIDTH ((uint32_t)0x00000004)
/// NFVGATHRH0 field mask
#define AGC_NFVGATHRH0_MASK ((uint32_t)0x0000000F)
/// NFVGATHRH0 field LSB position
#define AGC_NFVGATHRH0_LSB 0
/// NFVGATHRH0 field width
#define AGC_NFVGATHRH0_WIDTH ((uint32_t)0x00000004)
/// SNRMEASSEL field reset value
#define AGC_SNRMEASSEL_RST 0x0
/// NFVGATHRH2 field reset value
#define AGC_NFVGATHRH2_RST 0xA
/// NFVGATHRH1 field reset value
#define AGC_NFVGATHRH1_RST 0x8
/// NFVGATHRH0 field reset value
#define AGC_NFVGATHRH0_RST 0x6
/**
* @brief Constructs a value for the RWNXAGCSNR1 register given values for its fields
* and writes the value to the register.
*
* @param[in] snrmeassel - The value to use for the SNRMEASSEL field.
* @param[in] nfvgathrh2 - The value to use for the NFVGATHRH2 field.
* @param[in] nfvgathrh1 - The value to use for the NFVGATHRH1 field.
* @param[in] nfvgathrh0 - The value to use for the NFVGATHRH0 field.
*/
__INLINE void agc_rwnxagcsnr1_pack(uint8_t snrmeassel, uint8_t nfvgathrh2, uint8_t nfvgathrh1, uint8_t nfvgathrh0)
{
ASSERT_ERR((((uint32_t)snrmeassel << 24) & ~((uint32_t)0x01000000)) == 0);
ASSERT_ERR((((uint32_t)nfvgathrh2 << 8) & ~((uint32_t)0x00000F00)) == 0);
ASSERT_ERR((((uint32_t)nfvgathrh1 << 4) & ~((uint32_t)0x000000F0)) == 0);
ASSERT_ERR((((uint32_t)nfvgathrh0 << 0) & ~((uint32_t)0x0000000F)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR1_ADDR, ((uint32_t)snrmeassel << 24) | ((uint32_t)nfvgathrh2 << 8) | ((uint32_t)nfvgathrh1 << 4) | ((uint32_t)nfvgathrh0 << 0));
}
/**
* @brief Unpacks RWNXAGCSNR1's fields from current value of the RWNXAGCSNR1 register.
*
* Reads the RWNXAGCSNR1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] snrmeassel - Will be populated with the current value of this field from the register.
* @param[out] nfvgathrh2 - Will be populated with the current value of this field from the register.
* @param[out] nfvgathrh1 - Will be populated with the current value of this field from the register.
* @param[out] nfvgathrh0 - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcsnr1_unpack(uint8_t *snrmeassel, uint8_t *nfvgathrh2, uint8_t *nfvgathrh1, uint8_t *nfvgathrh0)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR1_ADDR);
*snrmeassel = (localVal & ((uint32_t)0x01000000)) >> 24;
*nfvgathrh2 = (localVal & ((uint32_t)0x00000F00)) >> 8;
*nfvgathrh1 = (localVal & ((uint32_t)0x000000F0)) >> 4;
*nfvgathrh0 = (localVal & ((uint32_t)0x0000000F)) >> 0;
}
/**
* @brief Returns the current value of the SNRMEASSEL field in the RWNXAGCSNR1 register.
*
* The RWNXAGCSNR1 register will be read and the SNRMEASSEL field's value will be returned.
*
* @return The current value of the SNRMEASSEL field in the RWNXAGCSNR1 register.
*/
__INLINE uint8_t agc_snrmeassel_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR1_ADDR);
return ((localVal & ((uint32_t)0x01000000)) >> 24);
}
/**
* @brief Sets the SNRMEASSEL field of the RWNXAGCSNR1 register.
*
* The RWNXAGCSNR1 register will be read, modified to contain the new field value, and written.
*
* @param[in] snrmeassel - The value to set the field to.
*/
__INLINE void agc_snrmeassel_setf(uint8_t snrmeassel)
{
ASSERT_ERR((((uint32_t)snrmeassel << 24) & ~((uint32_t)0x01000000)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR1_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR1_ADDR) & ~((uint32_t)0x01000000)) | ((uint32_t)snrmeassel << 24));
}
/**
* @brief Returns the current value of the NFVGATHRH2 field in the RWNXAGCSNR1 register.
*
* The RWNXAGCSNR1 register will be read and the NFVGATHRH2 field's value will be returned.
*
* @return The current value of the NFVGATHRH2 field in the RWNXAGCSNR1 register.
*/
__INLINE uint8_t agc_nfvgathrh2_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR1_ADDR);
return ((localVal & ((uint32_t)0x00000F00)) >> 8);
}
/**
* @brief Sets the NFVGATHRH2 field of the RWNXAGCSNR1 register.
*
* The RWNXAGCSNR1 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvgathrh2 - The value to set the field to.
*/
__INLINE void agc_nfvgathrh2_setf(uint8_t nfvgathrh2)
{
ASSERT_ERR((((uint32_t)nfvgathrh2 << 8) & ~((uint32_t)0x00000F00)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR1_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR1_ADDR) & ~((uint32_t)0x00000F00)) | ((uint32_t)nfvgathrh2 << 8));
}
/**
* @brief Returns the current value of the NFVGATHRH1 field in the RWNXAGCSNR1 register.
*
* The RWNXAGCSNR1 register will be read and the NFVGATHRH1 field's value will be returned.
*
* @return The current value of the NFVGATHRH1 field in the RWNXAGCSNR1 register.
*/
__INLINE uint8_t agc_nfvgathrh1_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR1_ADDR);
return ((localVal & ((uint32_t)0x000000F0)) >> 4);
}
/**
* @brief Sets the NFVGATHRH1 field of the RWNXAGCSNR1 register.
*
* The RWNXAGCSNR1 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvgathrh1 - The value to set the field to.
*/
__INLINE void agc_nfvgathrh1_setf(uint8_t nfvgathrh1)
{
ASSERT_ERR((((uint32_t)nfvgathrh1 << 4) & ~((uint32_t)0x000000F0)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR1_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR1_ADDR) & ~((uint32_t)0x000000F0)) | ((uint32_t)nfvgathrh1 << 4));
}
/**
* @brief Returns the current value of the NFVGATHRH0 field in the RWNXAGCSNR1 register.
*
* The RWNXAGCSNR1 register will be read and the NFVGATHRH0 field's value will be returned.
*
* @return The current value of the NFVGATHRH0 field in the RWNXAGCSNR1 register.
*/
__INLINE uint8_t agc_nfvgathrh0_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR1_ADDR);
return ((localVal & ((uint32_t)0x0000000F)) >> 0);
}
/**
* @brief Sets the NFVGATHRH0 field of the RWNXAGCSNR1 register.
*
* The RWNXAGCSNR1 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvgathrh0 - The value to set the field to.
*/
__INLINE void agc_nfvgathrh0_setf(uint8_t nfvgathrh0)
{
ASSERT_ERR((((uint32_t)nfvgathrh0 << 0) & ~((uint32_t)0x0000000F)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR1_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR1_ADDR) & ~((uint32_t)0x0000000F)) | ((uint32_t)nfvgathrh0 << 0));
}
/// @}
/**
* @name RWNXAGCSNR2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:24 NFVALL3DB 0x20
* 21:16 NFVALL2DB 0x21
* 13:08 NFVALL1DB 0x28
* 05:00 NFVALL0DB 0x28
* </pre>
*
* @{
*/
/// Address of the RWNXAGCSNR2 register
#define AGC_RWNXAGCSNR2_ADDR 0x01002090
/// Offset of the RWNXAGCSNR2 register from the base address
#define AGC_RWNXAGCSNR2_OFFSET 0x00002090
/// Index of the RWNXAGCSNR2 register
#define AGC_RWNXAGCSNR2_INDEX 0x00000824
/// Reset value of the RWNXAGCSNR2 register
#define AGC_RWNXAGCSNR2_RESET 0x20212828
/**
* @brief Returns the current value of the RWNXAGCSNR2 register.
* The RWNXAGCSNR2 register will be read and its value returned.
* @return The current value of the RWNXAGCSNR2 register.
*/
__INLINE uint32_t agc_rwnxagcsnr2_get(void)
{
return REG_PL_RD(AGC_RWNXAGCSNR2_ADDR);
}
/**
* @brief Sets the RWNXAGCSNR2 register to a value.
* The RWNXAGCSNR2 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcsnr2_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCSNR2_ADDR, value);
}
// field definitions
/// NFVALL3DB field mask
#define AGC_NFVALL3DB_MASK ((uint32_t)0x3F000000)
/// NFVALL3DB field LSB position
#define AGC_NFVALL3DB_LSB 24
/// NFVALL3DB field width
#define AGC_NFVALL3DB_WIDTH ((uint32_t)0x00000006)
/// NFVALL2DB field mask
#define AGC_NFVALL2DB_MASK ((uint32_t)0x003F0000)
/// NFVALL2DB field LSB position
#define AGC_NFVALL2DB_LSB 16
/// NFVALL2DB field width
#define AGC_NFVALL2DB_WIDTH ((uint32_t)0x00000006)
/// NFVALL1DB field mask
#define AGC_NFVALL1DB_MASK ((uint32_t)0x00003F00)
/// NFVALL1DB field LSB position
#define AGC_NFVALL1DB_LSB 8
/// NFVALL1DB field width
#define AGC_NFVALL1DB_WIDTH ((uint32_t)0x00000006)
/// NFVALL0DB field mask
#define AGC_NFVALL0DB_MASK ((uint32_t)0x0000003F)
/// NFVALL0DB field LSB position
#define AGC_NFVALL0DB_LSB 0
/// NFVALL0DB field width
#define AGC_NFVALL0DB_WIDTH ((uint32_t)0x00000006)
/// NFVALL3DB field reset value
#define AGC_NFVALL3DB_RST 0x20
/// NFVALL2DB field reset value
#define AGC_NFVALL2DB_RST 0x21
/// NFVALL1DB field reset value
#define AGC_NFVALL1DB_RST 0x28
/// NFVALL0DB field reset value
#define AGC_NFVALL0DB_RST 0x28
/**
* @brief Constructs a value for the RWNXAGCSNR2 register given values for its fields
* and writes the value to the register.
*
* @param[in] nfvall3db - The value to use for the NFVALL3DB field.
* @param[in] nfvall2db - The value to use for the NFVALL2DB field.
* @param[in] nfvall1db - The value to use for the NFVALL1DB field.
* @param[in] nfvall0db - The value to use for the NFVALL0DB field.
*/
__INLINE void agc_rwnxagcsnr2_pack(uint8_t nfvall3db, uint8_t nfvall2db, uint8_t nfvall1db, uint8_t nfvall0db)
{
ASSERT_ERR((((uint32_t)nfvall3db << 24) & ~((uint32_t)0x3F000000)) == 0);
ASSERT_ERR((((uint32_t)nfvall2db << 16) & ~((uint32_t)0x003F0000)) == 0);
ASSERT_ERR((((uint32_t)nfvall1db << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)nfvall0db << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR2_ADDR, ((uint32_t)nfvall3db << 24) | ((uint32_t)nfvall2db << 16) | ((uint32_t)nfvall1db << 8) | ((uint32_t)nfvall0db << 0));
}
/**
* @brief Unpacks RWNXAGCSNR2's fields from current value of the RWNXAGCSNR2 register.
*
* Reads the RWNXAGCSNR2 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] nfvall3db - Will be populated with the current value of this field from the register.
* @param[out] nfvall2db - Will be populated with the current value of this field from the register.
* @param[out] nfvall1db - Will be populated with the current value of this field from the register.
* @param[out] nfvall0db - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcsnr2_unpack(uint8_t *nfvall3db, uint8_t *nfvall2db, uint8_t *nfvall1db, uint8_t *nfvall0db)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR2_ADDR);
*nfvall3db = (localVal & ((uint32_t)0x3F000000)) >> 24;
*nfvall2db = (localVal & ((uint32_t)0x003F0000)) >> 16;
*nfvall1db = (localVal & ((uint32_t)0x00003F00)) >> 8;
*nfvall0db = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the NFVALL3DB field in the RWNXAGCSNR2 register.
*
* The RWNXAGCSNR2 register will be read and the NFVALL3DB field's value will be returned.
*
* @return The current value of the NFVALL3DB field in the RWNXAGCSNR2 register.
*/
__INLINE uint8_t agc_nfvall3db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR2_ADDR);
return ((localVal & ((uint32_t)0x3F000000)) >> 24);
}
/**
* @brief Sets the NFVALL3DB field of the RWNXAGCSNR2 register.
*
* The RWNXAGCSNR2 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvall3db - The value to set the field to.
*/
__INLINE void agc_nfvall3db_setf(uint8_t nfvall3db)
{
ASSERT_ERR((((uint32_t)nfvall3db << 24) & ~((uint32_t)0x3F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR2_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR2_ADDR) & ~((uint32_t)0x3F000000)) | ((uint32_t)nfvall3db << 24));
}
/**
* @brief Returns the current value of the NFVALL2DB field in the RWNXAGCSNR2 register.
*
* The RWNXAGCSNR2 register will be read and the NFVALL2DB field's value will be returned.
*
* @return The current value of the NFVALL2DB field in the RWNXAGCSNR2 register.
*/
__INLINE uint8_t agc_nfvall2db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR2_ADDR);
return ((localVal & ((uint32_t)0x003F0000)) >> 16);
}
/**
* @brief Sets the NFVALL2DB field of the RWNXAGCSNR2 register.
*
* The RWNXAGCSNR2 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvall2db - The value to set the field to.
*/
__INLINE void agc_nfvall2db_setf(uint8_t nfvall2db)
{
ASSERT_ERR((((uint32_t)nfvall2db << 16) & ~((uint32_t)0x003F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR2_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR2_ADDR) & ~((uint32_t)0x003F0000)) | ((uint32_t)nfvall2db << 16));
}
/**
* @brief Returns the current value of the NFVALL1DB field in the RWNXAGCSNR2 register.
*
* The RWNXAGCSNR2 register will be read and the NFVALL1DB field's value will be returned.
*
* @return The current value of the NFVALL1DB field in the RWNXAGCSNR2 register.
*/
__INLINE uint8_t agc_nfvall1db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR2_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the NFVALL1DB field of the RWNXAGCSNR2 register.
*
* The RWNXAGCSNR2 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvall1db - The value to set the field to.
*/
__INLINE void agc_nfvall1db_setf(uint8_t nfvall1db)
{
ASSERT_ERR((((uint32_t)nfvall1db << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR2_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR2_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)nfvall1db << 8));
}
/**
* @brief Returns the current value of the NFVALL0DB field in the RWNXAGCSNR2 register.
*
* The RWNXAGCSNR2 register will be read and the NFVALL0DB field's value will be returned.
*
* @return The current value of the NFVALL0DB field in the RWNXAGCSNR2 register.
*/
__INLINE uint8_t agc_nfvall0db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR2_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the NFVALL0DB field of the RWNXAGCSNR2 register.
*
* The RWNXAGCSNR2 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvall0db - The value to set the field to.
*/
__INLINE void agc_nfvall0db_setf(uint8_t nfvall0db)
{
ASSERT_ERR((((uint32_t)nfvall0db << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR2_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR2_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)nfvall0db << 0));
}
/// @}
/**
* @name RWNXAGCSNR3 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:24 NFVALM3DB 0x11
* 21:16 NFVALM2DB 0x12
* 13:08 NFVALM1DB 0x16
* 05:00 NFVALM0DB 0x17
* </pre>
*
* @{
*/
/// Address of the RWNXAGCSNR3 register
#define AGC_RWNXAGCSNR3_ADDR 0x01002094
/// Offset of the RWNXAGCSNR3 register from the base address
#define AGC_RWNXAGCSNR3_OFFSET 0x00002094
/// Index of the RWNXAGCSNR3 register
#define AGC_RWNXAGCSNR3_INDEX 0x00000825
/// Reset value of the RWNXAGCSNR3 register
#define AGC_RWNXAGCSNR3_RESET 0x11121617
/**
* @brief Returns the current value of the RWNXAGCSNR3 register.
* The RWNXAGCSNR3 register will be read and its value returned.
* @return The current value of the RWNXAGCSNR3 register.
*/
__INLINE uint32_t agc_rwnxagcsnr3_get(void)
{
return REG_PL_RD(AGC_RWNXAGCSNR3_ADDR);
}
/**
* @brief Sets the RWNXAGCSNR3 register to a value.
* The RWNXAGCSNR3 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcsnr3_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCSNR3_ADDR, value);
}
// field definitions
/// NFVALM3DB field mask
#define AGC_NFVALM3DB_MASK ((uint32_t)0x3F000000)
/// NFVALM3DB field LSB position
#define AGC_NFVALM3DB_LSB 24
/// NFVALM3DB field width
#define AGC_NFVALM3DB_WIDTH ((uint32_t)0x00000006)
/// NFVALM2DB field mask
#define AGC_NFVALM2DB_MASK ((uint32_t)0x003F0000)
/// NFVALM2DB field LSB position
#define AGC_NFVALM2DB_LSB 16
/// NFVALM2DB field width
#define AGC_NFVALM2DB_WIDTH ((uint32_t)0x00000006)
/// NFVALM1DB field mask
#define AGC_NFVALM1DB_MASK ((uint32_t)0x00003F00)
/// NFVALM1DB field LSB position
#define AGC_NFVALM1DB_LSB 8
/// NFVALM1DB field width
#define AGC_NFVALM1DB_WIDTH ((uint32_t)0x00000006)
/// NFVALM0DB field mask
#define AGC_NFVALM0DB_MASK ((uint32_t)0x0000003F)
/// NFVALM0DB field LSB position
#define AGC_NFVALM0DB_LSB 0
/// NFVALM0DB field width
#define AGC_NFVALM0DB_WIDTH ((uint32_t)0x00000006)
/// NFVALM3DB field reset value
#define AGC_NFVALM3DB_RST 0x11
/// NFVALM2DB field reset value
#define AGC_NFVALM2DB_RST 0x12
/// NFVALM1DB field reset value
#define AGC_NFVALM1DB_RST 0x16
/// NFVALM0DB field reset value
#define AGC_NFVALM0DB_RST 0x17
/**
* @brief Constructs a value for the RWNXAGCSNR3 register given values for its fields
* and writes the value to the register.
*
* @param[in] nfvalm3db - The value to use for the NFVALM3DB field.
* @param[in] nfvalm2db - The value to use for the NFVALM2DB field.
* @param[in] nfvalm1db - The value to use for the NFVALM1DB field.
* @param[in] nfvalm0db - The value to use for the NFVALM0DB field.
*/
__INLINE void agc_rwnxagcsnr3_pack(uint8_t nfvalm3db, uint8_t nfvalm2db, uint8_t nfvalm1db, uint8_t nfvalm0db)
{
ASSERT_ERR((((uint32_t)nfvalm3db << 24) & ~((uint32_t)0x3F000000)) == 0);
ASSERT_ERR((((uint32_t)nfvalm2db << 16) & ~((uint32_t)0x003F0000)) == 0);
ASSERT_ERR((((uint32_t)nfvalm1db << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)nfvalm0db << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR3_ADDR, ((uint32_t)nfvalm3db << 24) | ((uint32_t)nfvalm2db << 16) | ((uint32_t)nfvalm1db << 8) | ((uint32_t)nfvalm0db << 0));
}
/**
* @brief Unpacks RWNXAGCSNR3's fields from current value of the RWNXAGCSNR3 register.
*
* Reads the RWNXAGCSNR3 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] nfvalm3db - Will be populated with the current value of this field from the register.
* @param[out] nfvalm2db - Will be populated with the current value of this field from the register.
* @param[out] nfvalm1db - Will be populated with the current value of this field from the register.
* @param[out] nfvalm0db - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcsnr3_unpack(uint8_t *nfvalm3db, uint8_t *nfvalm2db, uint8_t *nfvalm1db, uint8_t *nfvalm0db)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR3_ADDR);
*nfvalm3db = (localVal & ((uint32_t)0x3F000000)) >> 24;
*nfvalm2db = (localVal & ((uint32_t)0x003F0000)) >> 16;
*nfvalm1db = (localVal & ((uint32_t)0x00003F00)) >> 8;
*nfvalm0db = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the NFVALM3DB field in the RWNXAGCSNR3 register.
*
* The RWNXAGCSNR3 register will be read and the NFVALM3DB field's value will be returned.
*
* @return The current value of the NFVALM3DB field in the RWNXAGCSNR3 register.
*/
__INLINE uint8_t agc_nfvalm3db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR3_ADDR);
return ((localVal & ((uint32_t)0x3F000000)) >> 24);
}
/**
* @brief Sets the NFVALM3DB field of the RWNXAGCSNR3 register.
*
* The RWNXAGCSNR3 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvalm3db - The value to set the field to.
*/
__INLINE void agc_nfvalm3db_setf(uint8_t nfvalm3db)
{
ASSERT_ERR((((uint32_t)nfvalm3db << 24) & ~((uint32_t)0x3F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR3_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR3_ADDR) & ~((uint32_t)0x3F000000)) | ((uint32_t)nfvalm3db << 24));
}
/**
* @brief Returns the current value of the NFVALM2DB field in the RWNXAGCSNR3 register.
*
* The RWNXAGCSNR3 register will be read and the NFVALM2DB field's value will be returned.
*
* @return The current value of the NFVALM2DB field in the RWNXAGCSNR3 register.
*/
__INLINE uint8_t agc_nfvalm2db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR3_ADDR);
return ((localVal & ((uint32_t)0x003F0000)) >> 16);
}
/**
* @brief Sets the NFVALM2DB field of the RWNXAGCSNR3 register.
*
* The RWNXAGCSNR3 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvalm2db - The value to set the field to.
*/
__INLINE void agc_nfvalm2db_setf(uint8_t nfvalm2db)
{
ASSERT_ERR((((uint32_t)nfvalm2db << 16) & ~((uint32_t)0x003F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR3_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR3_ADDR) & ~((uint32_t)0x003F0000)) | ((uint32_t)nfvalm2db << 16));
}
/**
* @brief Returns the current value of the NFVALM1DB field in the RWNXAGCSNR3 register.
*
* The RWNXAGCSNR3 register will be read and the NFVALM1DB field's value will be returned.
*
* @return The current value of the NFVALM1DB field in the RWNXAGCSNR3 register.
*/
__INLINE uint8_t agc_nfvalm1db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR3_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the NFVALM1DB field of the RWNXAGCSNR3 register.
*
* The RWNXAGCSNR3 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvalm1db - The value to set the field to.
*/
__INLINE void agc_nfvalm1db_setf(uint8_t nfvalm1db)
{
ASSERT_ERR((((uint32_t)nfvalm1db << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR3_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR3_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)nfvalm1db << 8));
}
/**
* @brief Returns the current value of the NFVALM0DB field in the RWNXAGCSNR3 register.
*
* The RWNXAGCSNR3 register will be read and the NFVALM0DB field's value will be returned.
*
* @return The current value of the NFVALM0DB field in the RWNXAGCSNR3 register.
*/
__INLINE uint8_t agc_nfvalm0db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR3_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the NFVALM0DB field of the RWNXAGCSNR3 register.
*
* The RWNXAGCSNR3 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvalm0db - The value to set the field to.
*/
__INLINE void agc_nfvalm0db_setf(uint8_t nfvalm0db)
{
ASSERT_ERR((((uint32_t)nfvalm0db << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR3_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR3_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)nfvalm0db << 0));
}
/// @}
/**
* @name RWNXAGCSNR4 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:24 NFVALH3DB 0x4
* 21:16 NFVALH2DB 0x6
* 13:08 NFVALH1DB 0x7
* 05:00 NFVALH0DB 0x8
* </pre>
*
* @{
*/
/// Address of the RWNXAGCSNR4 register
#define AGC_RWNXAGCSNR4_ADDR 0x01002098
/// Offset of the RWNXAGCSNR4 register from the base address
#define AGC_RWNXAGCSNR4_OFFSET 0x00002098
/// Index of the RWNXAGCSNR4 register
#define AGC_RWNXAGCSNR4_INDEX 0x00000826
/// Reset value of the RWNXAGCSNR4 register
#define AGC_RWNXAGCSNR4_RESET 0x04060708
/**
* @brief Returns the current value of the RWNXAGCSNR4 register.
* The RWNXAGCSNR4 register will be read and its value returned.
* @return The current value of the RWNXAGCSNR4 register.
*/
__INLINE uint32_t agc_rwnxagcsnr4_get(void)
{
return REG_PL_RD(AGC_RWNXAGCSNR4_ADDR);
}
/**
* @brief Sets the RWNXAGCSNR4 register to a value.
* The RWNXAGCSNR4 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcsnr4_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCSNR4_ADDR, value);
}
// field definitions
/// NFVALH3DB field mask
#define AGC_NFVALH3DB_MASK ((uint32_t)0x3F000000)
/// NFVALH3DB field LSB position
#define AGC_NFVALH3DB_LSB 24
/// NFVALH3DB field width
#define AGC_NFVALH3DB_WIDTH ((uint32_t)0x00000006)
/// NFVALH2DB field mask
#define AGC_NFVALH2DB_MASK ((uint32_t)0x003F0000)
/// NFVALH2DB field LSB position
#define AGC_NFVALH2DB_LSB 16
/// NFVALH2DB field width
#define AGC_NFVALH2DB_WIDTH ((uint32_t)0x00000006)
/// NFVALH1DB field mask
#define AGC_NFVALH1DB_MASK ((uint32_t)0x00003F00)
/// NFVALH1DB field LSB position
#define AGC_NFVALH1DB_LSB 8
/// NFVALH1DB field width
#define AGC_NFVALH1DB_WIDTH ((uint32_t)0x00000006)
/// NFVALH0DB field mask
#define AGC_NFVALH0DB_MASK ((uint32_t)0x0000003F)
/// NFVALH0DB field LSB position
#define AGC_NFVALH0DB_LSB 0
/// NFVALH0DB field width
#define AGC_NFVALH0DB_WIDTH ((uint32_t)0x00000006)
/// NFVALH3DB field reset value
#define AGC_NFVALH3DB_RST 0x4
/// NFVALH2DB field reset value
#define AGC_NFVALH2DB_RST 0x6
/// NFVALH1DB field reset value
#define AGC_NFVALH1DB_RST 0x7
/// NFVALH0DB field reset value
#define AGC_NFVALH0DB_RST 0x8
/**
* @brief Constructs a value for the RWNXAGCSNR4 register given values for its fields
* and writes the value to the register.
*
* @param[in] nfvalh3db - The value to use for the NFVALH3DB field.
* @param[in] nfvalh2db - The value to use for the NFVALH2DB field.
* @param[in] nfvalh1db - The value to use for the NFVALH1DB field.
* @param[in] nfvalh0db - The value to use for the NFVALH0DB field.
*/
__INLINE void agc_rwnxagcsnr4_pack(uint8_t nfvalh3db, uint8_t nfvalh2db, uint8_t nfvalh1db, uint8_t nfvalh0db)
{
ASSERT_ERR((((uint32_t)nfvalh3db << 24) & ~((uint32_t)0x3F000000)) == 0);
ASSERT_ERR((((uint32_t)nfvalh2db << 16) & ~((uint32_t)0x003F0000)) == 0);
ASSERT_ERR((((uint32_t)nfvalh1db << 8) & ~((uint32_t)0x00003F00)) == 0);
ASSERT_ERR((((uint32_t)nfvalh0db << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR4_ADDR, ((uint32_t)nfvalh3db << 24) | ((uint32_t)nfvalh2db << 16) | ((uint32_t)nfvalh1db << 8) | ((uint32_t)nfvalh0db << 0));
}
/**
* @brief Unpacks RWNXAGCSNR4's fields from current value of the RWNXAGCSNR4 register.
*
* Reads the RWNXAGCSNR4 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] nfvalh3db - Will be populated with the current value of this field from the register.
* @param[out] nfvalh2db - Will be populated with the current value of this field from the register.
* @param[out] nfvalh1db - Will be populated with the current value of this field from the register.
* @param[out] nfvalh0db - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcsnr4_unpack(uint8_t *nfvalh3db, uint8_t *nfvalh2db, uint8_t *nfvalh1db, uint8_t *nfvalh0db)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR4_ADDR);
*nfvalh3db = (localVal & ((uint32_t)0x3F000000)) >> 24;
*nfvalh2db = (localVal & ((uint32_t)0x003F0000)) >> 16;
*nfvalh1db = (localVal & ((uint32_t)0x00003F00)) >> 8;
*nfvalh0db = (localVal & ((uint32_t)0x0000003F)) >> 0;
}
/**
* @brief Returns the current value of the NFVALH3DB field in the RWNXAGCSNR4 register.
*
* The RWNXAGCSNR4 register will be read and the NFVALH3DB field's value will be returned.
*
* @return The current value of the NFVALH3DB field in the RWNXAGCSNR4 register.
*/
__INLINE uint8_t agc_nfvalh3db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR4_ADDR);
return ((localVal & ((uint32_t)0x3F000000)) >> 24);
}
/**
* @brief Sets the NFVALH3DB field of the RWNXAGCSNR4 register.
*
* The RWNXAGCSNR4 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvalh3db - The value to set the field to.
*/
__INLINE void agc_nfvalh3db_setf(uint8_t nfvalh3db)
{
ASSERT_ERR((((uint32_t)nfvalh3db << 24) & ~((uint32_t)0x3F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR4_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR4_ADDR) & ~((uint32_t)0x3F000000)) | ((uint32_t)nfvalh3db << 24));
}
/**
* @brief Returns the current value of the NFVALH2DB field in the RWNXAGCSNR4 register.
*
* The RWNXAGCSNR4 register will be read and the NFVALH2DB field's value will be returned.
*
* @return The current value of the NFVALH2DB field in the RWNXAGCSNR4 register.
*/
__INLINE uint8_t agc_nfvalh2db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR4_ADDR);
return ((localVal & ((uint32_t)0x003F0000)) >> 16);
}
/**
* @brief Sets the NFVALH2DB field of the RWNXAGCSNR4 register.
*
* The RWNXAGCSNR4 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvalh2db - The value to set the field to.
*/
__INLINE void agc_nfvalh2db_setf(uint8_t nfvalh2db)
{
ASSERT_ERR((((uint32_t)nfvalh2db << 16) & ~((uint32_t)0x003F0000)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR4_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR4_ADDR) & ~((uint32_t)0x003F0000)) | ((uint32_t)nfvalh2db << 16));
}
/**
* @brief Returns the current value of the NFVALH1DB field in the RWNXAGCSNR4 register.
*
* The RWNXAGCSNR4 register will be read and the NFVALH1DB field's value will be returned.
*
* @return The current value of the NFVALH1DB field in the RWNXAGCSNR4 register.
*/
__INLINE uint8_t agc_nfvalh1db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR4_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Sets the NFVALH1DB field of the RWNXAGCSNR4 register.
*
* The RWNXAGCSNR4 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvalh1db - The value to set the field to.
*/
__INLINE void agc_nfvalh1db_setf(uint8_t nfvalh1db)
{
ASSERT_ERR((((uint32_t)nfvalh1db << 8) & ~((uint32_t)0x00003F00)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR4_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR4_ADDR) & ~((uint32_t)0x00003F00)) | ((uint32_t)nfvalh1db << 8));
}
/**
* @brief Returns the current value of the NFVALH0DB field in the RWNXAGCSNR4 register.
*
* The RWNXAGCSNR4 register will be read and the NFVALH0DB field's value will be returned.
*
* @return The current value of the NFVALH0DB field in the RWNXAGCSNR4 register.
*/
__INLINE uint8_t agc_nfvalh0db_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCSNR4_ADDR);
return ((localVal & ((uint32_t)0x0000003F)) >> 0);
}
/**
* @brief Sets the NFVALH0DB field of the RWNXAGCSNR4 register.
*
* The RWNXAGCSNR4 register will be read, modified to contain the new field value, and written.
*
* @param[in] nfvalh0db - The value to set the field to.
*/
__INLINE void agc_nfvalh0db_setf(uint8_t nfvalh0db)
{
ASSERT_ERR((((uint32_t)nfvalh0db << 0) & ~((uint32_t)0x0000003F)) == 0);
REG_PL_WR(AGC_RWNXAGCSNR4_ADDR, (REG_PL_RD(AGC_RWNXAGCSNR4_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)nfvalh0db << 0));
}
/// @}
/**
* @name RWNXAGCCOMP register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:24 IDPOWGAPDNQDBM 0x28
* 23:16 IDPOWGAPUPQDBM 0x28
* 15:08 POWINFTHRDBM 0xBA
* 07:00 POWSUPTHRDBM 0xBA
* </pre>
*
* @{
*/
/// Address of the RWNXAGCCOMP register
#define AGC_RWNXAGCCOMP_ADDR 0x0100209C
/// Offset of the RWNXAGCCOMP register from the base address
#define AGC_RWNXAGCCOMP_OFFSET 0x0000209C
/// Index of the RWNXAGCCOMP register
#define AGC_RWNXAGCCOMP_INDEX 0x00000827
/// Reset value of the RWNXAGCCOMP register
#define AGC_RWNXAGCCOMP_RESET 0x2828BABA
/**
* @brief Returns the current value of the RWNXAGCCOMP register.
* The RWNXAGCCOMP register will be read and its value returned.
* @return The current value of the RWNXAGCCOMP register.
*/
__INLINE uint32_t agc_rwnxagccomp_get(void)
{
return REG_PL_RD(AGC_RWNXAGCCOMP_ADDR);
}
/**
* @brief Sets the RWNXAGCCOMP register to a value.
* The RWNXAGCCOMP register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagccomp_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCCOMP_ADDR, value);
}
// field definitions
/// IDPOWGAPDNQDBM field mask
#define AGC_IDPOWGAPDNQDBM_MASK ((uint32_t)0xFF000000)
/// IDPOWGAPDNQDBM field LSB position
#define AGC_IDPOWGAPDNQDBM_LSB 24
/// IDPOWGAPDNQDBM field width
#define AGC_IDPOWGAPDNQDBM_WIDTH ((uint32_t)0x00000008)
/// IDPOWGAPUPQDBM field mask
#define AGC_IDPOWGAPUPQDBM_MASK ((uint32_t)0x00FF0000)
/// IDPOWGAPUPQDBM field LSB position
#define AGC_IDPOWGAPUPQDBM_LSB 16
/// IDPOWGAPUPQDBM field width
#define AGC_IDPOWGAPUPQDBM_WIDTH ((uint32_t)0x00000008)
/// POWINFTHRDBM field mask
#define AGC_POWINFTHRDBM_MASK ((uint32_t)0x0000FF00)
/// POWINFTHRDBM field LSB position
#define AGC_POWINFTHRDBM_LSB 8
/// POWINFTHRDBM field width
#define AGC_POWINFTHRDBM_WIDTH ((uint32_t)0x00000008)
/// POWSUPTHRDBM field mask
#define AGC_POWSUPTHRDBM_MASK ((uint32_t)0x000000FF)
/// POWSUPTHRDBM field LSB position
#define AGC_POWSUPTHRDBM_LSB 0
/// POWSUPTHRDBM field width
#define AGC_POWSUPTHRDBM_WIDTH ((uint32_t)0x00000008)
/// IDPOWGAPDNQDBM field reset value
#define AGC_IDPOWGAPDNQDBM_RST 0x28
/// IDPOWGAPUPQDBM field reset value
#define AGC_IDPOWGAPUPQDBM_RST 0x28
/// POWINFTHRDBM field reset value
#define AGC_POWINFTHRDBM_RST 0xBA
/// POWSUPTHRDBM field reset value
#define AGC_POWSUPTHRDBM_RST 0xBA
/**
* @brief Constructs a value for the RWNXAGCCOMP register given values for its fields
* and writes the value to the register.
*
* @param[in] idpowgapdnqdbm - The value to use for the IDPOWGAPDNQDBM field.
* @param[in] idpowgapupqdbm - The value to use for the IDPOWGAPUPQDBM field.
* @param[in] powinfthrdbm - The value to use for the POWINFTHRDBM field.
* @param[in] powsupthrdbm - The value to use for the POWSUPTHRDBM field.
*/
__INLINE void agc_rwnxagccomp_pack(uint8_t idpowgapdnqdbm, uint8_t idpowgapupqdbm, uint8_t powinfthrdbm, uint8_t powsupthrdbm)
{
ASSERT_ERR((((uint32_t)idpowgapdnqdbm << 24) & ~((uint32_t)0xFF000000)) == 0);
ASSERT_ERR((((uint32_t)idpowgapupqdbm << 16) & ~((uint32_t)0x00FF0000)) == 0);
ASSERT_ERR((((uint32_t)powinfthrdbm << 8) & ~((uint32_t)0x0000FF00)) == 0);
ASSERT_ERR((((uint32_t)powsupthrdbm << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCCOMP_ADDR, ((uint32_t)idpowgapdnqdbm << 24) | ((uint32_t)idpowgapupqdbm << 16) | ((uint32_t)powinfthrdbm << 8) | ((uint32_t)powsupthrdbm << 0));
}
/**
* @brief Unpacks RWNXAGCCOMP's fields from current value of the RWNXAGCCOMP register.
*
* Reads the RWNXAGCCOMP register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] idpowgapdnqdbm - Will be populated with the current value of this field from the register.
* @param[out] idpowgapupqdbm - Will be populated with the current value of this field from the register.
* @param[out] powinfthrdbm - Will be populated with the current value of this field from the register.
* @param[out] powsupthrdbm - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagccomp_unpack(uint8_t *idpowgapdnqdbm, uint8_t *idpowgapupqdbm, uint8_t *powinfthrdbm, uint8_t *powsupthrdbm)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCOMP_ADDR);
*idpowgapdnqdbm = (localVal & ((uint32_t)0xFF000000)) >> 24;
*idpowgapupqdbm = (localVal & ((uint32_t)0x00FF0000)) >> 16;
*powinfthrdbm = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*powsupthrdbm = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the IDPOWGAPDNQDBM field in the RWNXAGCCOMP register.
*
* The RWNXAGCCOMP register will be read and the IDPOWGAPDNQDBM field's value will be returned.
*
* @return The current value of the IDPOWGAPDNQDBM field in the RWNXAGCCOMP register.
*/
__INLINE uint8_t agc_idpowgapdnqdbm_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCOMP_ADDR);
return ((localVal & ((uint32_t)0xFF000000)) >> 24);
}
/**
* @brief Sets the IDPOWGAPDNQDBM field of the RWNXAGCCOMP register.
*
* The RWNXAGCCOMP register will be read, modified to contain the new field value, and written.
*
* @param[in] idpowgapdnqdbm - The value to set the field to.
*/
__INLINE void agc_idpowgapdnqdbm_setf(uint8_t idpowgapdnqdbm)
{
ASSERT_ERR((((uint32_t)idpowgapdnqdbm << 24) & ~((uint32_t)0xFF000000)) == 0);
REG_PL_WR(AGC_RWNXAGCCOMP_ADDR, (REG_PL_RD(AGC_RWNXAGCCOMP_ADDR) & ~((uint32_t)0xFF000000)) | ((uint32_t)idpowgapdnqdbm << 24));
}
/**
* @brief Returns the current value of the IDPOWGAPUPQDBM field in the RWNXAGCCOMP register.
*
* The RWNXAGCCOMP register will be read and the IDPOWGAPUPQDBM field's value will be returned.
*
* @return The current value of the IDPOWGAPUPQDBM field in the RWNXAGCCOMP register.
*/
__INLINE uint8_t agc_idpowgapupqdbm_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCOMP_ADDR);
return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
}
/**
* @brief Sets the IDPOWGAPUPQDBM field of the RWNXAGCCOMP register.
*
* The RWNXAGCCOMP register will be read, modified to contain the new field value, and written.
*
* @param[in] idpowgapupqdbm - The value to set the field to.
*/
__INLINE void agc_idpowgapupqdbm_setf(uint8_t idpowgapupqdbm)
{
ASSERT_ERR((((uint32_t)idpowgapupqdbm << 16) & ~((uint32_t)0x00FF0000)) == 0);
REG_PL_WR(AGC_RWNXAGCCOMP_ADDR, (REG_PL_RD(AGC_RWNXAGCCOMP_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)idpowgapupqdbm << 16));
}
/**
* @brief Returns the current value of the POWINFTHRDBM field in the RWNXAGCCOMP register.
*
* The RWNXAGCCOMP register will be read and the POWINFTHRDBM field's value will be returned.
*
* @return The current value of the POWINFTHRDBM field in the RWNXAGCCOMP register.
*/
__INLINE uint8_t agc_powinfthrdbm_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCOMP_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Sets the POWINFTHRDBM field of the RWNXAGCCOMP register.
*
* The RWNXAGCCOMP register will be read, modified to contain the new field value, and written.
*
* @param[in] powinfthrdbm - The value to set the field to.
*/
__INLINE void agc_powinfthrdbm_setf(uint8_t powinfthrdbm)
{
ASSERT_ERR((((uint32_t)powinfthrdbm << 8) & ~((uint32_t)0x0000FF00)) == 0);
REG_PL_WR(AGC_RWNXAGCCOMP_ADDR, (REG_PL_RD(AGC_RWNXAGCCOMP_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)powinfthrdbm << 8));
}
/**
* @brief Returns the current value of the POWSUPTHRDBM field in the RWNXAGCCOMP register.
*
* The RWNXAGCCOMP register will be read and the POWSUPTHRDBM field's value will be returned.
*
* @return The current value of the POWSUPTHRDBM field in the RWNXAGCCOMP register.
*/
__INLINE uint8_t agc_powsupthrdbm_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCCOMP_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the POWSUPTHRDBM field of the RWNXAGCCOMP register.
*
* The RWNXAGCCOMP register will be read, modified to contain the new field value, and written.
*
* @param[in] powsupthrdbm - The value to set the field to.
*/
__INLINE void agc_powsupthrdbm_setf(uint8_t powsupthrdbm)
{
ASSERT_ERR((((uint32_t)powsupthrdbm << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCCOMP_ADDR, (REG_PL_RD(AGC_RWNXAGCCOMP_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)powsupthrdbm << 0));
}
/// @}
/**
* @name RWNXAGCRADAR register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 27:24 FREQSINGGAP 0x0
* 23:16 FREQSING 0x0
* 11:08 FOMSINGGAP 0x0
* 07:00 FOMSING 0x0
* </pre>
*
* @{
*/
/// Address of the RWNXAGCRADAR register
#define AGC_RWNXAGCRADAR_ADDR 0x010020A0
/// Offset of the RWNXAGCRADAR register from the base address
#define AGC_RWNXAGCRADAR_OFFSET 0x000020A0
/// Index of the RWNXAGCRADAR register
#define AGC_RWNXAGCRADAR_INDEX 0x00000828
/// Reset value of the RWNXAGCRADAR register
#define AGC_RWNXAGCRADAR_RESET 0x00000000
/**
* @brief Returns the current value of the RWNXAGCRADAR register.
* The RWNXAGCRADAR register will be read and its value returned.
* @return The current value of the RWNXAGCRADAR register.
*/
__INLINE uint32_t agc_rwnxagcradar_get(void)
{
return REG_PL_RD(AGC_RWNXAGCRADAR_ADDR);
}
/**
* @brief Sets the RWNXAGCRADAR register to a value.
* The RWNXAGCRADAR register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcradar_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCRADAR_ADDR, value);
}
// field definitions
/// FREQSINGGAP field mask
#define AGC_FREQSINGGAP_MASK ((uint32_t)0x0F000000)
/// FREQSINGGAP field LSB position
#define AGC_FREQSINGGAP_LSB 24
/// FREQSINGGAP field width
#define AGC_FREQSINGGAP_WIDTH ((uint32_t)0x00000004)
/// FREQSING field mask
#define AGC_FREQSING_MASK ((uint32_t)0x00FF0000)
/// FREQSING field LSB position
#define AGC_FREQSING_LSB 16
/// FREQSING field width
#define AGC_FREQSING_WIDTH ((uint32_t)0x00000008)
/// FOMSINGGAP field mask
#define AGC_FOMSINGGAP_MASK ((uint32_t)0x00000F00)
/// FOMSINGGAP field LSB position
#define AGC_FOMSINGGAP_LSB 8
/// FOMSINGGAP field width
#define AGC_FOMSINGGAP_WIDTH ((uint32_t)0x00000004)
/// FOMSING field mask
#define AGC_FOMSING_MASK ((uint32_t)0x000000FF)
/// FOMSING field LSB position
#define AGC_FOMSING_LSB 0
/// FOMSING field width
#define AGC_FOMSING_WIDTH ((uint32_t)0x00000008)
/// FREQSINGGAP field reset value
#define AGC_FREQSINGGAP_RST 0x0
/// FREQSING field reset value
#define AGC_FREQSING_RST 0x0
/// FOMSINGGAP field reset value
#define AGC_FOMSINGGAP_RST 0x0
/// FOMSING field reset value
#define AGC_FOMSING_RST 0x0
/**
* @brief Constructs a value for the RWNXAGCRADAR register given values for its fields
* and writes the value to the register.
*
* @param[in] freqsinggap - The value to use for the FREQSINGGAP field.
* @param[in] freqsing - The value to use for the FREQSING field.
* @param[in] fomsinggap - The value to use for the FOMSINGGAP field.
* @param[in] fomsing - The value to use for the FOMSING field.
*/
__INLINE void agc_rwnxagcradar_pack(uint8_t freqsinggap, uint8_t freqsing, uint8_t fomsinggap, uint8_t fomsing)
{
ASSERT_ERR((((uint32_t)freqsinggap << 24) & ~((uint32_t)0x0F000000)) == 0);
ASSERT_ERR((((uint32_t)freqsing << 16) & ~((uint32_t)0x00FF0000)) == 0);
ASSERT_ERR((((uint32_t)fomsinggap << 8) & ~((uint32_t)0x00000F00)) == 0);
ASSERT_ERR((((uint32_t)fomsing << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCRADAR_ADDR, ((uint32_t)freqsinggap << 24) | ((uint32_t)freqsing << 16) | ((uint32_t)fomsinggap << 8) | ((uint32_t)fomsing << 0));
}
/**
* @brief Unpacks RWNXAGCRADAR's fields from current value of the RWNXAGCRADAR register.
*
* Reads the RWNXAGCRADAR register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] freqsinggap - Will be populated with the current value of this field from the register.
* @param[out] freqsing - Will be populated with the current value of this field from the register.
* @param[out] fomsinggap - Will be populated with the current value of this field from the register.
* @param[out] fomsing - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcradar_unpack(uint8_t *freqsinggap, uint8_t *freqsing, uint8_t *fomsinggap, uint8_t *fomsing)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRADAR_ADDR);
*freqsinggap = (localVal & ((uint32_t)0x0F000000)) >> 24;
*freqsing = (localVal & ((uint32_t)0x00FF0000)) >> 16;
*fomsinggap = (localVal & ((uint32_t)0x00000F00)) >> 8;
*fomsing = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the FREQSINGGAP field in the RWNXAGCRADAR register.
*
* The RWNXAGCRADAR register will be read and the FREQSINGGAP field's value will be returned.
*
* @return The current value of the FREQSINGGAP field in the RWNXAGCRADAR register.
*/
__INLINE uint8_t agc_freqsinggap_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRADAR_ADDR);
return ((localVal & ((uint32_t)0x0F000000)) >> 24);
}
/**
* @brief Sets the FREQSINGGAP field of the RWNXAGCRADAR register.
*
* The RWNXAGCRADAR register will be read, modified to contain the new field value, and written.
*
* @param[in] freqsinggap - The value to set the field to.
*/
__INLINE void agc_freqsinggap_setf(uint8_t freqsinggap)
{
ASSERT_ERR((((uint32_t)freqsinggap << 24) & ~((uint32_t)0x0F000000)) == 0);
REG_PL_WR(AGC_RWNXAGCRADAR_ADDR, (REG_PL_RD(AGC_RWNXAGCRADAR_ADDR) & ~((uint32_t)0x0F000000)) | ((uint32_t)freqsinggap << 24));
}
/**
* @brief Returns the current value of the FREQSING field in the RWNXAGCRADAR register.
*
* The RWNXAGCRADAR register will be read and the FREQSING field's value will be returned.
*
* @return The current value of the FREQSING field in the RWNXAGCRADAR register.
*/
__INLINE uint8_t agc_freqsing_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRADAR_ADDR);
return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
}
/**
* @brief Sets the FREQSING field of the RWNXAGCRADAR register.
*
* The RWNXAGCRADAR register will be read, modified to contain the new field value, and written.
*
* @param[in] freqsing - The value to set the field to.
*/
__INLINE void agc_freqsing_setf(uint8_t freqsing)
{
ASSERT_ERR((((uint32_t)freqsing << 16) & ~((uint32_t)0x00FF0000)) == 0);
REG_PL_WR(AGC_RWNXAGCRADAR_ADDR, (REG_PL_RD(AGC_RWNXAGCRADAR_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)freqsing << 16));
}
/**
* @brief Returns the current value of the FOMSINGGAP field in the RWNXAGCRADAR register.
*
* The RWNXAGCRADAR register will be read and the FOMSINGGAP field's value will be returned.
*
* @return The current value of the FOMSINGGAP field in the RWNXAGCRADAR register.
*/
__INLINE uint8_t agc_fomsinggap_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRADAR_ADDR);
return ((localVal & ((uint32_t)0x00000F00)) >> 8);
}
/**
* @brief Sets the FOMSINGGAP field of the RWNXAGCRADAR register.
*
* The RWNXAGCRADAR register will be read, modified to contain the new field value, and written.
*
* @param[in] fomsinggap - The value to set the field to.
*/
__INLINE void agc_fomsinggap_setf(uint8_t fomsinggap)
{
ASSERT_ERR((((uint32_t)fomsinggap << 8) & ~((uint32_t)0x00000F00)) == 0);
REG_PL_WR(AGC_RWNXAGCRADAR_ADDR, (REG_PL_RD(AGC_RWNXAGCRADAR_ADDR) & ~((uint32_t)0x00000F00)) | ((uint32_t)fomsinggap << 8));
}
/**
* @brief Returns the current value of the FOMSING field in the RWNXAGCRADAR register.
*
* The RWNXAGCRADAR register will be read and the FOMSING field's value will be returned.
*
* @return The current value of the FOMSING field in the RWNXAGCRADAR register.
*/
__INLINE uint8_t agc_fomsing_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRADAR_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the FOMSING field of the RWNXAGCRADAR register.
*
* The RWNXAGCRADAR register will be read, modified to contain the new field value, and written.
*
* @param[in] fomsing - The value to set the field to.
*/
__INLINE void agc_fomsing_setf(uint8_t fomsing)
{
ASSERT_ERR((((uint32_t)fomsing << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCRADAR_ADDR, (REG_PL_RD(AGC_RWNXAGCRADAR_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)fomsing << 0));
}
/// @}
/**
* @name RWNXAGCRADARTIM register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31 PULSETIMERCLEAR 0
* 18:16 PULSEIRQFIFOTHR 0x3
* 07:00 PULSEIRQTIMEOUT 0x8
* </pre>
*
* @{
*/
/// Address of the RWNXAGCRADARTIM register
#define AGC_RWNXAGCRADARTIM_ADDR 0x010020A4
/// Offset of the RWNXAGCRADARTIM register from the base address
#define AGC_RWNXAGCRADARTIM_OFFSET 0x000020A4
/// Index of the RWNXAGCRADARTIM register
#define AGC_RWNXAGCRADARTIM_INDEX 0x00000829
/// Reset value of the RWNXAGCRADARTIM register
#define AGC_RWNXAGCRADARTIM_RESET 0x00030008
/**
* @brief Returns the current value of the RWNXAGCRADARTIM register.
* The RWNXAGCRADARTIM register will be read and its value returned.
* @return The current value of the RWNXAGCRADARTIM register.
*/
__INLINE uint32_t agc_rwnxagcradartim_get(void)
{
return REG_PL_RD(AGC_RWNXAGCRADARTIM_ADDR);
}
/**
* @brief Sets the RWNXAGCRADARTIM register to a value.
* The RWNXAGCRADARTIM register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcradartim_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCRADARTIM_ADDR, value);
}
// field definitions
/// PULSETIMERCLEAR field bit
#define AGC_PULSETIMERCLEAR_BIT ((uint32_t)0x80000000)
/// PULSETIMERCLEAR field position
#define AGC_PULSETIMERCLEAR_POS 31
/// PULSEIRQFIFOTHR field mask
#define AGC_PULSEIRQFIFOTHR_MASK ((uint32_t)0x00070000)
/// PULSEIRQFIFOTHR field LSB position
#define AGC_PULSEIRQFIFOTHR_LSB 16
/// PULSEIRQFIFOTHR field width
#define AGC_PULSEIRQFIFOTHR_WIDTH ((uint32_t)0x00000003)
/// PULSEIRQTIMEOUT field mask
#define AGC_PULSEIRQTIMEOUT_MASK ((uint32_t)0x000000FF)
/// PULSEIRQTIMEOUT field LSB position
#define AGC_PULSEIRQTIMEOUT_LSB 0
/// PULSEIRQTIMEOUT field width
#define AGC_PULSEIRQTIMEOUT_WIDTH ((uint32_t)0x00000008)
/// PULSETIMERCLEAR field reset value
#define AGC_PULSETIMERCLEAR_RST 0x0
/// PULSEIRQFIFOTHR field reset value
#define AGC_PULSEIRQFIFOTHR_RST 0x3
/// PULSEIRQTIMEOUT field reset value
#define AGC_PULSEIRQTIMEOUT_RST 0x8
/**
* @brief Constructs a value for the RWNXAGCRADARTIM register given values for its fields
* and writes the value to the register.
*
* @param[in] pulsetimerclear - The value to use for the PULSETIMERCLEAR field.
* @param[in] pulseirqfifothr - The value to use for the PULSEIRQFIFOTHR field.
* @param[in] pulseirqtimeout - The value to use for the PULSEIRQTIMEOUT field.
*/
__INLINE void agc_rwnxagcradartim_pack(uint8_t pulsetimerclear, uint8_t pulseirqfifothr, uint8_t pulseirqtimeout)
{
ASSERT_ERR((((uint32_t)pulsetimerclear << 31) & ~((uint32_t)0x80000000)) == 0);
ASSERT_ERR((((uint32_t)pulseirqfifothr << 16) & ~((uint32_t)0x00070000)) == 0);
ASSERT_ERR((((uint32_t)pulseirqtimeout << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCRADARTIM_ADDR, ((uint32_t)pulsetimerclear << 31) | ((uint32_t)pulseirqfifothr << 16) | ((uint32_t)pulseirqtimeout << 0));
}
/**
* @brief Unpacks RWNXAGCRADARTIM's fields from current value of the RWNXAGCRADARTIM register.
*
* Reads the RWNXAGCRADARTIM register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] pulsetimerclear - Will be populated with the current value of this field from the register.
* @param[out] pulseirqfifothr - Will be populated with the current value of this field from the register.
* @param[out] pulseirqtimeout - Will be populated with the current value of this field from the register.
*/
__INLINE void agc_rwnxagcradartim_unpack(uint8_t *pulsetimerclear, uint8_t *pulseirqfifothr, uint8_t *pulseirqtimeout)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRADARTIM_ADDR);
*pulsetimerclear = (localVal & ((uint32_t)0x80000000)) >> 31;
*pulseirqfifothr = (localVal & ((uint32_t)0x00070000)) >> 16;
*pulseirqtimeout = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the PULSETIMERCLEAR field in the RWNXAGCRADARTIM register.
*
* The RWNXAGCRADARTIM register will be read and the PULSETIMERCLEAR field's value will be returned.
*
* @return The current value of the PULSETIMERCLEAR field in the RWNXAGCRADARTIM register.
*/
__INLINE uint8_t agc_pulsetimerclear_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRADARTIM_ADDR);
return ((localVal & ((uint32_t)0x80000000)) >> 31);
}
/**
* @brief Sets the PULSETIMERCLEAR field of the RWNXAGCRADARTIM register.
*
* The RWNXAGCRADARTIM register will be read, modified to contain the new field value, and written.
*
* @param[in] pulsetimerclear - The value to set the field to.
*/
__INLINE void agc_pulsetimerclear_setf(uint8_t pulsetimerclear)
{
ASSERT_ERR((((uint32_t)pulsetimerclear << 31) & ~((uint32_t)0x80000000)) == 0);
REG_PL_WR(AGC_RWNXAGCRADARTIM_ADDR, (REG_PL_RD(AGC_RWNXAGCRADARTIM_ADDR) & ~((uint32_t)0x80000000)) | ((uint32_t)pulsetimerclear << 31));
}
/**
* @brief Returns the current value of the PULSEIRQFIFOTHR field in the RWNXAGCRADARTIM register.
*
* The RWNXAGCRADARTIM register will be read and the PULSEIRQFIFOTHR field's value will be returned.
*
* @return The current value of the PULSEIRQFIFOTHR field in the RWNXAGCRADARTIM register.
*/
__INLINE uint8_t agc_pulseirqfifothr_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRADARTIM_ADDR);
return ((localVal & ((uint32_t)0x00070000)) >> 16);
}
/**
* @brief Sets the PULSEIRQFIFOTHR field of the RWNXAGCRADARTIM register.
*
* The RWNXAGCRADARTIM register will be read, modified to contain the new field value, and written.
*
* @param[in] pulseirqfifothr - The value to set the field to.
*/
__INLINE void agc_pulseirqfifothr_setf(uint8_t pulseirqfifothr)
{
ASSERT_ERR((((uint32_t)pulseirqfifothr << 16) & ~((uint32_t)0x00070000)) == 0);
REG_PL_WR(AGC_RWNXAGCRADARTIM_ADDR, (REG_PL_RD(AGC_RWNXAGCRADARTIM_ADDR) & ~((uint32_t)0x00070000)) | ((uint32_t)pulseirqfifothr << 16));
}
/**
* @brief Returns the current value of the PULSEIRQTIMEOUT field in the RWNXAGCRADARTIM register.
*
* The RWNXAGCRADARTIM register will be read and the PULSEIRQTIMEOUT field's value will be returned.
*
* @return The current value of the PULSEIRQTIMEOUT field in the RWNXAGCRADARTIM register.
*/
__INLINE uint8_t agc_pulseirqtimeout_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCRADARTIM_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the PULSEIRQTIMEOUT field of the RWNXAGCRADARTIM register.
*
* The RWNXAGCRADARTIM register will be read, modified to contain the new field value, and written.
*
* @param[in] pulseirqtimeout - The value to set the field to.
*/
__INLINE void agc_pulseirqtimeout_setf(uint8_t pulseirqtimeout)
{
ASSERT_ERR((((uint32_t)pulseirqtimeout << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCRADARTIM_ADDR, (REG_PL_RD(AGC_RWNXAGCRADARTIM_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)pulseirqtimeout << 0));
}
/// @}
/**
* @name RWNXAGCDSP3 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:00 INBDPOWDBVTHR 0xBF
* </pre>
*
* @{
*/
/// Address of the RWNXAGCDSP3 register
#define AGC_RWNXAGCDSP3_ADDR 0x010020A8
/// Offset of the RWNXAGCDSP3 register from the base address
#define AGC_RWNXAGCDSP3_OFFSET 0x000020A8
/// Index of the RWNXAGCDSP3 register
#define AGC_RWNXAGCDSP3_INDEX 0x0000082A
/// Reset value of the RWNXAGCDSP3 register
#define AGC_RWNXAGCDSP3_RESET 0x000000BF
/**
* @brief Returns the current value of the RWNXAGCDSP3 register.
* The RWNXAGCDSP3 register will be read and its value returned.
* @return The current value of the RWNXAGCDSP3 register.
*/
__INLINE uint32_t agc_rwnxagcdsp3_get(void)
{
return REG_PL_RD(AGC_RWNXAGCDSP3_ADDR);
}
/**
* @brief Sets the RWNXAGCDSP3 register to a value.
* The RWNXAGCDSP3 register will be written.
* @param value - The value to write.
*/
__INLINE void agc_rwnxagcdsp3_set(uint32_t value)
{
REG_PL_WR(AGC_RWNXAGCDSP3_ADDR, value);
}
// field definitions
/// INBDPOWDBVTHR field mask
#define AGC_INBDPOWDBVTHR_MASK ((uint32_t)0x000000FF)
/// INBDPOWDBVTHR field LSB position
#define AGC_INBDPOWDBVTHR_LSB 0
/// INBDPOWDBVTHR field width
#define AGC_INBDPOWDBVTHR_WIDTH ((uint32_t)0x00000008)
/// INBDPOWDBVTHR field reset value
#define AGC_INBDPOWDBVTHR_RST 0xBF
/**
* @brief Returns the current value of the INBDPOWDBVTHR field in the RWNXAGCDSP3 register.
*
* The RWNXAGCDSP3 register will be read and the INBDPOWDBVTHR field's value will be returned.
*
* @return The current value of the INBDPOWDBVTHR field in the RWNXAGCDSP3 register.
*/
__INLINE uint8_t agc_inbdpowdbvthr_getf(void)
{
uint32_t localVal = REG_PL_RD(AGC_RWNXAGCDSP3_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0x000000FF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the INBDPOWDBVTHR field of the RWNXAGCDSP3 register.
*
* The RWNXAGCDSP3 register will be read, modified to contain the new field value, and written.
*
* @param[in] inbdpowdbvthr - The value to set the field to.
*/
__INLINE void agc_inbdpowdbvthr_setf(uint8_t inbdpowdbvthr)
{
ASSERT_ERR((((uint32_t)inbdpowdbvthr << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(AGC_RWNXAGCDSP3_ADDR, (uint32_t)inbdpowdbvthr << 0);
}
/// @}
/* On SOC platform, write agc value to (0x01C0A000) may not right */
#define PHY_AGC_UCODE_ADDR (0x0100A000)
#endif // _REG_AGC_H_
/// @}
Raw
reg_dma.h
#ifndef _REG_DMA_H_
#define _REG_DMA_H_
#include "co_int.h"
#include "_reg_dma.h"
#include "compiler.h"
#include "arch.h"
#include "reg_access.h"
#define REG_DMA_COUNT 49
#define REG_DMA_DECODING_MASK 0x000000FF
/**
* @brief CH_LLI_ROOT register definition
*/
__INLINE uint32_t dma_ch_lli_root_get(int reg_idx)
{
return 0;
}
__INLINE void dma_ch_lli_root_set(int reg_idx, uint32_t value)
{
}
/**
* @brief DMA_STATUS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29 DOWN_STREAM_BSY 0
* 28 UP_STREAM_BSY 0
* 27 ARB_Q3_VALID 0
* 26 ARB_Q2_VALID 0
* 25 ARB_Q1_VALID 0
* 24 ARB_Q0_VALID 0
* 23:20 REQUEST_STATE 0x0
* 19 CH3_STOPPED 0
* 18 CH2_STOPPED 0
* 17 CH1_STOPPED 0
* 16 CH0_STOPPED 0
* 15:00 OFT_FREE 0x0
* </pre>
*/
#define DMA_DMA_STATUS_ADDR 0x10A00010
#define DMA_DMA_STATUS_OFFSET 0x00000010
#define DMA_DMA_STATUS_INDEX 0x00000004
#define DMA_DMA_STATUS_RESET 0x00000000
__INLINE uint32_t dma_dma_status_get(void)
{
return 0;
}
// field definitions
#define DMA_DOWN_STREAM_BSY_BIT ((uint32_t)0x20000000)
#define DMA_DOWN_STREAM_BSY_POS 29
#define DMA_UP_STREAM_BSY_BIT ((uint32_t)0x10000000)
#define DMA_UP_STREAM_BSY_POS 28
#define DMA_ARB_Q3_VALID_BIT ((uint32_t)0x08000000)
#define DMA_ARB_Q3_VALID_POS 27
#define DMA_ARB_Q2_VALID_BIT ((uint32_t)0x04000000)
#define DMA_ARB_Q2_VALID_POS 26
#define DMA_ARB_Q1_VALID_BIT ((uint32_t)0x02000000)
#define DMA_ARB_Q1_VALID_POS 25
#define DMA_ARB_Q0_VALID_BIT ((uint32_t)0x01000000)
#define DMA_ARB_Q0_VALID_POS 24
#define DMA_REQUEST_STATE_MASK ((uint32_t)0x00F00000)
#define DMA_REQUEST_STATE_LSB 20
#define DMA_REQUEST_STATE_WIDTH ((uint32_t)0x00000004)
#define DMA_CH3_STOPPED_BIT ((uint32_t)0x00080000)
#define DMA_CH3_STOPPED_POS 19
#define DMA_CH2_STOPPED_BIT ((uint32_t)0x00040000)
#define DMA_CH2_STOPPED_POS 18
#define DMA_CH1_STOPPED_BIT ((uint32_t)0x00020000)
#define DMA_CH1_STOPPED_POS 17
#define DMA_CH0_STOPPED_BIT ((uint32_t)0x00010000)
#define DMA_CH0_STOPPED_POS 16
#define DMA_OFT_FREE_MASK ((uint32_t)0x0000FFFF)
#define DMA_OFT_FREE_LSB 0
#define DMA_OFT_FREE_WIDTH ((uint32_t)0x00000010)
#define DMA_DOWN_STREAM_BSY_RST 0x0
#define DMA_UP_STREAM_BSY_RST 0x0
#define DMA_ARB_Q3_VALID_RST 0x0
#define DMA_ARB_Q2_VALID_RST 0x0
#define DMA_ARB_Q1_VALID_RST 0x0
#define DMA_ARB_Q0_VALID_RST 0x0
#define DMA_REQUEST_STATE_RST 0x0
#define DMA_CH3_STOPPED_RST 0x0
#define DMA_CH2_STOPPED_RST 0x0
#define DMA_CH1_STOPPED_RST 0x0
#define DMA_CH0_STOPPED_RST 0x0
#define DMA_OFT_FREE_RST 0x0
__INLINE void dma_dma_status_unpack(uint8_t *downstreambsy, uint8_t *upstreambsy, uint8_t *arbq3valid, uint8_t *arbq2valid, uint8_t *arbq1valid, uint8_t *arbq0valid, uint8_t *requeststate, uint8_t *ch3stopped, uint8_t *ch2stopped, uint8_t *ch1stopped, uint8_t *ch0stopped, uint16_t *oftfree)
{
}
__INLINE uint8_t dma_dma_status_down_stream_bsy_getf(void)
{
return 0;
}
__INLINE uint8_t dma_dma_status_up_stream_bsy_getf(void)
{
return 0;
}
__INLINE uint8_t dma_dma_status_arb_q3_valid_getf(void)
{
return 0;
}
__INLINE uint8_t dma_dma_status_arb_q2_valid_getf(void)
{
return 0;
}
__INLINE uint8_t dma_dma_status_arb_q1_valid_getf(void)
{
return 0;
}
__INLINE uint8_t dma_dma_status_arb_q0_valid_getf(void)
{
return 0;
}
__INLINE uint8_t dma_dma_status_request_state_getf(void)
{
return 0;
}
__INLINE uint8_t dma_dma_status_ch3_stopped_getf(void)
{
return 0;
}
__INLINE uint8_t dma_dma_status_ch2_stopped_getf(void)
{
return 0;
}
__INLINE uint8_t dma_dma_status_ch1_stopped_getf(void)
{
return 0;
}
__INLINE uint8_t dma_dma_status_ch0_stopped_getf(void)
{
return 0;
}
/**
* @brief INT_RAWSTATUS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23 CH3_EOT 0
* 22 CH2_EOT 0
* 21 CH1_EOT 0
* 20 CH0_EOT 0
* 16 ERROR 0
* 15:00 LLI_IRQ 0x0
* </pre>
*/
#define DMA_INT_RAWSTATUS_ADDR 0x10A00014
#define DMA_INT_RAWSTATUS_OFFSET 0x00000014
#define DMA_INT_RAWSTATUS_INDEX 0x00000005
#define DMA_INT_RAWSTATUS_RESET 0x00000000
__INLINE uint32_t dma_int_rawstatus_get(void)
{
return 0;
}
// field definitions
#define DMA_CH3_EOT_BIT ((uint32_t)0x00800000)
#define DMA_CH3_EOT_POS 23
#define DMA_CH2_EOT_BIT ((uint32_t)0x00400000)
#define DMA_CH2_EOT_POS 22
#define DMA_CH1_EOT_BIT ((uint32_t)0x00200000)
#define DMA_CH1_EOT_POS 21
#define DMA_CH0_EOT_BIT ((uint32_t)0x00100000)
#define DMA_CH0_EOT_POS 20
#define DMA_ERROR_BIT ((uint32_t)0x00010000)
#define DMA_ERROR_POS 16
#define DMA_LLI_IRQ_MASK ((uint32_t)0x0000FFFF)
#define DMA_LLI_IRQ_LSB 0
#define DMA_LLI_IRQ_WIDTH ((uint32_t)0x00000010)
#define DMA_CH3_EOT_RST 0x0
#define DMA_CH2_EOT_RST 0x0
#define DMA_CH1_EOT_RST 0x0
#define DMA_CH0_EOT_RST 0x0
#define DMA_ERROR_RST 0x0
#define DMA_LLI_IRQ_RST 0x0
__INLINE void dma_int_rawstatus_unpack(uint8_t *ch3eot, uint8_t *ch2eot, uint8_t *ch1eot, uint8_t *ch0eot, uint8_t *error, uint16_t *lliirq)
{
}
__INLINE uint8_t dma_int_rawstatus_ch3_eot_getf(void)
{
return 0;
}
__INLINE uint8_t dma_int_rawstatus_ch2_eot_getf(void)
{
return 0;
}
__INLINE uint8_t dma_int_rawstatus_ch1_eot_getf(void)
{
return 0;
}
__INLINE uint8_t dma_int_rawstatus_ch0_eot_getf(void)
{
return 0;
}
__INLINE uint8_t dma_int_rawstatus_error_getf(void)
{
return 0;
}
__INLINE uint16_t dma_int_rawstatus_lli_irq_getf(void)
{
return 0;
}
/**
* @brief INT_UNMASK_SET register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23 CH3_EOT 0
* 22 CH2_EOT 0
* 21 CH1_EOT 0
* 20 CH0_EOT 0
* 16 ERROR 0
* 15:00 LLI_IRQ 0x0
* </pre>
*/
#define DMA_INT_UNMASK_SET_ADDR 0x10A00018
#define DMA_INT_UNMASK_SET_OFFSET 0x00000018
#define DMA_INT_UNMASK_SET_INDEX 0x00000006
#define DMA_INT_UNMASK_SET_RESET 0x00000000
__INLINE uint32_t dma_int_unmask_get(void)
{
return 0;
}
__INLINE void dma_int_unmask_set(uint32_t value)
{
}
// field definitions
#define DMA_CH3_EOT_BIT ((uint32_t)0x00800000)
#define DMA_CH3_EOT_POS 23
#define DMA_CH2_EOT_BIT ((uint32_t)0x00400000)
#define DMA_CH2_EOT_POS 22
#define DMA_CH1_EOT_BIT ((uint32_t)0x00200000)
#define DMA_CH1_EOT_POS 21
#define DMA_CH0_EOT_BIT ((uint32_t)0x00100000)
#define DMA_CH0_EOT_POS 20
#define DMA_ERROR_BIT ((uint32_t)0x00010000)
#define DMA_ERROR_POS 16
#define DMA_LLI_IRQ_MASK ((uint32_t)0x0000FFFF)
#define DMA_LLI_IRQ_LSB 0
#define DMA_LLI_IRQ_WIDTH ((uint32_t)0x00000010)
#define DMA_CH3_EOT_RST 0x0
#define DMA_CH2_EOT_RST 0x0
#define DMA_CH1_EOT_RST 0x0
#define DMA_CH0_EOT_RST 0x0
#define DMA_ERROR_RST 0x0
#define DMA_LLI_IRQ_RST 0x0
__INLINE void dma_int_unmask_set_pack(uint8_t ch3eot, uint8_t ch2eot, uint8_t ch1eot, uint8_t ch0eot, uint8_t error, uint16_t lliirq)
{
}
__INLINE void dma_int_unmask_unpack(uint8_t *ch3eot, uint8_t *ch2eot, uint8_t *ch1eot, uint8_t *ch0eot, uint8_t *error, uint16_t *lliirq)
{
}
__INLINE uint8_t dma_int_unmask_ch3_eot_getf(void)
{
return 0;
}
__INLINE void dma_int_unmask_ch3_eot_setf(uint8_t ch3eot)
{
}
__INLINE uint8_t dma_int_unmask_ch2_eot_getf(void)
{
return 0;
}
__INLINE void dma_int_unmask_ch2_eot_setf(uint8_t ch2eot)
{
}
__INLINE uint8_t dma_int_unmask_ch1_eot_getf(void)
{
return 0;
}
__INLINE void dma_int_unmask_ch1_eot_setf(uint8_t ch1eot)
{
}
__INLINE uint8_t dma_int_unmask_ch0_eot_getf(void)
{
return 0;
}
__INLINE void dma_int_unmask_ch0_eot_setf(uint8_t ch0eot)
{
}
__INLINE uint8_t dma_int_unmask_error_getf(void)
{
return 0;
}
__INLINE void dma_int_unmask_error_setf(uint8_t error)
{
}
__INLINE uint16_t dma_int_unmask_lli_irq_getf(void)
{
return 0;
}
__INLINE void dma_int_unmask_lli_irq_setf(uint16_t lliirq)
{
}
/**
* @brief INT_UNMASK_CLEAR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23 CH3_EOT 0
* 22 CH2_EOT 0
* 21 CH1_EOT 0
* 20 CH0_EOT 0
* 16 ERROR 0
* 15:00 LLI_IRQ 0x0
* </pre>
*/
#define DMA_INT_UNMASK_CLEAR_ADDR 0x10A0001C
#define DMA_INT_UNMASK_CLEAR_OFFSET 0x0000001C
#define DMA_INT_UNMASK_CLEAR_INDEX 0x00000007
#define DMA_INT_UNMASK_CLEAR_RESET 0x00000000
__INLINE void dma_int_unmask_clear(uint32_t value)
{
}
// fields defined in symmetrical set/clear register
__INLINE void dma_int_unmask_clear_pack(uint8_t ch3eot, uint8_t ch2eot, uint8_t ch1eot, uint8_t ch0eot, uint8_t error, uint16_t lliirq)
{
}
__INLINE void dma_int_unmask_ch3_eot_clearf(uint8_t ch3eot)
{
}
__INLINE void dma_int_unmask_ch2_eot_clearf(uint8_t ch2eot)
{
}
__INLINE void dma_int_unmask_ch1_eot_clearf(uint8_t ch1eot)
{
}
__INLINE void dma_int_unmask_ch0_eot_clearf(uint8_t ch0eot)
{
}
__INLINE void dma_int_unmask_error_clearf(uint8_t error)
{
}
__INLINE void dma_int_unmask_lli_irq_clearf(uint16_t lliirq)
{
}
/**
* @brief INT_ACK register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23 CH3_EOT 0
* 22 CH2_EOT 0
* 21 CH1_EOT 0
* 20 CH0_EOT 0
* 16 ERROR 0
* 15:00 LLI_IRQ 0x0
* </pre>
*/
#define DMA_INT_ACK_ADDR 0x10A00020
#define DMA_INT_ACK_OFFSET 0x00000020
#define DMA_INT_ACK_INDEX 0x00000008
#define DMA_INT_ACK_RESET 0x00000000
__INLINE uint32_t dma_int_ack_get(void)
{
return 0;
}
__INLINE void dma_int_ack_clear(uint32_t value)
{
}
// field definitions
#define DMA_CH3_EOT_BIT ((uint32_t)0x00800000)
#define DMA_CH3_EOT_POS 23
#define DMA_CH2_EOT_BIT ((uint32_t)0x00400000)
#define DMA_CH2_EOT_POS 22
#define DMA_CH1_EOT_BIT ((uint32_t)0x00200000)
#define DMA_CH1_EOT_POS 21
#define DMA_CH0_EOT_BIT ((uint32_t)0x00100000)
#define DMA_CH0_EOT_POS 20
#define DMA_ERROR_BIT ((uint32_t)0x00010000)
#define DMA_ERROR_POS 16
#define DMA_LLI_IRQ_MASK ((uint32_t)0x0000FFFF)
#define DMA_LLI_IRQ_LSB 0
#define DMA_LLI_IRQ_WIDTH ((uint32_t)0x00000010)
#define DMA_CH3_EOT_RST 0x0
#define DMA_CH2_EOT_RST 0x0
#define DMA_CH1_EOT_RST 0x0
#define DMA_CH0_EOT_RST 0x0
#define DMA_ERROR_RST 0x0
#define DMA_LLI_IRQ_RST 0x0
__INLINE void dma_int_ack_pack(uint8_t ch3eot, uint8_t ch2eot, uint8_t ch1eot, uint8_t ch0eot, uint8_t error, uint16_t lliirq)
{
}
__INLINE void dma_int_ack_unpack(uint8_t *ch3eot, uint8_t *ch2eot, uint8_t *ch1eot, uint8_t *ch0eot, uint8_t *error, uint16_t *lliirq)
{
}
__INLINE uint8_t dma_int_ack_ch3_eot_getf(void)
{
return 0;
}
__INLINE void dma_int_ack_ch3_eot_clearf(uint8_t ch3eot)
{
}
__INLINE uint8_t dma_int_ack_ch2_eot_getf(void)
{
return 0;
}
__INLINE void dma_int_ack_ch2_eot_clearf(uint8_t ch2eot)
{
}
__INLINE uint8_t dma_int_ack_ch1_eot_getf(void)
{
return 0;
}
__INLINE void dma_int_ack_ch1_eot_clearf(uint8_t ch1eot)
{
}
__INLINE uint8_t dma_int_ack_ch0_eot_getf(void)
{
return 0;
}
__INLINE void dma_int_ack_ch0_eot_clearf(uint8_t ch0eot)
{
}
__INLINE uint8_t dma_int_ack_error_getf(void)
{
return 0;
}
__INLINE void dma_int_ack_error_clearf(uint8_t error)
{
}
__INLINE uint16_t dma_int_ack_lli_irq_getf(void)
{
return 0;
}
__INLINE void dma_int_ack_lli_irq_clearf(uint16_t lliirq)
{
}
/**
* @brief INT_STATUS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23 CH3_EOT 0
* 22 CH2_EOT 0
* 21 CH1_EOT 0
* 20 CH0_EOT 0
* 16 ERROR 0
* 15:00 LLI_IRQ 0x0
* </pre>
*/
#define DMA_INT_STATUS_ADDR 0x10A00024
#define DMA_INT_STATUS_OFFSET 0x00000024
#define DMA_INT_STATUS_INDEX 0x00000009
#define DMA_INT_STATUS_RESET 0x00000000
__INLINE uint32_t dma_int_status_get(void)
{
return REG_PL_RD(DMA_INT_STATUS_ADDR);
}
// field definitions
#define DMA_CH3_EOT_BIT ((uint32_t)0x00800000)
#define DMA_CH3_EOT_POS 23
#define DMA_CH2_EOT_BIT ((uint32_t)0x00400000)
#define DMA_CH2_EOT_POS 22
#define DMA_CH1_EOT_BIT ((uint32_t)0x00200000)
#define DMA_CH1_EOT_POS 21
#define DMA_CH0_EOT_BIT ((uint32_t)0x00100000)
#define DMA_CH0_EOT_POS 20
#define DMA_ERROR_BIT ((uint32_t)0x00010000)
#define DMA_ERROR_POS 16
#define DMA_LLI_IRQ_MASK ((uint32_t)0x0000FFFF)
#define DMA_LLI_IRQ_LSB 0
#define DMA_LLI_IRQ_WIDTH ((uint32_t)0x00000010)
#define DMA_CH3_EOT_RST 0x0
#define DMA_CH2_EOT_RST 0x0
#define DMA_CH1_EOT_RST 0x0
#define DMA_CH0_EOT_RST 0x0
#define DMA_ERROR_RST 0x0
#define DMA_LLI_IRQ_RST 0x0
__INLINE void dma_int_status_unpack(uint8_t *ch3eot, uint8_t *ch2eot, uint8_t *ch1eot, uint8_t *ch0eot, uint8_t *error, uint16_t *lliirq)
{
}
__INLINE uint8_t dma_int_status_ch3_eot_getf(void)
{
return 0;
}
__INLINE uint8_t dma_int_status_ch2_eot_getf(void)
{
return 0;
}
__INLINE uint8_t dma_int_status_ch1_eot_getf(void)
{
return 0;
}
__INLINE uint8_t dma_int_status_ch0_eot_getf(void)
{
return 0;
}
__INLINE uint8_t dma_int_status_error_getf(void)
{
return 0;
}
__INLINE uint16_t dma_int_status_lli_irq_getf(void)
{
return 0;
}
/**
* @brief CHANNEL_PRIORITY register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 16 INTERLEAVE_ENABLED 0
* 13:12 CH3_PRIORITY 0x0
* 09:08 CH2_PRIORITY 0x0
* 05:04 CH1_PRIORITY 0x0
* 01:00 CH0_PRIORITY 0x0
* </pre>
*/
#define DMA_CHANNEL_PRIORITY_ADDR 0x10A00034
#define DMA_CHANNEL_PRIORITY_OFFSET 0x00000034
#define DMA_CHANNEL_PRIORITY_INDEX 0x0000000D
#define DMA_CHANNEL_PRIORITY_RESET 0x00000000
__INLINE uint32_t dma_channel_priority_get(void)
{
return 0;
}
__INLINE void dma_channel_priority_set(uint32_t value)
{
REG_PL_WR(DMA_CHANNEL_PRIORITY_ADDR, value);
}
// field definitions
#define DMA_INTERLEAVE_ENABLED_BIT ((uint32_t)0x00010000)
#define DMA_INTERLEAVE_ENABLED_POS 16
#define DMA_CH3_PRIORITY_MASK ((uint32_t)0x00003000)
#define DMA_CH3_PRIORITY_LSB 12
#define DMA_CH3_PRIORITY_WIDTH ((uint32_t)0x00000002)
#define DMA_CH2_PRIORITY_MASK ((uint32_t)0x00000300)
#define DMA_CH2_PRIORITY_LSB 8
#define DMA_CH2_PRIORITY_WIDTH ((uint32_t)0x00000002)
#define DMA_CH1_PRIORITY_MASK ((uint32_t)0x00000030)
#define DMA_CH1_PRIORITY_LSB 4
#define DMA_CH1_PRIORITY_WIDTH ((uint32_t)0x00000002)
#define DMA_CH0_PRIORITY_MASK ((uint32_t)0x00000003)
#define DMA_CH0_PRIORITY_LSB 0
#define DMA_CH0_PRIORITY_WIDTH ((uint32_t)0x00000002)
#define DMA_INTERLEAVE_ENABLED_RST 0x0
#define DMA_CH3_PRIORITY_RST 0x0
#define DMA_CH2_PRIORITY_RST 0x0
#define DMA_CH1_PRIORITY_RST 0x0
#define DMA_CH0_PRIORITY_RST 0x0
__INLINE void dma_channel_priority_pack(uint8_t interleaveenabled, uint8_t ch3priority, uint8_t ch2priority, uint8_t ch1priority, uint8_t ch0priority)
{
}
__INLINE void dma_channel_priority_unpack(uint8_t *interleaveenabled, uint8_t *ch3priority, uint8_t *ch2priority, uint8_t *ch1priority, uint8_t *ch0priority)
{
}
__INLINE uint8_t dma_channel_priority_interleave_enabled_getf(void)
{
return 0;
}
__INLINE void dma_channel_priority_interleave_enabled_setf(uint8_t interleaveenabled)
{
}
__INLINE uint8_t dma_channel_priority_ch3_priority_getf(void)
{
return 0;
}
__INLINE void dma_channel_priority_ch3_priority_setf(uint8_t ch3priority)
{
}
__INLINE uint8_t dma_channel_priority_ch2_priority_getf(void)
{
return 0;
}
__INLINE void dma_channel_priority_ch2_priority_setf(uint8_t ch2priority)
{
}
__INLINE uint8_t dma_channel_priority_ch1_priority_getf(void)
{
return 0;
}
__INLINE void dma_channel_priority_ch1_priority_setf(uint8_t ch1priority)
{
}
__INLINE uint8_t dma_channel_priority_ch0_priority_getf(void)
{
return 0;
}
__INLINE void dma_channel_priority_ch0_priority_setf(uint8_t ch0priority)
{
}
/**
* @brief CHANNEL_MUTEX_SET register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03 CH3_MUTEX 0
* 02 CH2_MUTEX 0
* 01 CH1_MUTEX 0
* 00 CH0_MUTEX 0
* </pre>
*/
#define DMA_CHANNEL_MUTEX_SET_ADDR 0x10A00038
#define DMA_CHANNEL_MUTEX_SET_OFFSET 0x00000038
#define DMA_CHANNEL_MUTEX_SET_INDEX 0x0000000E
#define DMA_CHANNEL_MUTEX_SET_RESET 0x00000000
__INLINE uint32_t dma_channel_mutex_get(void)
{
return 0;
}
__INLINE void dma_channel_mutex_set(uint32_t value)
{
}
// field definitions
#define DMA_CH3_MUTEX_BIT ((uint32_t)0x00000008)
#define DMA_CH3_MUTEX_POS 3
#define DMA_CH2_MUTEX_BIT ((uint32_t)0x00000004)
#define DMA_CH2_MUTEX_POS 2
#define DMA_CH1_MUTEX_BIT ((uint32_t)0x00000002)
#define DMA_CH1_MUTEX_POS 1
#define DMA_CH0_MUTEX_BIT ((uint32_t)0x00000001)
#define DMA_CH0_MUTEX_POS 0
#define DMA_CH3_MUTEX_RST 0x0
#define DMA_CH2_MUTEX_RST 0x0
#define DMA_CH1_MUTEX_RST 0x0
#define DMA_CH0_MUTEX_RST 0x0
__INLINE void dma_channel_mutex_set_pack(uint8_t ch3mutex, uint8_t ch2mutex, uint8_t ch1mutex, uint8_t ch0mutex)
{
}
__INLINE void dma_channel_mutex_unpack(uint8_t *ch3mutex, uint8_t *ch2mutex, uint8_t *ch1mutex, uint8_t *ch0mutex)
{
}
__INLINE uint8_t dma_channel_mutex_ch3_mutex_getf(void)
{
return 0;
}
__INLINE void dma_channel_mutex_ch3_mutex_setf(uint8_t ch3mutex)
{
}
__INLINE uint8_t dma_channel_mutex_ch2_mutex_getf(void)
{
return 0;
}
__INLINE void dma_channel_mutex_ch2_mutex_setf(uint8_t ch2mutex)
{
}
__INLINE uint8_t dma_channel_mutex_ch1_mutex_getf(void)
{
return 0;
}
__INLINE void dma_channel_mutex_ch1_mutex_setf(uint8_t ch1mutex)
{
}
__INLINE uint8_t dma_channel_mutex_ch0_mutex_getf(void)
{
return 0;
}
__INLINE void dma_channel_mutex_ch0_mutex_setf(uint8_t ch0mutex)
{
}
/**
* @brief CHANNEL_MUTEX_CLEAR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03 CH3_MUTEX 0
* 02 CH2_MUTEX 0
* 01 CH1_MUTEX 0
* 00 CH0_MUTEX 0
* </pre>
*/
#define DMA_CHANNEL_MUTEX_CLEAR_ADDR 0x10A0003C
#define DMA_CHANNEL_MUTEX_CLEAR_OFFSET 0x0000003C
#define DMA_CHANNEL_MUTEX_CLEAR_INDEX 0x0000000F
#define DMA_CHANNEL_MUTEX_CLEAR_RESET 0x00000000
__INLINE void dma_channel_mutex_clear(uint32_t value)
{
}
// fields defined in symmetrical set/clear register
__INLINE void dma_channel_mutex_clear_pack(uint8_t ch3mutex, uint8_t ch2mutex, uint8_t ch1mutex, uint8_t ch0mutex)
{
}
__INLINE void dma_channel_mutex_ch3_mutex_clearf(uint8_t ch3mutex)
{
}
__INLINE void dma_channel_mutex_ch2_mutex_clearf(uint8_t ch2mutex)
{
}
__INLINE void dma_channel_mutex_ch1_mutex_clearf(uint8_t ch1mutex)
{
}
__INLINE void dma_channel_mutex_ch0_mutex_clearf(uint8_t ch0mutex)
{
}
// field definitions
#define DMA_COUNTER_MASK ((uint32_t)0x0000FFFF)
#define DMA_COUNTER_LSB 0
#define DMA_COUNTER_WIDTH ((uint32_t)0x00000010)
#define DMA_COUNTER_RST 0x0
/**
* @brief DUMMY register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 00 DUMMY 0
* </pre>
*/
#define DMA_DUMMY_ADDR 0x10A000C0
#define DMA_DUMMY_OFFSET 0x000000C0
#define DMA_DUMMY_INDEX 0x00000030
#define DMA_DUMMY_RESET 0x00000000
__INLINE uint32_t dma_dummy_get(void)
{
return 0;
}
__INLINE void dma_dummy_set(uint32_t value)
{
}
// field definitions
#define DMA_DUMMY_BIT ((uint32_t)0x00000001)
#define DMA_DUMMY_POS 0
#define DMA_DUMMY_RST 0x0
__INLINE uint8_t dma_dummy_getf(void)
{
return 0;
}
__INLINE void dma_dummy_setf(uint8_t dummy)
{
}
#endif // _REG_DMA_H_
Raw
reg_intc.h
/**
* @file reg_intc.h
* @brief Definitions of the INTC HW block registers and register access functions.
*
* @defgroup REG_INTC REG_INTC
* @ingroup REG
* @{
*
* @brief Definitions of the INTC HW block registers and register access functions.
*/
#ifndef _REG_INTC_H_
#define _REG_INTC_H_
#include "co_int.h"
#include "_reg_intc.h"
#include "compiler.h"
#include "arch.h"
#include "reg_access.h"
/** @brief Number of registers in the REG_INTC peripheral.
*/
#define REG_INTC_COUNT 17
/** @brief Decoding mask of the REG_INTC peripheral registers from the CPU point of view.
*/
#define REG_INTC_DECODING_MASK 0x0000007F
/**
* @name IRQ_STATUS register definitions
*
* @{
*/
/// Address of the IRQ_STATUS register
#define INTC_IRQ_STATUS_ADDR 0x10910000
/// Offset of the IRQ_STATUS register from the base address
#define INTC_IRQ_STATUS_OFFSET 0x00000000
/// Index of the IRQ_STATUS register
#define INTC_IRQ_STATUS_INDEX 0x00000000
/// Reset value of the IRQ_STATUS register
#define INTC_IRQ_STATUS_RESET 0x00000000
/// Number of elements of the IRQ_STATUS register array
#define INTC_IRQ_STATUS_COUNT 2
/**
* @brief Returns the current value of the IRQ_STATUS register.
* The IRQ_STATUS register will be read and its value returned.
* @param[in] reg_idx Index of the register
* @return The current value of the IRQ_STATUS register.
*/
__INLINE uint32_t intc_irq_status_get(int reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return REG_PL_RD(INTC_IRQ_STATUS_ADDR + reg_idx * 4);
}
/// @}
/**
* @name IRQ_RAW_STATUS register definitions
*
* @{
*/
/// Address of the IRQ_RAW_STATUS register
#define INTC_IRQ_RAW_STATUS_ADDR 0x10910008
/// Offset of the IRQ_RAW_STATUS register from the base address
#define INTC_IRQ_RAW_STATUS_OFFSET 0x00000008
/// Index of the IRQ_RAW_STATUS register
#define INTC_IRQ_RAW_STATUS_INDEX 0x00000002
/// Reset value of the IRQ_RAW_STATUS register
#define INTC_IRQ_RAW_STATUS_RESET 0x00000000
/// Number of elements of the IRQ_RAW_STATUS register array
#define INTC_IRQ_RAW_STATUS_COUNT 2
/**
* @brief Returns the current value of the IRQ_RAW_STATUS register.
* The IRQ_RAW_STATUS register will be read and its value returned.
* @param[in] reg_idx Index of the register
* @return The current value of the IRQ_RAW_STATUS register.
*/
__INLINE uint32_t intc_irq_raw_status_get(int reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return REG_PL_RD(INTC_IRQ_RAW_STATUS_ADDR + reg_idx * 4);
}
/// @}
/**
* @name IRQ_UNMASK_SET register definitions
*
* @{
*/
/// Address of the IRQ_UNMASK_SET register
#define INTC_IRQ_UNMASK_SET_ADDR 0x10910010
/// Offset of the IRQ_UNMASK_SET register from the base address
#define INTC_IRQ_UNMASK_SET_OFFSET 0x00000010
/// Index of the IRQ_UNMASK_SET register
#define INTC_IRQ_UNMASK_SET_INDEX 0x00000004
/// Reset value of the IRQ_UNMASK_SET register
#define INTC_IRQ_UNMASK_SET_RESET 0x00000000
/// Number of elements of the IRQ_UNMASK_SET register array
#define INTC_IRQ_UNMASK_SET_COUNT 2
/**
* @brief Returns the current value of the IRQ_UNMASK_SET register.
* The IRQ_UNMASK_SET register will be read and its value returned.
* @param[in] reg_idx Index of the register
* @return The current value of the IRQ_UNMASK_SET register.
*/
__INLINE uint32_t intc_irq_unmask_get(int reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return REG_PL_RD(INTC_IRQ_UNMASK_SET_ADDR + reg_idx * 4);
}
/**
* @brief Sets the IRQ_UNMASK_SET register to a value.
* The IRQ_UNMASK_SET register will be written.
* @param[in] reg_idx Index of the register
* @param value - The value to write.
*/
__INLINE void intc_irq_unmask_set(int reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
REG_PL_WR(INTC_IRQ_UNMASK_SET_ADDR + reg_idx * 4, value);
}
/// @}
/**
* @name IRQ_UNMASK_CLEAR register definitions
*
* @{
*/
/// Address of the IRQ_UNMASK_CLEAR register
#define INTC_IRQ_UNMASK_CLEAR_ADDR 0x10910018
/// Offset of the IRQ_UNMASK_CLEAR register from the base address
#define INTC_IRQ_UNMASK_CLEAR_OFFSET 0x00000018
/// Index of the IRQ_UNMASK_CLEAR register
#define INTC_IRQ_UNMASK_CLEAR_INDEX 0x00000006
/// Reset value of the IRQ_UNMASK_CLEAR register
#define INTC_IRQ_UNMASK_CLEAR_RESET 0x00000000
/// Number of elements of the IRQ_UNMASK_CLEAR register array
#define INTC_IRQ_UNMASK_CLEAR_COUNT 2
/**
* @brief Sets the IRQ_UNMASK_CLEAR register to a value.
* The IRQ_UNMASK_CLEAR register will be written.
* @param[in] reg_idx Index of the register
* @param value - The value to write.
*/
__INLINE void intc_irq_unmask_clear(int reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
REG_PL_WR(INTC_IRQ_UNMASK_CLEAR_ADDR + reg_idx * 4, value);
}
/// @}
/**
* @name IRQ_POLARITY register definitions
*
* @{
*/
/// Address of the IRQ_POLARITY register
#define INTC_IRQ_POLARITY_ADDR 0x10910020
/// Offset of the IRQ_POLARITY register from the base address
#define INTC_IRQ_POLARITY_OFFSET 0x00000020
/// Index of the IRQ_POLARITY register
#define INTC_IRQ_POLARITY_INDEX 0x00000008
/// Reset value of the IRQ_POLARITY register
#define INTC_IRQ_POLARITY_RESET 0x00000000
/// Number of elements of the IRQ_POLARITY register array
#define INTC_IRQ_POLARITY_COUNT 2
/**
* @brief Returns the current value of the IRQ_POLARITY register.
* The IRQ_POLARITY register will be read and its value returned.
* @param[in] reg_idx Index of the register
* @return The current value of the IRQ_POLARITY register.
*/
__INLINE uint32_t intc_irq_polarity_get(int reg_idx)
{
ASSERT_ERR(reg_idx <= 1);
return REG_PL_RD(INTC_IRQ_POLARITY_ADDR + reg_idx * 4);
}
/**
* @brief Sets the IRQ_POLARITY register to a value.
* The IRQ_POLARITY register will be written.
* @param[in] reg_idx Index of the register
* @param value - The value to write.
*/
__INLINE void intc_irq_polarity_set(int reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 1);
REG_PL_WR(INTC_IRQ_POLARITY_ADDR + reg_idx * 4, value);
}
/// @}
/**
* @name IRQ_INDEX register definitions
*
* @{
*/
/// Address of the IRQ_INDEX register
#define INTC_IRQ_INDEX_ADDR 0x10910040
/// Offset of the IRQ_INDEX register from the base address
#define INTC_IRQ_INDEX_OFFSET 0x00000040
/// Index of the IRQ_INDEX register
#define INTC_IRQ_INDEX_INDEX 0x00000010
/// Reset value of the IRQ_INDEX register
#define INTC_IRQ_INDEX_RESET 0x00000000
/**
* @brief Returns the current value of the IRQ_INDEX register.
* The IRQ_INDEX register will be read and its value returned.
* @return The current value of the IRQ_INDEX register.
*/
__INLINE uint32_t intc_irq_index_get(void)
{
return REG_PL_RD(INTC_IRQ_INDEX_ADDR);
}
/// @}
#endif // _REG_INTC_H_
/// @}
Raw
reg_la.h
/**
* @file reg_la.h
* @brief Definitions of the LA HW block registers and register access functions.
*
* @defgroup REG_LA REG_LA
* @ingroup REG
* @{
*
* @brief Definitions of the LA HW block registers and register access functions.
*/
#ifndef _REG_LA_H_
#define _REG_LA_H_
#include "co_int.h"
#include "_reg_la.h"
#include "compiler.h"
#include "arch.h"
#include "reg_access.h"
/** @brief Number of registers in the REG_LA peripheral.
*/
#define REG_LA_COUNT 16
/** @brief Decoding mask of the REG_LA peripheral registers from the CPU point of view.
*/
#define REG_LA_DECODING_MASK 0x0000003F
/**
* @name ID_LOW register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 id_low 0x0
* </pre>
*
* @{
*/
/// Address of the ID_LOW register
#define LA_ID_LOW_ADDR 0x10E00000
/// Offset of the ID_LOW register from the base address
#define LA_ID_LOW_OFFSET 0x00000000
/// Index of the ID_LOW register
#define LA_ID_LOW_INDEX 0x00000000
/// Reset value of the ID_LOW register
#define LA_ID_LOW_RESET 0x00000000
/**
* @brief Returns the current value of the ID_LOW register.
* The ID_LOW register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the ID_LOW register.
*/
__INLINE uint32_t la_id_low_get(int elt_idx)
{
return REG_PL_RD(LA_ID_LOW_ADDR + elt_idx * REG_LA_OFFSET);
}
// field definitions
/// ID_LOW field mask
#define LA_ID_LOW_MASK ((uint32_t)0xFFFFFFFF)
/// ID_LOW field LSB position
#define LA_ID_LOW_LSB 0
/// ID_LOW field width
#define LA_ID_LOW_WIDTH ((uint32_t)0x00000020)
/// ID_LOW field reset value
#define LA_ID_LOW_RST 0x0
/**
* @brief Returns the current value of the id_low field in the ID_LOW register.
*
* The ID_LOW register will be read and the id_low field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the id_low field in the ID_LOW register.
*/
__INLINE uint32_t la_id_low_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_ID_LOW_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/// @}
/**
* @name ID_HIGH register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 id_high 0x0
* </pre>
*
* @{
*/
/// Address of the ID_HIGH register
#define LA_ID_HIGH_ADDR 0x10E00004
/// Offset of the ID_HIGH register from the base address
#define LA_ID_HIGH_OFFSET 0x00000004
/// Index of the ID_HIGH register
#define LA_ID_HIGH_INDEX 0x00000001
/// Reset value of the ID_HIGH register
#define LA_ID_HIGH_RESET 0x00000000
/**
* @brief Returns the current value of the ID_HIGH register.
* The ID_HIGH register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the ID_HIGH register.
*/
__INLINE uint32_t la_id_high_get(int elt_idx)
{
return REG_PL_RD(LA_ID_HIGH_ADDR + elt_idx * REG_LA_OFFSET);
}
// field definitions
/// ID_HIGH field mask
#define LA_ID_HIGH_MASK ((uint32_t)0xFFFFFFFF)
/// ID_HIGH field LSB position
#define LA_ID_HIGH_LSB 0
/// ID_HIGH field width
#define LA_ID_HIGH_WIDTH ((uint32_t)0x00000020)
/// ID_HIGH field reset value
#define LA_ID_HIGH_RST 0x0
/**
* @brief Returns the current value of the id_high field in the ID_HIGH register.
*
* The ID_HIGH register will be read and the id_high field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the id_high field in the ID_HIGH register.
*/
__INLINE uint32_t la_id_high_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_ID_HIGH_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/// @}
/**
* @name VERSION register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 version 0x0
* </pre>
*
* @{
*/
/// Address of the VERSION register
#define LA_VERSION_ADDR 0x10E00008
/// Offset of the VERSION register from the base address
#define LA_VERSION_OFFSET 0x00000008
/// Index of the VERSION register
#define LA_VERSION_INDEX 0x00000002
/// Reset value of the VERSION register
#define LA_VERSION_RESET 0x00000000
/**
* @brief Returns the current value of the VERSION register.
* The VERSION register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the VERSION register.
*/
__INLINE uint32_t la_version_get(int elt_idx)
{
return REG_PL_RD(LA_VERSION_ADDR + elt_idx * REG_LA_OFFSET);
}
// field definitions
/// VERSION field mask
#define LA_VERSION_MASK ((uint32_t)0xFFFFFFFF)
/// VERSION field LSB position
#define LA_VERSION_LSB 0
/// VERSION field width
#define LA_VERSION_WIDTH ((uint32_t)0x00000020)
/// VERSION field reset value
#define LA_VERSION_RST 0x0
/**
* @brief Returns the current value of the version field in the VERSION register.
*
* The VERSION register will be read and the version field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the version field in the VERSION register.
*/
__INLINE uint32_t la_version_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_VERSION_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/// @}
/**
* @name CNTRL register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 02 reset 0
* 01 stop 0
* 00 start 0
* </pre>
*
* @{
*/
/// Address of the CNTRL register
#define LA_CNTRL_ADDR 0x10E0000C
/// Offset of the CNTRL register from the base address
#define LA_CNTRL_OFFSET 0x0000000C
/// Index of the CNTRL register
#define LA_CNTRL_INDEX 0x00000003
/// Reset value of the CNTRL register
#define LA_CNTRL_RESET 0x00000000
/**
* @brief Sets the CNTRL register to a value.
* The CNTRL register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_cntrl_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_CNTRL_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// RESET field bit
#define LA_RESET_BIT ((uint32_t)0x00000004)
/// RESET field position
#define LA_RESET_POS 2
/// STOP field bit
#define LA_STOP_BIT ((uint32_t)0x00000002)
/// STOP field position
#define LA_STOP_POS 1
/// START field bit
#define LA_START_BIT ((uint32_t)0x00000001)
/// START field position
#define LA_START_POS 0
/// RESET field reset value
#define LA_RESET_RST 0x0
/// STOP field reset value
#define LA_STOP_RST 0x0
/// START field reset value
#define LA_START_RST 0x0
/**
* @brief Constructs a value for the CNTRL register given values for its fields
* and writes the value to the register.
*
* @param[in] elt_idx Index of the HW block
* @param[in] reset - The value to use for the reset field.
* @param[in] stop - The value to use for the stop field.
* @param[in] start - The value to use for the start field.
*/
__INLINE void la_cntrl_pack(int elt_idx, uint8_t reset, uint8_t stop, uint8_t start)
{
ASSERT_ERR((((uint32_t)reset << 2) & ~((uint32_t)0x00000004)) == 0);
ASSERT_ERR((((uint32_t)stop << 1) & ~((uint32_t)0x00000002)) == 0);
ASSERT_ERR((((uint32_t)start << 0) & ~((uint32_t)0x00000001)) == 0);
REG_PL_WR(LA_CNTRL_ADDR + elt_idx * REG_LA_OFFSET, ((uint32_t)reset << 2) | ((uint32_t)stop << 1) | ((uint32_t)start << 0));
}
/**
* @brief Sets the reset field of the CNTRL register.
*
* The CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] reset - The value to set the field to.
*/
__INLINE void la_reset_setf(int elt_idx, uint8_t reset)
{
ASSERT_ERR((((uint32_t)reset << 2) & ~((uint32_t)0x00000004)) == 0);
REG_PL_WR(LA_CNTRL_ADDR + elt_idx * REG_LA_OFFSET, (REG_PL_RD(LA_CNTRL_ADDR + elt_idx * REG_LA_OFFSET) & ~((uint32_t)0x00000004)) | ((uint32_t)reset << 2));
}
/**
* @brief Sets the stop field of the CNTRL register.
*
* The CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] stop - The value to set the field to.
*/
__INLINE void la_stop_setf(int elt_idx, uint8_t stop)
{
ASSERT_ERR((((uint32_t)stop << 1) & ~((uint32_t)0x00000002)) == 0);
REG_PL_WR(LA_CNTRL_ADDR + elt_idx * REG_LA_OFFSET, (REG_PL_RD(LA_CNTRL_ADDR + elt_idx * REG_LA_OFFSET) & ~((uint32_t)0x00000002)) | ((uint32_t)stop << 1));
}
/**
* @brief Sets the start field of the CNTRL register.
*
* The CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] start - The value to set the field to.
*/
__INLINE void la_start_setf(int elt_idx, uint8_t start)
{
ASSERT_ERR((((uint32_t)start << 0) & ~((uint32_t)0x00000001)) == 0);
REG_PL_WR(LA_CNTRL_ADDR + elt_idx * REG_LA_OFFSET, (REG_PL_RD(LA_CNTRL_ADDR + elt_idx * REG_LA_OFFSET) & ~((uint32_t)0x00000001)) | ((uint32_t)start << 0));
}
/// @}
/**
* @name STATUS register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23:08 writeaddr 0x0
* 07 error 0
* 01 triggered 0
* 00 started 0
* </pre>
*
* @{
*/
/// Address of the STATUS register
#define LA_STATUS_ADDR 0x10E00010
/// Offset of the STATUS register from the base address
#define LA_STATUS_OFFSET 0x00000010
/// Index of the STATUS register
#define LA_STATUS_INDEX 0x00000004
/// Reset value of the STATUS register
#define LA_STATUS_RESET 0x00000000
/**
* @brief Returns the current value of the STATUS register.
* The STATUS register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the STATUS register.
*/
__INLINE uint32_t la_status_get(int elt_idx)
{
return REG_PL_RD(LA_STATUS_ADDR + elt_idx * REG_LA_OFFSET);
}
/**
* @brief Sets the STATUS register to a value.
* The STATUS register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_status_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_STATUS_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// WRITEADDR field mask
#define LA_WRITEADDR_MASK ((uint32_t)0x00FFFF00)
/// WRITEADDR field LSB position
#define LA_WRITEADDR_LSB 8
/// WRITEADDR field width
#define LA_WRITEADDR_WIDTH ((uint32_t)0x00000010)
/// ERROR field bit
#define LA_ERROR_BIT ((uint32_t)0x00000080)
/// ERROR field position
#define LA_ERROR_POS 7
/// TRIGGERED field bit
#define LA_TRIGGERED_BIT ((uint32_t)0x00000002)
/// TRIGGERED field position
#define LA_TRIGGERED_POS 1
/// STARTED field bit
#define LA_STARTED_BIT ((uint32_t)0x00000001)
/// STARTED field position
#define LA_STARTED_POS 0
/// WRITEADDR field reset value
#define LA_WRITEADDR_RST 0x0
/// ERROR field reset value
#define LA_ERROR_RST 0x0
/// TRIGGERED field reset value
#define LA_TRIGGERED_RST 0x0
/// STARTED field reset value
#define LA_STARTED_RST 0x0
/**
* @brief Unpacks STATUS's fields from current value of the STATUS register.
*
* Reads the STATUS register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[in] elt_idx Index of the HW block
* @param[out] writeaddr - Will be populated with the current value of this field from the register.
* @param[out] error - Will be populated with the current value of this field from the register.
* @param[out] triggered - Will be populated with the current value of this field from the register.
* @param[out] started - Will be populated with the current value of this field from the register.
*/
__INLINE void la_status_unpack(int elt_idx, uint16_t *writeaddr, uint8_t *error, uint8_t *triggered, uint8_t *started)
{
uint32_t localVal = REG_PL_RD(LA_STATUS_ADDR + elt_idx * REG_LA_OFFSET);
*writeaddr = (localVal & ((uint32_t)0x00FFFF00)) >> 8;
*error = (localVal & ((uint32_t)0x00000080)) >> 7;
*triggered = (localVal & ((uint32_t)0x00000002)) >> 1;
*started = (localVal & ((uint32_t)0x00000001)) >> 0;
}
/**
* @brief Returns the current value of the writeaddr field in the STATUS register.
*
* The STATUS register will be read and the writeaddr field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the writeaddr field in the STATUS register.
*/
__INLINE uint16_t la_writeaddr_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_STATUS_ADDR + elt_idx * REG_LA_OFFSET);
return ((localVal & ((uint32_t)0x00FFFF00)) >> 8);
}
/**
* @brief Returns the current value of the error field in the STATUS register.
*
* The STATUS register will be read and the error field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the error field in the STATUS register.
*/
__INLINE uint8_t la_error_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_STATUS_ADDR + elt_idx * REG_LA_OFFSET);
return ((localVal & ((uint32_t)0x00000080)) >> 7);
}
/**
* @brief Returns the current value of the triggered field in the STATUS register.
*
* The STATUS register will be read and the triggered field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the triggered field in the STATUS register.
*/
__INLINE uint8_t la_triggered_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_STATUS_ADDR + elt_idx * REG_LA_OFFSET);
return ((localVal & ((uint32_t)0x00000002)) >> 1);
}
/**
* @brief Returns the current value of the started field in the STATUS register.
*
* The STATUS register will be read and the started field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the started field in the STATUS register.
*/
__INLINE uint8_t la_started_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_STATUS_ADDR + elt_idx * REG_LA_OFFSET);
return ((localVal & ((uint32_t)0x00000001)) >> 0);
}
/// @}
/**
* @name SAMPLING_MASK_LOW register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 sampling_mask_low 0x0
* </pre>
*
* @{
*/
/// Address of the SAMPLING_MASK_LOW register
#define LA_SAMPLING_MASK_LOW_ADDR 0x10E00014
/// Offset of the SAMPLING_MASK_LOW register from the base address
#define LA_SAMPLING_MASK_LOW_OFFSET 0x00000014
/// Index of the SAMPLING_MASK_LOW register
#define LA_SAMPLING_MASK_LOW_INDEX 0x00000005
/// Reset value of the SAMPLING_MASK_LOW register
#define LA_SAMPLING_MASK_LOW_RESET 0x00000000
/**
* @brief Returns the current value of the SAMPLING_MASK_LOW register.
* The SAMPLING_MASK_LOW register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the SAMPLING_MASK_LOW register.
*/
__INLINE uint32_t la_sampling_mask_low_get(int elt_idx)
{
return REG_PL_RD(LA_SAMPLING_MASK_LOW_ADDR + elt_idx * REG_LA_OFFSET);
}
/**
* @brief Sets the SAMPLING_MASK_LOW register to a value.
* The SAMPLING_MASK_LOW register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_sampling_mask_low_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_SAMPLING_MASK_LOW_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// SAMPLING_MASK_LOW field mask
#define LA_SAMPLING_MASK_LOW_MASK ((uint32_t)0xFFFFFFFF)
/// SAMPLING_MASK_LOW field LSB position
#define LA_SAMPLING_MASK_LOW_LSB 0
/// SAMPLING_MASK_LOW field width
#define LA_SAMPLING_MASK_LOW_WIDTH ((uint32_t)0x00000020)
/// SAMPLING_MASK_LOW field reset value
#define LA_SAMPLING_MASK_LOW_RST 0x0
/**
* @brief Returns the current value of the sampling_mask_low field in the SAMPLING_MASK_LOW register.
*
* The SAMPLING_MASK_LOW register will be read and the sampling_mask_low field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the sampling_mask_low field in the SAMPLING_MASK_LOW register.
*/
__INLINE uint32_t la_sampling_mask_low_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_SAMPLING_MASK_LOW_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the sampling_mask_low field of the SAMPLING_MASK_LOW register.
*
* The SAMPLING_MASK_LOW register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] samplingmasklow - The value to set the field to.
*/
__INLINE void la_sampling_mask_low_setf(int elt_idx, uint32_t samplingmasklow)
{
ASSERT_ERR((((uint32_t)samplingmasklow << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(LA_SAMPLING_MASK_LOW_ADDR + elt_idx * REG_LA_OFFSET, (uint32_t)samplingmasklow << 0);
}
/// @}
/**
* @name SAMPLING_MASK_MED register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 sampling_mask_med 0x0
* </pre>
*
* @{
*/
/// Address of the SAMPLING_MASK_MED register
#define LA_SAMPLING_MASK_MED_ADDR 0x10E00018
/// Offset of the SAMPLING_MASK_MED register from the base address
#define LA_SAMPLING_MASK_MED_OFFSET 0x00000018
/// Index of the SAMPLING_MASK_MED register
#define LA_SAMPLING_MASK_MED_INDEX 0x00000006
/// Reset value of the SAMPLING_MASK_MED register
#define LA_SAMPLING_MASK_MED_RESET 0x00000000
/**
* @brief Returns the current value of the SAMPLING_MASK_MED register.
* The SAMPLING_MASK_MED register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the SAMPLING_MASK_MED register.
*/
__INLINE uint32_t la_sampling_mask_med_get(int elt_idx)
{
return REG_PL_RD(LA_SAMPLING_MASK_MED_ADDR + elt_idx * REG_LA_OFFSET);
}
/**
* @brief Sets the SAMPLING_MASK_MED register to a value.
* The SAMPLING_MASK_MED register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_sampling_mask_med_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_SAMPLING_MASK_MED_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// SAMPLING_MASK_MED field mask
#define LA_SAMPLING_MASK_MED_MASK ((uint32_t)0xFFFFFFFF)
/// SAMPLING_MASK_MED field LSB position
#define LA_SAMPLING_MASK_MED_LSB 0
/// SAMPLING_MASK_MED field width
#define LA_SAMPLING_MASK_MED_WIDTH ((uint32_t)0x00000020)
/// SAMPLING_MASK_MED field reset value
#define LA_SAMPLING_MASK_MED_RST 0x0
/**
* @brief Returns the current value of the sampling_mask_med field in the SAMPLING_MASK_MED register.
*
* The SAMPLING_MASK_MED register will be read and the sampling_mask_med field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the sampling_mask_med field in the SAMPLING_MASK_MED register.
*/
__INLINE uint32_t la_sampling_mask_med_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_SAMPLING_MASK_MED_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the sampling_mask_med field of the SAMPLING_MASK_MED register.
*
* The SAMPLING_MASK_MED register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] samplingmaskmed - The value to set the field to.
*/
__INLINE void la_sampling_mask_med_setf(int elt_idx, uint32_t samplingmaskmed)
{
ASSERT_ERR((((uint32_t)samplingmaskmed << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(LA_SAMPLING_MASK_MED_ADDR + elt_idx * REG_LA_OFFSET, (uint32_t)samplingmaskmed << 0);
}
/// @}
/**
* @name SAMPLING_MASK_HIGH register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 sampling_mask_high 0x0
* </pre>
*
* @{
*/
/// Address of the SAMPLING_MASK_HIGH register
#define LA_SAMPLING_MASK_HIGH_ADDR 0x10E0001C
/// Offset of the SAMPLING_MASK_HIGH register from the base address
#define LA_SAMPLING_MASK_HIGH_OFFSET 0x0000001C
/// Index of the SAMPLING_MASK_HIGH register
#define LA_SAMPLING_MASK_HIGH_INDEX 0x00000007
/// Reset value of the SAMPLING_MASK_HIGH register
#define LA_SAMPLING_MASK_HIGH_RESET 0x00000000
/**
* @brief Returns the current value of the SAMPLING_MASK_HIGH register.
* The SAMPLING_MASK_HIGH register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the SAMPLING_MASK_HIGH register.
*/
__INLINE uint32_t la_sampling_mask_high_get(int elt_idx)
{
return REG_PL_RD(LA_SAMPLING_MASK_HIGH_ADDR + elt_idx * REG_LA_OFFSET);
}
/**
* @brief Sets the SAMPLING_MASK_HIGH register to a value.
* The SAMPLING_MASK_HIGH register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_sampling_mask_high_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_SAMPLING_MASK_HIGH_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// SAMPLING_MASK_HIGH field mask
#define LA_SAMPLING_MASK_HIGH_MASK ((uint32_t)0xFFFFFFFF)
/// SAMPLING_MASK_HIGH field LSB position
#define LA_SAMPLING_MASK_HIGH_LSB 0
/// SAMPLING_MASK_HIGH field width
#define LA_SAMPLING_MASK_HIGH_WIDTH ((uint32_t)0x00000020)
/// SAMPLING_MASK_HIGH field reset value
#define LA_SAMPLING_MASK_HIGH_RST 0x0
/**
* @brief Returns the current value of the sampling_mask_high field in the SAMPLING_MASK_HIGH register.
*
* The SAMPLING_MASK_HIGH register will be read and the sampling_mask_high field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the sampling_mask_high field in the SAMPLING_MASK_HIGH register.
*/
__INLINE uint32_t la_sampling_mask_high_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_SAMPLING_MASK_HIGH_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the sampling_mask_high field of the SAMPLING_MASK_HIGH register.
*
* The SAMPLING_MASK_HIGH register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] samplingmaskhigh - The value to set the field to.
*/
__INLINE void la_sampling_mask_high_setf(int elt_idx, uint32_t samplingmaskhigh)
{
ASSERT_ERR((((uint32_t)samplingmaskhigh << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(LA_SAMPLING_MASK_HIGH_ADDR + elt_idx * REG_LA_OFFSET, (uint32_t)samplingmaskhigh << 0);
}
/// @}
/**
* @name TRIGGER_MASK_LOW register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 trigger_mask_med 0x0
* </pre>
*
* @{
*/
/// Address of the TRIGGER_MASK_LOW register
#define LA_TRIGGER_MASK_LOW_ADDR 0x10E00020
/// Offset of the TRIGGER_MASK_LOW register from the base address
#define LA_TRIGGER_MASK_LOW_OFFSET 0x00000020
/// Index of the TRIGGER_MASK_LOW register
#define LA_TRIGGER_MASK_LOW_INDEX 0x00000008
/// Reset value of the TRIGGER_MASK_LOW register
#define LA_TRIGGER_MASK_LOW_RESET 0x00000000
/**
* @brief Returns the current value of the TRIGGER_MASK_LOW register.
* The TRIGGER_MASK_LOW register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the TRIGGER_MASK_LOW register.
*/
__INLINE uint32_t la_trigger_mask_low_get(int elt_idx)
{
return REG_PL_RD(LA_TRIGGER_MASK_LOW_ADDR + elt_idx * REG_LA_OFFSET);
}
/**
* @brief Sets the TRIGGER_MASK_LOW register to a value.
* The TRIGGER_MASK_LOW register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_trigger_mask_low_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_TRIGGER_MASK_LOW_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// TRIGGER_MASK_MED field mask
#define LA_TRIGGER_MASK_MED_MASK ((uint32_t)0xFFFFFFFF)
/// TRIGGER_MASK_MED field LSB position
#define LA_TRIGGER_MASK_MED_LSB 0
/// TRIGGER_MASK_MED field width
#define LA_TRIGGER_MASK_MED_WIDTH ((uint32_t)0x00000020)
/// TRIGGER_MASK_MED field reset value
#define LA_TRIGGER_MASK_MED_RST 0x0
/**
* @brief Returns the current value of the trigger_mask_med field in the TRIGGER_MASK_LOW register.
*
* The TRIGGER_MASK_LOW register will be read and the trigger_mask_med field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the trigger_mask_med field in the TRIGGER_MASK_LOW register.
*/
__INLINE uint32_t la_trigger_mask_med_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_TRIGGER_MASK_LOW_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the trigger_mask_med field of the TRIGGER_MASK_LOW register.
*
* The TRIGGER_MASK_LOW register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] triggermaskmed - The value to set the field to.
*/
__INLINE void la_trigger_mask_med_setf(int elt_idx, uint32_t triggermaskmed)
{
ASSERT_ERR((((uint32_t)triggermaskmed << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(LA_TRIGGER_MASK_LOW_ADDR + elt_idx * REG_LA_OFFSET, (uint32_t)triggermaskmed << 0);
}
/// @}
/**
* @name TRIGGER_MASK_MED register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 trigger_mask_low 0x0
* </pre>
*
* @{
*/
/// Address of the TRIGGER_MASK_MED register
#define LA_TRIGGER_MASK_MED_ADDR 0x10E00024
/// Offset of the TRIGGER_MASK_MED register from the base address
#define LA_TRIGGER_MASK_MED_OFFSET 0x00000024
/// Index of the TRIGGER_MASK_MED register
#define LA_TRIGGER_MASK_MED_INDEX 0x00000009
/// Reset value of the TRIGGER_MASK_MED register
#define LA_TRIGGER_MASK_MED_RESET 0x00000000
/**
* @brief Returns the current value of the TRIGGER_MASK_MED register.
* The TRIGGER_MASK_MED register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the TRIGGER_MASK_MED register.
*/
__INLINE uint32_t la_trigger_mask_med_get(int elt_idx)
{
return REG_PL_RD(LA_TRIGGER_MASK_MED_ADDR + elt_idx * REG_LA_OFFSET);
}
/**
* @brief Sets the TRIGGER_MASK_MED register to a value.
* The TRIGGER_MASK_MED register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_trigger_mask_med_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_TRIGGER_MASK_MED_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// TRIGGER_MASK_LOW field mask
#define LA_TRIGGER_MASK_LOW_MASK ((uint32_t)0xFFFFFFFF)
/// TRIGGER_MASK_LOW field LSB position
#define LA_TRIGGER_MASK_LOW_LSB 0
/// TRIGGER_MASK_LOW field width
#define LA_TRIGGER_MASK_LOW_WIDTH ((uint32_t)0x00000020)
/// TRIGGER_MASK_LOW field reset value
#define LA_TRIGGER_MASK_LOW_RST 0x0
/**
* @brief Returns the current value of the trigger_mask_low field in the TRIGGER_MASK_MED register.
*
* The TRIGGER_MASK_MED register will be read and the trigger_mask_low field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the trigger_mask_low field in the TRIGGER_MASK_MED register.
*/
__INLINE uint32_t la_trigger_mask_low_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_TRIGGER_MASK_MED_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the trigger_mask_low field of the TRIGGER_MASK_MED register.
*
* The TRIGGER_MASK_MED register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] triggermasklow - The value to set the field to.
*/
__INLINE void la_trigger_mask_low_setf(int elt_idx, uint32_t triggermasklow)
{
ASSERT_ERR((((uint32_t)triggermasklow << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(LA_TRIGGER_MASK_MED_ADDR + elt_idx * REG_LA_OFFSET, (uint32_t)triggermasklow << 0);
}
/// @}
/**
* @name TRIGGER_MASK_HIGH register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 trigger_mask_high 0x0
* </pre>
*
* @{
*/
/// Address of the TRIGGER_MASK_HIGH register
#define LA_TRIGGER_MASK_HIGH_ADDR 0x10E00028
/// Offset of the TRIGGER_MASK_HIGH register from the base address
#define LA_TRIGGER_MASK_HIGH_OFFSET 0x00000028
/// Index of the TRIGGER_MASK_HIGH register
#define LA_TRIGGER_MASK_HIGH_INDEX 0x0000000A
/// Reset value of the TRIGGER_MASK_HIGH register
#define LA_TRIGGER_MASK_HIGH_RESET 0x00000000
/**
* @brief Returns the current value of the TRIGGER_MASK_HIGH register.
* The TRIGGER_MASK_HIGH register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the TRIGGER_MASK_HIGH register.
*/
__INLINE uint32_t la_trigger_mask_high_get(int elt_idx)
{
return REG_PL_RD(LA_TRIGGER_MASK_HIGH_ADDR + elt_idx * REG_LA_OFFSET);
}
/**
* @brief Sets the TRIGGER_MASK_HIGH register to a value.
* The TRIGGER_MASK_HIGH register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_trigger_mask_high_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_TRIGGER_MASK_HIGH_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// TRIGGER_MASK_HIGH field mask
#define LA_TRIGGER_MASK_HIGH_MASK ((uint32_t)0xFFFFFFFF)
/// TRIGGER_MASK_HIGH field LSB position
#define LA_TRIGGER_MASK_HIGH_LSB 0
/// TRIGGER_MASK_HIGH field width
#define LA_TRIGGER_MASK_HIGH_WIDTH ((uint32_t)0x00000020)
/// TRIGGER_MASK_HIGH field reset value
#define LA_TRIGGER_MASK_HIGH_RST 0x0
/**
* @brief Returns the current value of the trigger_mask_high field in the TRIGGER_MASK_HIGH register.
*
* The TRIGGER_MASK_HIGH register will be read and the trigger_mask_high field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the trigger_mask_high field in the TRIGGER_MASK_HIGH register.
*/
__INLINE uint32_t la_trigger_mask_high_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_TRIGGER_MASK_HIGH_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the trigger_mask_high field of the TRIGGER_MASK_HIGH register.
*
* The TRIGGER_MASK_HIGH register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] triggermaskhigh - The value to set the field to.
*/
__INLINE void la_trigger_mask_high_setf(int elt_idx, uint32_t triggermaskhigh)
{
ASSERT_ERR((((uint32_t)triggermaskhigh << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(LA_TRIGGER_MASK_HIGH_ADDR + elt_idx * REG_LA_OFFSET, (uint32_t)triggermaskhigh << 0);
}
/// @}
/**
* @name TRIGGER_VALUE_LOW register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 trigger_value_low 0x0
* </pre>
*
* @{
*/
/// Address of the TRIGGER_VALUE_LOW register
#define LA_TRIGGER_VALUE_LOW_ADDR 0x10E0002C
/// Offset of the TRIGGER_VALUE_LOW register from the base address
#define LA_TRIGGER_VALUE_LOW_OFFSET 0x0000002C
/// Index of the TRIGGER_VALUE_LOW register
#define LA_TRIGGER_VALUE_LOW_INDEX 0x0000000B
/// Reset value of the TRIGGER_VALUE_LOW register
#define LA_TRIGGER_VALUE_LOW_RESET 0x00000000
/**
* @brief Returns the current value of the TRIGGER_VALUE_LOW register.
* The TRIGGER_VALUE_LOW register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the TRIGGER_VALUE_LOW register.
*/
__INLINE uint32_t la_trigger_value_low_get(int elt_idx)
{
return REG_PL_RD(LA_TRIGGER_VALUE_LOW_ADDR + elt_idx * REG_LA_OFFSET);
}
/**
* @brief Sets the TRIGGER_VALUE_LOW register to a value.
* The TRIGGER_VALUE_LOW register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_trigger_value_low_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_TRIGGER_VALUE_LOW_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// TRIGGER_VALUE_LOW field mask
#define LA_TRIGGER_VALUE_LOW_MASK ((uint32_t)0xFFFFFFFF)
/// TRIGGER_VALUE_LOW field LSB position
#define LA_TRIGGER_VALUE_LOW_LSB 0
/// TRIGGER_VALUE_LOW field width
#define LA_TRIGGER_VALUE_LOW_WIDTH ((uint32_t)0x00000020)
/// TRIGGER_VALUE_LOW field reset value
#define LA_TRIGGER_VALUE_LOW_RST 0x0
/**
* @brief Returns the current value of the trigger_value_low field in the TRIGGER_VALUE_LOW register.
*
* The TRIGGER_VALUE_LOW register will be read and the trigger_value_low field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the trigger_value_low field in the TRIGGER_VALUE_LOW register.
*/
__INLINE uint32_t la_trigger_value_low_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_TRIGGER_VALUE_LOW_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the trigger_value_low field of the TRIGGER_VALUE_LOW register.
*
* The TRIGGER_VALUE_LOW register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] triggervaluelow - The value to set the field to.
*/
__INLINE void la_trigger_value_low_setf(int elt_idx, uint32_t triggervaluelow)
{
ASSERT_ERR((((uint32_t)triggervaluelow << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(LA_TRIGGER_VALUE_LOW_ADDR + elt_idx * REG_LA_OFFSET, (uint32_t)triggervaluelow << 0);
}
/// @}
/**
* @name TRIGGER_VALUE_MED register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 trigger_value_med 0x0
* </pre>
*
* @{
*/
/// Address of the TRIGGER_VALUE_MED register
#define LA_TRIGGER_VALUE_MED_ADDR 0x10E00030
/// Offset of the TRIGGER_VALUE_MED register from the base address
#define LA_TRIGGER_VALUE_MED_OFFSET 0x00000030
/// Index of the TRIGGER_VALUE_MED register
#define LA_TRIGGER_VALUE_MED_INDEX 0x0000000C
/// Reset value of the TRIGGER_VALUE_MED register
#define LA_TRIGGER_VALUE_MED_RESET 0x00000000
/**
* @brief Returns the current value of the TRIGGER_VALUE_MED register.
* The TRIGGER_VALUE_MED register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the TRIGGER_VALUE_MED register.
*/
__INLINE uint32_t la_trigger_value_med_get(int elt_idx)
{
return REG_PL_RD(LA_TRIGGER_VALUE_MED_ADDR + elt_idx * REG_LA_OFFSET);
}
/**
* @brief Sets the TRIGGER_VALUE_MED register to a value.
* The TRIGGER_VALUE_MED register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_trigger_value_med_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_TRIGGER_VALUE_MED_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// TRIGGER_VALUE_MED field mask
#define LA_TRIGGER_VALUE_MED_MASK ((uint32_t)0xFFFFFFFF)
/// TRIGGER_VALUE_MED field LSB position
#define LA_TRIGGER_VALUE_MED_LSB 0
/// TRIGGER_VALUE_MED field width
#define LA_TRIGGER_VALUE_MED_WIDTH ((uint32_t)0x00000020)
/// TRIGGER_VALUE_MED field reset value
#define LA_TRIGGER_VALUE_MED_RST 0x0
/**
* @brief Returns the current value of the trigger_value_med field in the TRIGGER_VALUE_MED register.
*
* The TRIGGER_VALUE_MED register will be read and the trigger_value_med field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the trigger_value_med field in the TRIGGER_VALUE_MED register.
*/
__INLINE uint32_t la_trigger_value_med_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_TRIGGER_VALUE_MED_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the trigger_value_med field of the TRIGGER_VALUE_MED register.
*
* The TRIGGER_VALUE_MED register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] triggervaluemed - The value to set the field to.
*/
__INLINE void la_trigger_value_med_setf(int elt_idx, uint32_t triggervaluemed)
{
ASSERT_ERR((((uint32_t)triggervaluemed << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(LA_TRIGGER_VALUE_MED_ADDR + elt_idx * REG_LA_OFFSET, (uint32_t)triggervaluemed << 0);
}
/// @}
/**
* @name TRIGGER_VALUE_HIGH register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 trigger_value_high 0x0
* </pre>
*
* @{
*/
/// Address of the TRIGGER_VALUE_HIGH register
#define LA_TRIGGER_VALUE_HIGH_ADDR 0x10E00034
/// Offset of the TRIGGER_VALUE_HIGH register from the base address
#define LA_TRIGGER_VALUE_HIGH_OFFSET 0x00000034
/// Index of the TRIGGER_VALUE_HIGH register
#define LA_TRIGGER_VALUE_HIGH_INDEX 0x0000000D
/// Reset value of the TRIGGER_VALUE_HIGH register
#define LA_TRIGGER_VALUE_HIGH_RESET 0x00000000
/**
* @brief Returns the current value of the TRIGGER_VALUE_HIGH register.
* The TRIGGER_VALUE_HIGH register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the TRIGGER_VALUE_HIGH register.
*/
__INLINE uint32_t la_trigger_value_high_get(int elt_idx)
{
return REG_PL_RD(LA_TRIGGER_VALUE_HIGH_ADDR + elt_idx * REG_LA_OFFSET);
}
/**
* @brief Sets the TRIGGER_VALUE_HIGH register to a value.
* The TRIGGER_VALUE_HIGH register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_trigger_value_high_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_TRIGGER_VALUE_HIGH_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// TRIGGER_VALUE_HIGH field mask
#define LA_TRIGGER_VALUE_HIGH_MASK ((uint32_t)0xFFFFFFFF)
/// TRIGGER_VALUE_HIGH field LSB position
#define LA_TRIGGER_VALUE_HIGH_LSB 0
/// TRIGGER_VALUE_HIGH field width
#define LA_TRIGGER_VALUE_HIGH_WIDTH ((uint32_t)0x00000020)
/// TRIGGER_VALUE_HIGH field reset value
#define LA_TRIGGER_VALUE_HIGH_RST 0x0
/**
* @brief Returns the current value of the trigger_value_high field in the TRIGGER_VALUE_HIGH register.
*
* The TRIGGER_VALUE_HIGH register will be read and the trigger_value_high field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the trigger_value_high field in the TRIGGER_VALUE_HIGH register.
*/
__INLINE uint32_t la_trigger_value_high_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_TRIGGER_VALUE_HIGH_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the trigger_value_high field of the TRIGGER_VALUE_HIGH register.
*
* The TRIGGER_VALUE_HIGH register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] triggervaluehigh - The value to set the field to.
*/
__INLINE void la_trigger_value_high_setf(int elt_idx, uint32_t triggervaluehigh)
{
ASSERT_ERR((((uint32_t)triggervaluehigh << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(LA_TRIGGER_VALUE_HIGH_ADDR + elt_idx * REG_LA_OFFSET, (uint32_t)triggervaluehigh << 0);
}
/// @}
/**
* @name TRIGGER_POINT register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 trigger_point 0x0
* </pre>
*
* @{
*/
/// Address of the TRIGGER_POINT register
#define LA_TRIGGER_POINT_ADDR 0x10E00038
/// Offset of the TRIGGER_POINT register from the base address
#define LA_TRIGGER_POINT_OFFSET 0x00000038
/// Index of the TRIGGER_POINT register
#define LA_TRIGGER_POINT_INDEX 0x0000000E
/// Reset value of the TRIGGER_POINT register
#define LA_TRIGGER_POINT_RESET 0x00000000
/**
* @brief Returns the current value of the TRIGGER_POINT register.
* The TRIGGER_POINT register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the TRIGGER_POINT register.
*/
__INLINE uint32_t la_trigger_point_get(int elt_idx)
{
return REG_PL_RD(LA_TRIGGER_POINT_ADDR + elt_idx * REG_LA_OFFSET);
}
/**
* @brief Sets the TRIGGER_POINT register to a value.
* The TRIGGER_POINT register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_trigger_point_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_TRIGGER_POINT_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// TRIGGER_POINT field mask
#define LA_TRIGGER_POINT_MASK ((uint32_t)0x0000FFFF)
/// TRIGGER_POINT field LSB position
#define LA_TRIGGER_POINT_LSB 0
/// TRIGGER_POINT field width
#define LA_TRIGGER_POINT_WIDTH ((uint32_t)0x00000010)
/// TRIGGER_POINT field reset value
#define LA_TRIGGER_POINT_RST 0x0
/**
* @brief Returns the current value of the trigger_point field in the TRIGGER_POINT register.
*
* The TRIGGER_POINT register will be read and the trigger_point field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the trigger_point field in the TRIGGER_POINT register.
*/
__INLINE uint16_t la_trigger_point_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_TRIGGER_POINT_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0x0000FFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the trigger_point field of the TRIGGER_POINT register.
*
* The TRIGGER_POINT register will be read, modified to contain the new field value, and written.
*
* @param[in] elt_idx Index of the HW block
* @param[in] triggerpoint - The value to set the field to.
*/
__INLINE void la_trigger_point_setf(int elt_idx, uint16_t triggerpoint)
{
ASSERT_ERR((((uint32_t)triggerpoint << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(LA_TRIGGER_POINT_ADDR + elt_idx * REG_LA_OFFSET, (uint32_t)triggerpoint << 0);
}
/// @}
/**
* @name FIRSTSAMPLE register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 firstsample 0x0
* </pre>
*
* @{
*/
/// Address of the FIRSTSAMPLE register
#define LA_FIRSTSAMPLE_ADDR 0x10E0003C
/// Offset of the FIRSTSAMPLE register from the base address
#define LA_FIRSTSAMPLE_OFFSET 0x0000003C
/// Index of the FIRSTSAMPLE register
#define LA_FIRSTSAMPLE_INDEX 0x0000000F
/// Reset value of the FIRSTSAMPLE register
#define LA_FIRSTSAMPLE_RESET 0x00000000
/**
* @brief Returns the current value of the FIRSTSAMPLE register.
* The FIRSTSAMPLE register will be read and its value returned.
* @param[in] elt_idx Index of the HW block
* @return The current value of the FIRSTSAMPLE register.
*/
__INLINE uint32_t la_firstsample_get(int elt_idx)
{
return REG_PL_RD(LA_FIRSTSAMPLE_ADDR + elt_idx * REG_LA_OFFSET);
}
/**
* @brief Sets the FIRSTSAMPLE register to a value.
* The FIRSTSAMPLE register will be written.
* @param[in] elt_idx Index of the HW block
* @param value - The value to write.
*/
__INLINE void la_firstsample_set(int elt_idx, uint32_t value)
{
REG_PL_WR(LA_FIRSTSAMPLE_ADDR + elt_idx * REG_LA_OFFSET, value);
}
// field definitions
/// FIRSTSAMPLE field mask
#define LA_FIRSTSAMPLE_MASK ((uint32_t)0x0000FFFF)
/// FIRSTSAMPLE field LSB position
#define LA_FIRSTSAMPLE_LSB 0
/// FIRSTSAMPLE field width
#define LA_FIRSTSAMPLE_WIDTH ((uint32_t)0x00000010)
/// FIRSTSAMPLE field reset value
#define LA_FIRSTSAMPLE_RST 0x0
/**
* @brief Returns the current value of the firstsample field in the FIRSTSAMPLE register.
*
* The FIRSTSAMPLE register will be read and the firstsample field's value will be returned.
*
* @param[in] elt_idx Index of the HW block
* @return The current value of the firstsample field in the FIRSTSAMPLE register.
*/
__INLINE uint16_t la_firstsample_getf(int elt_idx)
{
uint32_t localVal = REG_PL_RD(LA_FIRSTSAMPLE_ADDR + elt_idx * REG_LA_OFFSET);
ASSERT_ERR((localVal & ~((uint32_t)0x0000FFFF)) == 0);
return (localVal >> 0);
}
/// @}
#endif // _REG_LA_H_
/// @}
Raw
reg_mac_core.h
/**
* @file reg_mac_core.h
* @brief Definitions of the NXMAC HW block registers and register access functions.
*
* @defgroup REG_MAC_CORE REG_MAC_CORE
* @ingroup REG
* @{
*
* @brief Definitions of the NXMAC HW block registers and register access functions.
*/
#ifndef _REG_MAC_CORE_H_
#define _REG_MAC_CORE_H_
#include "co_int.h"
#include "_reg_mac_core.h"
#include "compiler.h"
#include "arch.h"
#include "reg_access.h"
/*lint -e91 */
/** @brief Number of registers in the REG_MAC_CORE peripheral.
*/
#define REG_MAC_CORE_COUNT 344
/** @brief Decoding mask of the REG_MAC_CORE peripheral registers from the CPU point of view.
*/
#define REG_MAC_CORE_DECODING_MASK 0x000007FF
/**
* @name SIGNATURE register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 signature 0x0
* </pre>
*
* @{
*/
/// Address of the SIGNATURE register
#define NXMAC_SIGNATURE_ADDR 0xC0000000
/// Offset of the SIGNATURE register from the base address
#define NXMAC_SIGNATURE_OFFSET 0x00000000
/// Index of the SIGNATURE register
#define NXMAC_SIGNATURE_INDEX 0x00000000
/// Reset value of the SIGNATURE register
#define NXMAC_SIGNATURE_RESET 0x00000000
/**
* @brief Returns the current value of the SIGNATURE register.
* The SIGNATURE register will be read and its value returned.
* @return The current value of the SIGNATURE register.
*/
__INLINE uint32_t nxmac_signature_get(void)
{
return REG_PL_RD(NXMAC_SIGNATURE_ADDR);
}
// field definitions
/// SIGNATURE field mask
#define NXMAC_SIGNATURE_MASK ((uint32_t)0xFFFFFFFF)
/// SIGNATURE field LSB position
#define NXMAC_SIGNATURE_LSB 0
/// SIGNATURE field width
#define NXMAC_SIGNATURE_WIDTH ((uint32_t)0x00000020)
/// SIGNATURE field reset value
#define NXMAC_SIGNATURE_RST 0x0
/**
* @brief Returns the current value of the signature field in the SIGNATURE register.
*
* The SIGNATURE register will be read and the signature field's value will be returned.
*
* @return The current value of the signature field in the SIGNATURE register.
*/
__INLINE uint32_t nxmac_signature_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_SIGNATURE_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/// @}
/**
* @name VERSION_1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 19 muMIMOTx 0
* 18 bfmer 0
* 17 bfmee 0
* 16 mac80211MHFormat 0
* 14 coex 0
* 13 wapi 0
* 12 tpc 1
* 11 vht 1
* 10 ht 1
* 08 rce 0
* 07 ccmp 0
* 06 tkip 0
* 05 wep 0
* 04 security 0
* 03 sme 0
* 02 hcca 0
* 01 edca 1
* 00 qos 1
* </pre>
*
* @{
*/
/// Address of the VERSION_1 register
#define NXMAC_VERSION_1_ADDR 0xC0000004
/// Offset of the VERSION_1 register from the base address
#define NXMAC_VERSION_1_OFFSET 0x00000004
/// Index of the VERSION_1 register
#define NXMAC_VERSION_1_INDEX 0x00000001
/// Reset value of the VERSION_1 register
#define NXMAC_VERSION_1_RESET 0x00001C03
/**
* @brief Returns the current value of the VERSION_1 register.
* The VERSION_1 register will be read and its value returned.
* @return The current value of the VERSION_1 register.
*/
__INLINE uint32_t nxmac_version_1_get(void)
{
return REG_PL_RD(NXMAC_VERSION_1_ADDR);
}
// field definitions
/// MU_MIMO_TX field bit
#define NXMAC_MU_MIMO_TX_BIT ((uint32_t)0x00080000)
/// MU_MIMO_TX field position
#define NXMAC_MU_MIMO_TX_POS 19
/// BFMER field bit
#define NXMAC_BFMER_BIT ((uint32_t)0x00040000)
/// BFMER field position
#define NXMAC_BFMER_POS 18
/// BFMEE field bit
#define NXMAC_BFMEE_BIT ((uint32_t)0x00020000)
/// BFMEE field position
#define NXMAC_BFMEE_POS 17
/// MAC_80211MH_FORMAT field bit
#define NXMAC_MAC_80211MH_FORMAT_BIT ((uint32_t)0x00010000)
/// MAC_80211MH_FORMAT field position
#define NXMAC_MAC_80211MH_FORMAT_POS 16
/// COEX field bit
#define NXMAC_COEX_BIT ((uint32_t)0x00004000)
/// COEX field position
#define NXMAC_COEX_POS 14
/// WAPI field bit
#define NXMAC_WAPI_BIT ((uint32_t)0x00002000)
/// WAPI field position
#define NXMAC_WAPI_POS 13
/// TPC field bit
#define NXMAC_TPC_BIT ((uint32_t)0x00001000)
/// TPC field position
#define NXMAC_TPC_POS 12
/// VHT field bit
#define NXMAC_VHT_BIT ((uint32_t)0x00000800)
/// VHT field position
#define NXMAC_VHT_POS 11
/// HT field bit
#define NXMAC_HT_BIT ((uint32_t)0x00000400)
/// HT field position
#define NXMAC_HT_POS 10
/// RCE field bit
#define NXMAC_RCE_BIT ((uint32_t)0x00000100)
/// RCE field position
#define NXMAC_RCE_POS 8
/// CCMP field bit
#define NXMAC_CCMP_BIT ((uint32_t)0x00000080)
/// CCMP field position
#define NXMAC_CCMP_POS 7
/// TKIP field bit
#define NXMAC_TKIP_BIT ((uint32_t)0x00000040)
/// TKIP field position
#define NXMAC_TKIP_POS 6
/// WEP field bit
#define NXMAC_WEP_BIT ((uint32_t)0x00000020)
/// WEP field position
#define NXMAC_WEP_POS 5
/// SECURITY field bit
#define NXMAC_SECURITY_BIT ((uint32_t)0x00000010)
/// SECURITY field position
#define NXMAC_SECURITY_POS 4
/// SME field bit
#define NXMAC_SME_BIT ((uint32_t)0x00000008)
/// SME field position
#define NXMAC_SME_POS 3
/// HCCA field bit
#define NXMAC_HCCA_BIT ((uint32_t)0x00000004)
/// HCCA field position
#define NXMAC_HCCA_POS 2
/// EDCA field bit
#define NXMAC_EDCA_BIT ((uint32_t)0x00000002)
/// EDCA field position
#define NXMAC_EDCA_POS 1
/// QOS field bit
#define NXMAC_QOS_BIT ((uint32_t)0x00000001)
/// QOS field position
#define NXMAC_QOS_POS 0
/// MU_MIMO_TX field reset value
#define NXMAC_MU_MIMO_TX_RST 0x0
/// BFMER field reset value
#define NXMAC_BFMER_RST 0x0
/// BFMEE field reset value
#define NXMAC_BFMEE_RST 0x0
/// MAC_80211MH_FORMAT field reset value
#define NXMAC_MAC_80211MH_FORMAT_RST 0x0
/// COEX field reset value
#define NXMAC_COEX_RST 0x0
/// WAPI field reset value
#define NXMAC_WAPI_RST 0x0
/// TPC field reset value
#define NXMAC_TPC_RST 0x1
/// VHT field reset value
#define NXMAC_VHT_RST 0x1
/// HT field reset value
#define NXMAC_HT_RST 0x1
/// RCE field reset value
#define NXMAC_RCE_RST 0x0
/// CCMP field reset value
#define NXMAC_CCMP_RST 0x0
/// TKIP field reset value
#define NXMAC_TKIP_RST 0x0
/// WEP field reset value
#define NXMAC_WEP_RST 0x0
/// SECURITY field reset value
#define NXMAC_SECURITY_RST 0x0
/// SME field reset value
#define NXMAC_SME_RST 0x0
/// HCCA field reset value
#define NXMAC_HCCA_RST 0x0
/// EDCA field reset value
#define NXMAC_EDCA_RST 0x1
/// QOS field reset value
#define NXMAC_QOS_RST 0x1
/**
* @brief Unpacks VERSION_1's fields from current value of the VERSION_1 register.
*
* Reads the VERSION_1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] mumimotx - Will be populated with the current value of this field from the register.
* @param[out] bfmer - Will be populated with the current value of this field from the register.
* @param[out] bfmee - Will be populated with the current value of this field from the register.
* @param[out] mac80211mhformat - Will be populated with the current value of this field from the register.
* @param[out] coex - Will be populated with the current value of this field from the register.
* @param[out] wapi - Will be populated with the current value of this field from the register.
* @param[out] tpc - Will be populated with the current value of this field from the register.
* @param[out] vht - Will be populated with the current value of this field from the register.
* @param[out] ht - Will be populated with the current value of this field from the register.
* @param[out] rce - Will be populated with the current value of this field from the register.
* @param[out] ccmp - Will be populated with the current value of this field from the register.
* @param[out] tkip - Will be populated with the current value of this field from the register.
* @param[out] wep - Will be populated with the current value of this field from the register.
* @param[out] security - Will be populated with the current value of this field from the register.
* @param[out] sme - Will be populated with the current value of this field from the register.
* @param[out] hcca - Will be populated with the current value of this field from the register.
* @param[out] edca - Will be populated with the current value of this field from the register.
* @param[out] qos - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_version_1_unpack(uint8_t *mumimotx, uint8_t *bfmer, uint8_t *bfmee, uint8_t *mac80211mhformat, uint8_t *coex, uint8_t *wapi, uint8_t *tpc, uint8_t *vht, uint8_t *ht, uint8_t *rce, uint8_t *ccmp, uint8_t *tkip, uint8_t *wep, uint8_t *security, uint8_t *sme, uint8_t *hcca, uint8_t *edca, uint8_t *qos)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
*mumimotx = (localVal & ((uint32_t)0x00080000)) >> 19;
*bfmer = (localVal & ((uint32_t)0x00040000)) >> 18;
*bfmee = (localVal & ((uint32_t)0x00020000)) >> 17;
*mac80211mhformat = (localVal & ((uint32_t)0x00010000)) >> 16;
*coex = (localVal & ((uint32_t)0x00004000)) >> 14;
*wapi = (localVal & ((uint32_t)0x00002000)) >> 13;
*tpc = (localVal & ((uint32_t)0x00001000)) >> 12;
*vht = (localVal & ((uint32_t)0x00000800)) >> 11;
*ht = (localVal & ((uint32_t)0x00000400)) >> 10;
*rce = (localVal & ((uint32_t)0x00000100)) >> 8;
*ccmp = (localVal & ((uint32_t)0x00000080)) >> 7;
*tkip = (localVal & ((uint32_t)0x00000040)) >> 6;
*wep = (localVal & ((uint32_t)0x00000020)) >> 5;
*security = (localVal & ((uint32_t)0x00000010)) >> 4;
*sme = (localVal & ((uint32_t)0x00000008)) >> 3;
*hcca = (localVal & ((uint32_t)0x00000004)) >> 2;
*edca = (localVal & ((uint32_t)0x00000002)) >> 1;
*qos = (localVal & ((uint32_t)0x00000001)) >> 0;
}
/**
* @brief Returns the current value of the muMIMOTx field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the muMIMOTx field's value will be returned.
*
* @return The current value of the muMIMOTx field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_mu_mimo_tx_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00080000)) >> 19);
}
/**
* @brief Returns the current value of the bfmer field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the bfmer field's value will be returned.
*
* @return The current value of the bfmer field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_bfmer_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00040000)) >> 18);
}
/**
* @brief Returns the current value of the bfmee field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the bfmee field's value will be returned.
*
* @return The current value of the bfmee field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_bfmee_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00020000)) >> 17);
}
/**
* @brief Returns the current value of the mac80211MHFormat field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the mac80211MHFormat field's value will be returned.
*
* @return The current value of the mac80211MHFormat field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_mac_80211mh_format_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00010000)) >> 16);
}
/**
* @brief Returns the current value of the coex field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the coex field's value will be returned.
*
* @return The current value of the coex field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_coex_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00004000)) >> 14);
}
/**
* @brief Returns the current value of the wapi field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the wapi field's value will be returned.
*
* @return The current value of the wapi field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_wapi_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00002000)) >> 13);
}
/**
* @brief Returns the current value of the tpc field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the tpc field's value will be returned.
*
* @return The current value of the tpc field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_tpc_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00001000)) >> 12);
}
/**
* @brief Returns the current value of the vht field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the vht field's value will be returned.
*
* @return The current value of the vht field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_vht_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00000800)) >> 11);
}
/**
* @brief Returns the current value of the ht field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the ht field's value will be returned.
*
* @return The current value of the ht field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_ht_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00000400)) >> 10);
}
/**
* @brief Returns the current value of the rce field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the rce field's value will be returned.
*
* @return The current value of the rce field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_rce_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00000100)) >> 8);
}
/**
* @brief Returns the current value of the ccmp field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the ccmp field's value will be returned.
*
* @return The current value of the ccmp field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_ccmp_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00000080)) >> 7);
}
/**
* @brief Returns the current value of the tkip field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the tkip field's value will be returned.
*
* @return The current value of the tkip field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_tkip_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00000040)) >> 6);
}
/**
* @brief Returns the current value of the wep field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the wep field's value will be returned.
*
* @return The current value of the wep field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_wep_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00000020)) >> 5);
}
/**
* @brief Returns the current value of the security field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the security field's value will be returned.
*
* @return The current value of the security field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_security_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00000010)) >> 4);
}
/**
* @brief Returns the current value of the sme field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the sme field's value will be returned.
*
* @return The current value of the sme field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_sme_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00000008)) >> 3);
}
/**
* @brief Returns the current value of the hcca field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the hcca field's value will be returned.
*
* @return The current value of the hcca field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_hcca_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00000004)) >> 2);
}
/**
* @brief Returns the current value of the edca field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the edca field's value will be returned.
*
* @return The current value of the edca field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_edca_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00000002)) >> 1);
}
/**
* @brief Returns the current value of the qos field in the VERSION_1 register.
*
* The VERSION_1 register will be read and the qos field's value will be returned.
*
* @return The current value of the qos field in the VERSION_1 register.
*/
__INLINE uint8_t nxmac_qos_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_1_ADDR);
return ((localVal & ((uint32_t)0x00000001)) >> 0);
}
/// @}
/**
* @name VERSION_2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 16:14 phaseNumber 0x0
* 13:08 releaseNumber 0x0
* 07 ieRelease 0
* 06:00 umVersion 0x0
* </pre>
*
* @{
*/
/// Address of the VERSION_2 register
#define NXMAC_VERSION_2_ADDR 0xC0000008
/// Offset of the VERSION_2 register from the base address
#define NXMAC_VERSION_2_OFFSET 0x00000008
/// Index of the VERSION_2 register
#define NXMAC_VERSION_2_INDEX 0x00000002
/// Reset value of the VERSION_2 register
#define NXMAC_VERSION_2_RESET 0x00000000
/**
* @brief Returns the current value of the VERSION_2 register.
* The VERSION_2 register will be read and its value returned.
* @return The current value of the VERSION_2 register.
*/
__INLINE uint32_t nxmac_version_2_get(void)
{
return REG_PL_RD(NXMAC_VERSION_2_ADDR);
}
// field definitions
/// PHASE_NUMBER field mask
#define NXMAC_PHASE_NUMBER_MASK ((uint32_t)0x0001C000)
/// PHASE_NUMBER field LSB position
#define NXMAC_PHASE_NUMBER_LSB 14
/// PHASE_NUMBER field width
#define NXMAC_PHASE_NUMBER_WIDTH ((uint32_t)0x00000003)
/// RELEASE_NUMBER field mask
#define NXMAC_RELEASE_NUMBER_MASK ((uint32_t)0x00003F00)
/// RELEASE_NUMBER field LSB position
#define NXMAC_RELEASE_NUMBER_LSB 8
/// RELEASE_NUMBER field width
#define NXMAC_RELEASE_NUMBER_WIDTH ((uint32_t)0x00000006)
/// IE_RELEASE field bit
#define NXMAC_IE_RELEASE_BIT ((uint32_t)0x00000080)
/// IE_RELEASE field position
#define NXMAC_IE_RELEASE_POS 7
/// UM_VERSION field mask
#define NXMAC_UM_VERSION_MASK ((uint32_t)0x0000007F)
/// UM_VERSION field LSB position
#define NXMAC_UM_VERSION_LSB 0
/// UM_VERSION field width
#define NXMAC_UM_VERSION_WIDTH ((uint32_t)0x00000007)
/// PHASE_NUMBER field reset value
#define NXMAC_PHASE_NUMBER_RST 0x0
/// RELEASE_NUMBER field reset value
#define NXMAC_RELEASE_NUMBER_RST 0x0
/// IE_RELEASE field reset value
#define NXMAC_IE_RELEASE_RST 0x0
/// UM_VERSION field reset value
#define NXMAC_UM_VERSION_RST 0x0
/**
* @brief Unpacks VERSION_2's fields from current value of the VERSION_2 register.
*
* Reads the VERSION_2 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] phasenumber - Will be populated with the current value of this field from the register.
* @param[out] releasenumber - Will be populated with the current value of this field from the register.
* @param[out] ierelease - Will be populated with the current value of this field from the register.
* @param[out] umversion - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_version_2_unpack(uint8_t *phasenumber, uint8_t *releasenumber, uint8_t *ierelease, uint8_t *umversion)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_2_ADDR);
*phasenumber = (localVal & ((uint32_t)0x0001C000)) >> 14;
*releasenumber = (localVal & ((uint32_t)0x00003F00)) >> 8;
*ierelease = (localVal & ((uint32_t)0x00000080)) >> 7;
*umversion = (localVal & ((uint32_t)0x0000007F)) >> 0;
}
/**
* @brief Returns the current value of the phaseNumber field in the VERSION_2 register.
*
* The VERSION_2 register will be read and the phaseNumber field's value will be returned.
*
* @return The current value of the phaseNumber field in the VERSION_2 register.
*/
__INLINE uint8_t nxmac_phase_number_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_2_ADDR);
return ((localVal & ((uint32_t)0x0001C000)) >> 14);
}
/**
* @brief Returns the current value of the releaseNumber field in the VERSION_2 register.
*
* The VERSION_2 register will be read and the releaseNumber field's value will be returned.
*
* @return The current value of the releaseNumber field in the VERSION_2 register.
*/
__INLINE uint8_t nxmac_release_number_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_2_ADDR);
return ((localVal & ((uint32_t)0x00003F00)) >> 8);
}
/**
* @brief Returns the current value of the ieRelease field in the VERSION_2 register.
*
* The VERSION_2 register will be read and the ieRelease field's value will be returned.
*
* @return The current value of the ieRelease field in the VERSION_2 register.
*/
__INLINE uint8_t nxmac_ie_release_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_2_ADDR);
return ((localVal & ((uint32_t)0x00000080)) >> 7);
}
/**
* @brief Returns the current value of the umVersion field in the VERSION_2 register.
*
* The VERSION_2 register will be read and the umVersion field's value will be returned.
*
* @return The current value of the umVersion field in the VERSION_2 register.
*/
__INLINE uint8_t nxmac_um_version_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_VERSION_2_ADDR);
return ((localVal & ((uint32_t)0x0000007F)) >> 0);
}
/// @}
/**
* @name BITMAP_CNT register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 bitmapCnt 0x0
* </pre>
*
* @{
*/
/// Address of the BITMAP_CNT register
#define NXMAC_BITMAP_CNT_ADDR 0xC000000C
/// Offset of the BITMAP_CNT register from the base address
#define NXMAC_BITMAP_CNT_OFFSET 0x0000000C
/// Index of the BITMAP_CNT register
#define NXMAC_BITMAP_CNT_INDEX 0x00000003
/// Reset value of the BITMAP_CNT register
#define NXMAC_BITMAP_CNT_RESET 0x00000000
/**
* @brief Returns the current value of the BITMAP_CNT register.
* The BITMAP_CNT register will be read and its value returned.
* @return The current value of the BITMAP_CNT register.
*/
__INLINE uint32_t nxmac_bitmap_cnt_get(void)
{
return REG_PL_RD(NXMAC_BITMAP_CNT_ADDR);
}
// field definitions
/// BITMAP_CNT field mask
#define NXMAC_BITMAP_CNT_MASK ((uint32_t)0x0000FFFF)
/// BITMAP_CNT field LSB position
#define NXMAC_BITMAP_CNT_LSB 0
/// BITMAP_CNT field width
#define NXMAC_BITMAP_CNT_WIDTH ((uint32_t)0x00000010)
/// BITMAP_CNT field reset value
#define NXMAC_BITMAP_CNT_RST 0x0
/**
* @brief Returns the current value of the bitmapCnt field in the BITMAP_CNT register.
*
* The BITMAP_CNT register will be read and the bitmapCnt field's value will be returned.
*
* @return The current value of the bitmapCnt field in the BITMAP_CNT register.
*/
__INLINE uint16_t nxmac_bitmap_cnt_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BITMAP_CNT_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0x0000FFFF)) == 0);
return (localVal >> 0);
}
/// @}
/**
* @name MAC_ADDR_LOW register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 macAddrLow 0x0
* </pre>
*
* @{
*/
/// Address of the MAC_ADDR_LOW register
#define NXMAC_MAC_ADDR_LOW_ADDR 0xC0000010
/// Offset of the MAC_ADDR_LOW register from the base address
#define NXMAC_MAC_ADDR_LOW_OFFSET 0x00000010
/// Index of the MAC_ADDR_LOW register
#define NXMAC_MAC_ADDR_LOW_INDEX 0x00000004
/// Reset value of the MAC_ADDR_LOW register
#define NXMAC_MAC_ADDR_LOW_RESET 0x00000000
/**
* @brief Returns the current value of the MAC_ADDR_LOW register.
* The MAC_ADDR_LOW register will be read and its value returned.
* @return The current value of the MAC_ADDR_LOW register.
*/
__INLINE uint32_t nxmac_mac_addr_low_get(void)
{
return REG_PL_RD(NXMAC_MAC_ADDR_LOW_ADDR);
}
/**
* @brief Sets the MAC_ADDR_LOW register to a value.
* The MAC_ADDR_LOW register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_mac_addr_low_set(uint32_t value)
{
REG_PL_WR(NXMAC_MAC_ADDR_LOW_ADDR, value);
}
// field definitions
/// MAC_ADDR_LOW field mask
#define NXMAC_MAC_ADDR_LOW_MASK ((uint32_t)0xFFFFFFFF)
/// MAC_ADDR_LOW field LSB position
#define NXMAC_MAC_ADDR_LOW_LSB 0
/// MAC_ADDR_LOW field width
#define NXMAC_MAC_ADDR_LOW_WIDTH ((uint32_t)0x00000020)
/// MAC_ADDR_LOW field reset value
#define NXMAC_MAC_ADDR_LOW_RST 0x0
/**
* @brief Returns the current value of the macAddrLow field in the MAC_ADDR_LOW register.
*
* The MAC_ADDR_LOW register will be read and the macAddrLow field's value will be returned.
*
* @return The current value of the macAddrLow field in the MAC_ADDR_LOW register.
*/
__INLINE uint32_t nxmac_mac_addr_low_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ADDR_LOW_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the macAddrLow field of the MAC_ADDR_LOW register.
*
* The MAC_ADDR_LOW register will be read, modified to contain the new field value, and written.
*
* @param[in] macaddrlow - The value to set the field to.
*/
__INLINE void nxmac_mac_addr_low_setf(uint32_t macaddrlow)
{
ASSERT_ERR((((uint32_t)macaddrlow << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_MAC_ADDR_LOW_ADDR, (uint32_t)macaddrlow << 0);
}
/// @}
/**
* @name MAC_ADDR_HI register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 macAddrHigh 0x0
* </pre>
*
* @{
*/
/// Address of the MAC_ADDR_HI register
#define NXMAC_MAC_ADDR_HI_ADDR 0xC0000014
/// Offset of the MAC_ADDR_HI register from the base address
#define NXMAC_MAC_ADDR_HI_OFFSET 0x00000014
/// Index of the MAC_ADDR_HI register
#define NXMAC_MAC_ADDR_HI_INDEX 0x00000005
/// Reset value of the MAC_ADDR_HI register
#define NXMAC_MAC_ADDR_HI_RESET 0x00000000
/**
* @brief Returns the current value of the MAC_ADDR_HI register.
* The MAC_ADDR_HI register will be read and its value returned.
* @return The current value of the MAC_ADDR_HI register.
*/
__INLINE uint32_t nxmac_mac_addr_hi_get(void)
{
return REG_PL_RD(NXMAC_MAC_ADDR_HI_ADDR);
}
/**
* @brief Sets the MAC_ADDR_HI register to a value.
* The MAC_ADDR_HI register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_mac_addr_hi_set(uint32_t value)
{
REG_PL_WR(NXMAC_MAC_ADDR_HI_ADDR, value);
}
// field definitions
/// MAC_ADDR_HIGH field mask
#define NXMAC_MAC_ADDR_HIGH_MASK ((uint32_t)0x0000FFFF)
/// MAC_ADDR_HIGH field LSB position
#define NXMAC_MAC_ADDR_HIGH_LSB 0
/// MAC_ADDR_HIGH field width
#define NXMAC_MAC_ADDR_HIGH_WIDTH ((uint32_t)0x00000010)
/// MAC_ADDR_HIGH field reset value
#define NXMAC_MAC_ADDR_HIGH_RST 0x0
/**
* @brief Returns the current value of the macAddrHigh field in the MAC_ADDR_HI register.
*
* The MAC_ADDR_HI register will be read and the macAddrHigh field's value will be returned.
*
* @return The current value of the macAddrHigh field in the MAC_ADDR_HI register.
*/
__INLINE uint16_t nxmac_mac_addr_high_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ADDR_HI_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0x0000FFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the macAddrHigh field of the MAC_ADDR_HI register.
*
* The MAC_ADDR_HI register will be read, modified to contain the new field value, and written.
*
* @param[in] macaddrhigh - The value to set the field to.
*/
__INLINE void nxmac_mac_addr_high_setf(uint16_t macaddrhigh)
{
ASSERT_ERR((((uint32_t)macaddrhigh << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_MAC_ADDR_HI_ADDR, (uint32_t)macaddrhigh << 0);
}
/// @}
/**
* @name MAC_ADDR_LOW_MASK register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 macAddrLowMask 0x0
* </pre>
*
* @{
*/
/// Address of the MAC_ADDR_LOW_MASK register
#define NXMAC_MAC_ADDR_LOW_MASK_ADDR 0xC0000018
/// Offset of the MAC_ADDR_LOW_MASK register from the base address
#define NXMAC_MAC_ADDR_LOW_MASK_OFFSET 0x00000018
/// Index of the MAC_ADDR_LOW_MASK register
#define NXMAC_MAC_ADDR_LOW_MASK_INDEX 0x00000006
/// Reset value of the MAC_ADDR_LOW_MASK register
#define NXMAC_MAC_ADDR_LOW_MASK_RESET 0x00000000
/**
* @brief Returns the current value of the MAC_ADDR_LOW_MASK register.
* The MAC_ADDR_LOW_MASK register will be read and its value returned.
* @return The current value of the MAC_ADDR_LOW_MASK register.
*/
__INLINE uint32_t nxmac_mac_addr_low_mask_get(void)
{
return REG_PL_RD(NXMAC_MAC_ADDR_LOW_MASK_ADDR);
}
/**
* @brief Sets the MAC_ADDR_LOW_MASK register to a value.
* The MAC_ADDR_LOW_MASK register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_mac_addr_low_mask_set(uint32_t value)
{
REG_PL_WR(NXMAC_MAC_ADDR_LOW_MASK_ADDR, value);
}
// field definitions
/// MAC_ADDR_LOW_MASK field mask
#define NXMAC_MAC_ADDR_LOW_MASK_MASK ((uint32_t)0xFFFFFFFF)
/// MAC_ADDR_LOW_MASK field LSB position
#define NXMAC_MAC_ADDR_LOW_MASK_LSB 0
/// MAC_ADDR_LOW_MASK field width
#define NXMAC_MAC_ADDR_LOW_MASK_WIDTH ((uint32_t)0x00000020)
/// MAC_ADDR_LOW_MASK field reset value
#define NXMAC_MAC_ADDR_LOW_MASK_RST 0x0
/**
* @brief Returns the current value of the macAddrLowMask field in the MAC_ADDR_LOW_MASK register.
*
* The MAC_ADDR_LOW_MASK register will be read and the macAddrLowMask field's value will be returned.
*
* @return The current value of the macAddrLowMask field in the MAC_ADDR_LOW_MASK register.
*/
__INLINE uint32_t nxmac_mac_addr_low_mask_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ADDR_LOW_MASK_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the macAddrLowMask field of the MAC_ADDR_LOW_MASK register.
*
* The MAC_ADDR_LOW_MASK register will be read, modified to contain the new field value, and written.
*
* @param[in] macaddrlowmask - The value to set the field to.
*/
__INLINE void nxmac_mac_addr_low_mask_setf(uint32_t macaddrlowmask)
{
ASSERT_ERR((((uint32_t)macaddrlowmask << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_MAC_ADDR_LOW_MASK_ADDR, (uint32_t)macaddrlowmask << 0);
}
/// @}
/**
* @name MAC_ADDR_HI_MASK register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 macAddrHighMask 0x0
* </pre>
*
* @{
*/
/// Address of the MAC_ADDR_HI_MASK register
#define NXMAC_MAC_ADDR_HI_MASK_ADDR 0xC000001C
/// Offset of the MAC_ADDR_HI_MASK register from the base address
#define NXMAC_MAC_ADDR_HI_MASK_OFFSET 0x0000001C
/// Index of the MAC_ADDR_HI_MASK register
#define NXMAC_MAC_ADDR_HI_MASK_INDEX 0x00000007
/// Reset value of the MAC_ADDR_HI_MASK register
#define NXMAC_MAC_ADDR_HI_MASK_RESET 0x00000000
/**
* @brief Returns the current value of the MAC_ADDR_HI_MASK register.
* The MAC_ADDR_HI_MASK register will be read and its value returned.
* @return The current value of the MAC_ADDR_HI_MASK register.
*/
__INLINE uint32_t nxmac_mac_addr_hi_mask_get(void)
{
return REG_PL_RD(NXMAC_MAC_ADDR_HI_MASK_ADDR);
}
/**
* @brief Sets the MAC_ADDR_HI_MASK register to a value.
* The MAC_ADDR_HI_MASK register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_mac_addr_hi_mask_set(uint32_t value)
{
REG_PL_WR(NXMAC_MAC_ADDR_HI_MASK_ADDR, value);
}
// field definitions
/// MAC_ADDR_HIGH_MASK field mask
#define NXMAC_MAC_ADDR_HIGH_MASK_MASK ((uint32_t)0x0000FFFF)
/// MAC_ADDR_HIGH_MASK field LSB position
#define NXMAC_MAC_ADDR_HIGH_MASK_LSB 0
/// MAC_ADDR_HIGH_MASK field width
#define NXMAC_MAC_ADDR_HIGH_MASK_WIDTH ((uint32_t)0x00000010)
/// MAC_ADDR_HIGH_MASK field reset value
#define NXMAC_MAC_ADDR_HIGH_MASK_RST 0x0
/**
* @brief Returns the current value of the macAddrHighMask field in the MAC_ADDR_HI_MASK register.
*
* The MAC_ADDR_HI_MASK register will be read and the macAddrHighMask field's value will be returned.
*
* @return The current value of the macAddrHighMask field in the MAC_ADDR_HI_MASK register.
*/
__INLINE uint16_t nxmac_mac_addr_high_mask_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ADDR_HI_MASK_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0x0000FFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the macAddrHighMask field of the MAC_ADDR_HI_MASK register.
*
* The MAC_ADDR_HI_MASK register will be read, modified to contain the new field value, and written.
*
* @param[in] macaddrhighmask - The value to set the field to.
*/
__INLINE void nxmac_mac_addr_high_mask_setf(uint16_t macaddrhighmask)
{
ASSERT_ERR((((uint32_t)macaddrhighmask << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_MAC_ADDR_HI_MASK_ADDR, (uint32_t)macaddrhighmask << 0);
}
/// @}
/**
* @name BSS_ID_LOW register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 bssIDLow 0x0
* </pre>
*
* @{
*/
/// Address of the BSS_ID_LOW register
#define NXMAC_BSS_ID_LOW_ADDR 0xC0000020
/// Offset of the BSS_ID_LOW register from the base address
#define NXMAC_BSS_ID_LOW_OFFSET 0x00000020
/// Index of the BSS_ID_LOW register
#define NXMAC_BSS_ID_LOW_INDEX 0x00000008
/// Reset value of the BSS_ID_LOW register
#define NXMAC_BSS_ID_LOW_RESET 0x00000000
/**
* @brief Returns the current value of the BSS_ID_LOW register.
* The BSS_ID_LOW register will be read and its value returned.
* @return The current value of the BSS_ID_LOW register.
*/
__INLINE uint32_t nxmac_bss_id_low_get(void)
{
return REG_PL_RD(NXMAC_BSS_ID_LOW_ADDR);
}
/**
* @brief Sets the BSS_ID_LOW register to a value.
* The BSS_ID_LOW register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_bss_id_low_set(uint32_t value)
{
REG_PL_WR(NXMAC_BSS_ID_LOW_ADDR, value);
}
// field definitions
/// BSS_ID_LOW field mask
#define NXMAC_BSS_ID_LOW_MASK ((uint32_t)0xFFFFFFFF)
/// BSS_ID_LOW field LSB position
#define NXMAC_BSS_ID_LOW_LSB 0
/// BSS_ID_LOW field width
#define NXMAC_BSS_ID_LOW_WIDTH ((uint32_t)0x00000020)
/// BSS_ID_LOW field reset value
#define NXMAC_BSS_ID_LOW_RST 0x0
/**
* @brief Returns the current value of the bssIDLow field in the BSS_ID_LOW register.
*
* The BSS_ID_LOW register will be read and the bssIDLow field's value will be returned.
*
* @return The current value of the bssIDLow field in the BSS_ID_LOW register.
*/
__INLINE uint32_t nxmac_bss_id_low_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BSS_ID_LOW_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the bssIDLow field of the BSS_ID_LOW register.
*
* The BSS_ID_LOW register will be read, modified to contain the new field value, and written.
*
* @param[in] bssidlow - The value to set the field to.
*/
__INLINE void nxmac_bss_id_low_setf(uint32_t bssidlow)
{
ASSERT_ERR((((uint32_t)bssidlow << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_BSS_ID_LOW_ADDR, (uint32_t)bssidlow << 0);
}
/// @}
/**
* @name BSS_ID_HI register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 bssIDHigh 0x0
* </pre>
*
* @{
*/
/// Address of the BSS_ID_HI register
#define NXMAC_BSS_ID_HI_ADDR 0xC0000024
/// Offset of the BSS_ID_HI register from the base address
#define NXMAC_BSS_ID_HI_OFFSET 0x00000024
/// Index of the BSS_ID_HI register
#define NXMAC_BSS_ID_HI_INDEX 0x00000009
/// Reset value of the BSS_ID_HI register
#define NXMAC_BSS_ID_HI_RESET 0x00000000
/**
* @brief Returns the current value of the BSS_ID_HI register.
* The BSS_ID_HI register will be read and its value returned.
* @return The current value of the BSS_ID_HI register.
*/
__INLINE uint32_t nxmac_bss_id_hi_get(void)
{
return REG_PL_RD(NXMAC_BSS_ID_HI_ADDR);
}
/**
* @brief Sets the BSS_ID_HI register to a value.
* The BSS_ID_HI register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_bss_id_hi_set(uint32_t value)
{
REG_PL_WR(NXMAC_BSS_ID_HI_ADDR, value);
}
// field definitions
/// BSS_ID_HIGH field mask
#define NXMAC_BSS_ID_HIGH_MASK ((uint32_t)0x0000FFFF)
/// BSS_ID_HIGH field LSB position
#define NXMAC_BSS_ID_HIGH_LSB 0
/// BSS_ID_HIGH field width
#define NXMAC_BSS_ID_HIGH_WIDTH ((uint32_t)0x00000010)
/// BSS_ID_HIGH field reset value
#define NXMAC_BSS_ID_HIGH_RST 0x0
/**
* @brief Returns the current value of the bssIDHigh field in the BSS_ID_HI register.
*
* The BSS_ID_HI register will be read and the bssIDHigh field's value will be returned.
*
* @return The current value of the bssIDHigh field in the BSS_ID_HI register.
*/
__INLINE uint16_t nxmac_bss_id_high_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BSS_ID_HI_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0x0000FFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the bssIDHigh field of the BSS_ID_HI register.
*
* The BSS_ID_HI register will be read, modified to contain the new field value, and written.
*
* @param[in] bssidhigh - The value to set the field to.
*/
__INLINE void nxmac_bss_id_high_setf(uint16_t bssidhigh)
{
ASSERT_ERR((((uint32_t)bssidhigh << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_BSS_ID_HI_ADDR, (uint32_t)bssidhigh << 0);
}
/// @}
/**
* @name BSS_ID_LOW_MASK register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 bssIDLowMask 0x0
* </pre>
*
* @{
*/
/// Address of the BSS_ID_LOW_MASK register
#define NXMAC_BSS_ID_LOW_MASK_ADDR 0xC0000028
/// Offset of the BSS_ID_LOW_MASK register from the base address
#define NXMAC_BSS_ID_LOW_MASK_OFFSET 0x00000028
/// Index of the BSS_ID_LOW_MASK register
#define NXMAC_BSS_ID_LOW_MASK_INDEX 0x0000000A
/// Reset value of the BSS_ID_LOW_MASK register
#define NXMAC_BSS_ID_LOW_MASK_RESET 0x00000000
/**
* @brief Returns the current value of the BSS_ID_LOW_MASK register.
* The BSS_ID_LOW_MASK register will be read and its value returned.
* @return The current value of the BSS_ID_LOW_MASK register.
*/
__INLINE uint32_t nxmac_bss_id_low_mask_get(void)
{
return REG_PL_RD(NXMAC_BSS_ID_LOW_MASK_ADDR);
}
/**
* @brief Sets the BSS_ID_LOW_MASK register to a value.
* The BSS_ID_LOW_MASK register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_bss_id_low_mask_set(uint32_t value)
{
REG_PL_WR(NXMAC_BSS_ID_LOW_MASK_ADDR, value);
}
// field definitions
/// BSS_ID_LOW_MASK field mask
#define NXMAC_BSS_ID_LOW_MASK_MASK ((uint32_t)0xFFFFFFFF)
/// BSS_ID_LOW_MASK field LSB position
#define NXMAC_BSS_ID_LOW_MASK_LSB 0
/// BSS_ID_LOW_MASK field width
#define NXMAC_BSS_ID_LOW_MASK_WIDTH ((uint32_t)0x00000020)
/// BSS_ID_LOW_MASK field reset value
#define NXMAC_BSS_ID_LOW_MASK_RST 0x0
/**
* @brief Returns the current value of the bssIDLowMask field in the BSS_ID_LOW_MASK register.
*
* The BSS_ID_LOW_MASK register will be read and the bssIDLowMask field's value will be returned.
*
* @return The current value of the bssIDLowMask field in the BSS_ID_LOW_MASK register.
*/
__INLINE uint32_t nxmac_bss_id_low_mask_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BSS_ID_LOW_MASK_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the bssIDLowMask field of the BSS_ID_LOW_MASK register.
*
* The BSS_ID_LOW_MASK register will be read, modified to contain the new field value, and written.
*
* @param[in] bssidlowmask - The value to set the field to.
*/
__INLINE void nxmac_bss_id_low_mask_setf(uint32_t bssidlowmask)
{
ASSERT_ERR((((uint32_t)bssidlowmask << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_BSS_ID_LOW_MASK_ADDR, (uint32_t)bssidlowmask << 0);
}
/// @}
/**
* @name BSS_ID_HI_MASK register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 bssIDHighMask 0x0
* </pre>
*
* @{
*/
/// Address of the BSS_ID_HI_MASK register
#define NXMAC_BSS_ID_HI_MASK_ADDR 0xC000002C
/// Offset of the BSS_ID_HI_MASK register from the base address
#define NXMAC_BSS_ID_HI_MASK_OFFSET 0x0000002C
/// Index of the BSS_ID_HI_MASK register
#define NXMAC_BSS_ID_HI_MASK_INDEX 0x0000000B
/// Reset value of the BSS_ID_HI_MASK register
#define NXMAC_BSS_ID_HI_MASK_RESET 0x00000000
/**
* @brief Returns the current value of the BSS_ID_HI_MASK register.
* The BSS_ID_HI_MASK register will be read and its value returned.
* @return The current value of the BSS_ID_HI_MASK register.
*/
__INLINE uint32_t nxmac_bss_id_hi_mask_get(void)
{
return REG_PL_RD(NXMAC_BSS_ID_HI_MASK_ADDR);
}
/**
* @brief Sets the BSS_ID_HI_MASK register to a value.
* The BSS_ID_HI_MASK register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_bss_id_hi_mask_set(uint32_t value)
{
REG_PL_WR(NXMAC_BSS_ID_HI_MASK_ADDR, value);
}
// field definitions
/// BSS_ID_HIGH_MASK field mask
#define NXMAC_BSS_ID_HIGH_MASK_MASK ((uint32_t)0x0000FFFF)
/// BSS_ID_HIGH_MASK field LSB position
#define NXMAC_BSS_ID_HIGH_MASK_LSB 0
/// BSS_ID_HIGH_MASK field width
#define NXMAC_BSS_ID_HIGH_MASK_WIDTH ((uint32_t)0x00000010)
/// BSS_ID_HIGH_MASK field reset value
#define NXMAC_BSS_ID_HIGH_MASK_RST 0x0
/**
* @brief Returns the current value of the bssIDHighMask field in the BSS_ID_HI_MASK register.
*
* The BSS_ID_HI_MASK register will be read and the bssIDHighMask field's value will be returned.
*
* @return The current value of the bssIDHighMask field in the BSS_ID_HI_MASK register.
*/
__INLINE uint16_t nxmac_bss_id_high_mask_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BSS_ID_HI_MASK_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0x0000FFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the bssIDHighMask field of the BSS_ID_HI_MASK register.
*
* The BSS_ID_HI_MASK register will be read, modified to contain the new field value, and written.
*
* @param[in] bssidhighmask - The value to set the field to.
*/
__INLINE void nxmac_bss_id_high_mask_setf(uint16_t bssidhighmask)
{
ASSERT_ERR((((uint32_t)bssidhighmask << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_BSS_ID_HI_MASK_ADDR, (uint32_t)bssidhighmask << 0);
}
/// @}
/**
* @name STATE_CNTRL register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 07:04 nextState 0x0
* 03:00 currentState 0x0
* </pre>
*
* @{
*/
/// Address of the STATE_CNTRL register
#define NXMAC_STATE_CNTRL_ADDR 0xC0000038
/// Offset of the STATE_CNTRL register from the base address
#define NXMAC_STATE_CNTRL_OFFSET 0x00000038
/// Index of the STATE_CNTRL register
#define NXMAC_STATE_CNTRL_INDEX 0x0000000E
/// Reset value of the STATE_CNTRL register
#define NXMAC_STATE_CNTRL_RESET 0x00000000
/**
* @brief Returns the current value of the STATE_CNTRL register.
* The STATE_CNTRL register will be read and its value returned.
* @return The current value of the STATE_CNTRL register.
*/
__INLINE uint32_t nxmac_state_cntrl_get(void)
{
return REG_PL_RD(NXMAC_STATE_CNTRL_ADDR);
}
/**
* @brief Sets the STATE_CNTRL register to a value.
* The STATE_CNTRL register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_state_cntrl_set(uint32_t value)
{
REG_PL_WR(NXMAC_STATE_CNTRL_ADDR, value);
}
// field definitions
/// NEXT_STATE field mask
#define NXMAC_NEXT_STATE_MASK ((uint32_t)0x000000F0)
/// NEXT_STATE field LSB position
#define NXMAC_NEXT_STATE_LSB 4
/// NEXT_STATE field width
#define NXMAC_NEXT_STATE_WIDTH ((uint32_t)0x00000004)
/// CURRENT_STATE field mask
#define NXMAC_CURRENT_STATE_MASK ((uint32_t)0x0000000F)
/// CURRENT_STATE field LSB position
#define NXMAC_CURRENT_STATE_LSB 0
/// CURRENT_STATE field width
#define NXMAC_CURRENT_STATE_WIDTH ((uint32_t)0x00000004)
/// NEXT_STATE field reset value
#define NXMAC_NEXT_STATE_RST 0x0
/// CURRENT_STATE field reset value
#define NXMAC_CURRENT_STATE_RST 0x0
/**
* @brief Unpacks STATE_CNTRL's fields from current value of the STATE_CNTRL register.
*
* Reads the STATE_CNTRL register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] nextstate - Will be populated with the current value of this field from the register.
* @param[out] currentstate - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_state_cntrl_unpack(uint8_t *nextstate, uint8_t *currentstate)
{
uint32_t localVal = REG_PL_RD(NXMAC_STATE_CNTRL_ADDR);
*nextstate = (localVal & ((uint32_t)0x000000F0)) >> 4;
*currentstate = (localVal & ((uint32_t)0x0000000F)) >> 0;
}
/**
* @brief Returns the current value of the nextState field in the STATE_CNTRL register.
*
* The STATE_CNTRL register will be read and the nextState field's value will be returned.
*
* @return The current value of the nextState field in the STATE_CNTRL register.
*/
__INLINE uint8_t nxmac_next_state_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_STATE_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x000000F0)) >> 4);
}
/**
* @brief Sets the nextState field of the STATE_CNTRL register.
*
* The STATE_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] nextstate - The value to set the field to.
*/
__INLINE void nxmac_next_state_setf(uint8_t nextstate)
{
ASSERT_ERR((((uint32_t)nextstate << 4) & ~((uint32_t)0x000000F0)) == 0);
REG_PL_WR(NXMAC_STATE_CNTRL_ADDR, (uint32_t)nextstate << 4);
}
/**
* @brief Returns the current value of the currentState field in the STATE_CNTRL register.
*
* The STATE_CNTRL register will be read and the currentState field's value will be returned.
*
* @return The current value of the currentState field in the STATE_CNTRL register.
*/
__INLINE uint8_t nxmac_current_state_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_STATE_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x0000000F)) >> 0);
}
/// @}
/**
* @name SCAN_CNTRL register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 probeDelay 0x0
* </pre>
*
* @{
*/
/// Address of the SCAN_CNTRL register
#define NXMAC_SCAN_CNTRL_ADDR 0xC000003C
/// Offset of the SCAN_CNTRL register from the base address
#define NXMAC_SCAN_CNTRL_OFFSET 0x0000003C
/// Index of the SCAN_CNTRL register
#define NXMAC_SCAN_CNTRL_INDEX 0x0000000F
/// Reset value of the SCAN_CNTRL register
#define NXMAC_SCAN_CNTRL_RESET 0x00000000
/**
* @brief Returns the current value of the SCAN_CNTRL register.
* The SCAN_CNTRL register will be read and its value returned.
* @return The current value of the SCAN_CNTRL register.
*/
__INLINE uint32_t nxmac_scan_cntrl_get(void)
{
return REG_PL_RD(NXMAC_SCAN_CNTRL_ADDR);
}
/**
* @brief Sets the SCAN_CNTRL register to a value.
* The SCAN_CNTRL register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_scan_cntrl_set(uint32_t value)
{
REG_PL_WR(NXMAC_SCAN_CNTRL_ADDR, value);
}
// field definitions
/// PROBE_DELAY field mask
#define NXMAC_PROBE_DELAY_MASK ((uint32_t)0x0000FFFF)
/// PROBE_DELAY field LSB position
#define NXMAC_PROBE_DELAY_LSB 0
/// PROBE_DELAY field width
#define NXMAC_PROBE_DELAY_WIDTH ((uint32_t)0x00000010)
/// PROBE_DELAY field reset value
#define NXMAC_PROBE_DELAY_RST 0x0
/**
* @brief Returns the current value of the probeDelay field in the SCAN_CNTRL register.
*
* The SCAN_CNTRL register will be read and the probeDelay field's value will be returned.
*
* @return The current value of the probeDelay field in the SCAN_CNTRL register.
*/
__INLINE uint16_t nxmac_probe_delay_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_SCAN_CNTRL_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0x0000FFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the probeDelay field of the SCAN_CNTRL register.
*
* The SCAN_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] probedelay - The value to set the field to.
*/
__INLINE void nxmac_probe_delay_setf(uint16_t probedelay)
{
ASSERT_ERR((((uint32_t)probedelay << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_SCAN_CNTRL_ADDR, (uint32_t)probedelay << 0);
}
/// @}
/**
* @name DOZE_CNTRL_1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:17 atimW 0x0
* 16 wakeupDTIM 0
* 15:00 listenInterval 0x0
* </pre>
*
* @{
*/
/// Address of the DOZE_CNTRL_1 register
#define NXMAC_DOZE_CNTRL_1_ADDR 0xC0000044
/// Offset of the DOZE_CNTRL_1 register from the base address
#define NXMAC_DOZE_CNTRL_1_OFFSET 0x00000044
/// Index of the DOZE_CNTRL_1 register
#define NXMAC_DOZE_CNTRL_1_INDEX 0x00000011
/// Reset value of the DOZE_CNTRL_1 register
#define NXMAC_DOZE_CNTRL_1_RESET 0x00000000
/**
* @brief Returns the current value of the DOZE_CNTRL_1 register.
* The DOZE_CNTRL_1 register will be read and its value returned.
* @return The current value of the DOZE_CNTRL_1 register.
*/
__INLINE uint32_t nxmac_doze_cntrl_1_get(void)
{
return REG_PL_RD(NXMAC_DOZE_CNTRL_1_ADDR);
}
/**
* @brief Sets the DOZE_CNTRL_1 register to a value.
* The DOZE_CNTRL_1 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_doze_cntrl_1_set(uint32_t value)
{
REG_PL_WR(NXMAC_DOZE_CNTRL_1_ADDR, value);
}
// field definitions
/// ATIM_W field mask
#define NXMAC_ATIM_W_MASK ((uint32_t)0xFFFE0000)
/// ATIM_W field LSB position
#define NXMAC_ATIM_W_LSB 17
/// ATIM_W field width
#define NXMAC_ATIM_W_WIDTH ((uint32_t)0x0000000F)
/// WAKEUP_DTIM field bit
#define NXMAC_WAKEUP_DTIM_BIT ((uint32_t)0x00010000)
/// WAKEUP_DTIM field position
#define NXMAC_WAKEUP_DTIM_POS 16
/// LISTEN_INTERVAL field mask
#define NXMAC_LISTEN_INTERVAL_MASK ((uint32_t)0x0000FFFF)
/// LISTEN_INTERVAL field LSB position
#define NXMAC_LISTEN_INTERVAL_LSB 0
/// LISTEN_INTERVAL field width
#define NXMAC_LISTEN_INTERVAL_WIDTH ((uint32_t)0x00000010)
/// ATIM_W field reset value
#define NXMAC_ATIM_W_RST 0x0
/// WAKEUP_DTIM field reset value
#define NXMAC_WAKEUP_DTIM_RST 0x0
/// LISTEN_INTERVAL field reset value
#define NXMAC_LISTEN_INTERVAL_RST 0x0
/**
* @brief Constructs a value for the DOZE_CNTRL_1 register given values for its fields
* and writes the value to the register.
*
* @param[in] atimw - The value to use for the atimW field.
* @param[in] wakeupdtim - The value to use for the wakeupDTIM field.
* @param[in] listeninterval - The value to use for the listenInterval field.
*/
__INLINE void nxmac_doze_cntrl_1_pack(uint16_t atimw, uint8_t wakeupdtim, uint16_t listeninterval)
{
ASSERT_ERR((((uint32_t)atimw << 17) & ~((uint32_t)0xFFFE0000)) == 0);
ASSERT_ERR((((uint32_t)wakeupdtim << 16) & ~((uint32_t)0x00010000)) == 0);
ASSERT_ERR((((uint32_t)listeninterval << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_DOZE_CNTRL_1_ADDR, ((uint32_t)atimw << 17) | ((uint32_t)wakeupdtim << 16) | ((uint32_t)listeninterval << 0));
}
/**
* @brief Unpacks DOZE_CNTRL_1's fields from current value of the DOZE_CNTRL_1 register.
*
* Reads the DOZE_CNTRL_1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] atimw - Will be populated with the current value of this field from the register.
* @param[out] wakeupdtim - Will be populated with the current value of this field from the register.
* @param[out] listeninterval - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_doze_cntrl_1_unpack(uint16_t *atimw, uint8_t *wakeupdtim, uint16_t *listeninterval)
{
uint32_t localVal = REG_PL_RD(NXMAC_DOZE_CNTRL_1_ADDR);
*atimw = (localVal & ((uint32_t)0xFFFE0000)) >> 17;
*wakeupdtim = (localVal & ((uint32_t)0x00010000)) >> 16;
*listeninterval = (localVal & ((uint32_t)0x0000FFFF)) >> 0;
}
/**
* @brief Returns the current value of the atimW field in the DOZE_CNTRL_1 register.
*
* The DOZE_CNTRL_1 register will be read and the atimW field's value will be returned.
*
* @return The current value of the atimW field in the DOZE_CNTRL_1 register.
*/
__INLINE uint16_t nxmac_atim_w_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_DOZE_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0xFFFE0000)) >> 17);
}
/**
* @brief Sets the atimW field of the DOZE_CNTRL_1 register.
*
* The DOZE_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] atimw - The value to set the field to.
*/
__INLINE void nxmac_atim_w_setf(uint16_t atimw)
{
ASSERT_ERR((((uint32_t)atimw << 17) & ~((uint32_t)0xFFFE0000)) == 0);
REG_PL_WR(NXMAC_DOZE_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_DOZE_CNTRL_1_ADDR) & ~((uint32_t)0xFFFE0000)) | ((uint32_t)atimw << 17));
}
/**
* @brief Returns the current value of the wakeupDTIM field in the DOZE_CNTRL_1 register.
*
* The DOZE_CNTRL_1 register will be read and the wakeupDTIM field's value will be returned.
*
* @return The current value of the wakeupDTIM field in the DOZE_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_wakeup_dtim_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_DOZE_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00010000)) >> 16);
}
/**
* @brief Sets the wakeupDTIM field of the DOZE_CNTRL_1 register.
*
* The DOZE_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] wakeupdtim - The value to set the field to.
*/
__INLINE void nxmac_wakeup_dtim_setf(uint8_t wakeupdtim)
{
ASSERT_ERR((((uint32_t)wakeupdtim << 16) & ~((uint32_t)0x00010000)) == 0);
REG_PL_WR(NXMAC_DOZE_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_DOZE_CNTRL_1_ADDR) & ~((uint32_t)0x00010000)) | ((uint32_t)wakeupdtim << 16));
}
/**
* @brief Returns the current value of the listenInterval field in the DOZE_CNTRL_1 register.
*
* The DOZE_CNTRL_1 register will be read and the listenInterval field's value will be returned.
*
* @return The current value of the listenInterval field in the DOZE_CNTRL_1 register.
*/
__INLINE uint16_t nxmac_listen_interval_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_DOZE_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x0000FFFF)) >> 0);
}
/**
* @brief Sets the listenInterval field of the DOZE_CNTRL_1 register.
*
* The DOZE_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] listeninterval - The value to set the field to.
*/
__INLINE void nxmac_listen_interval_setf(uint16_t listeninterval)
{
ASSERT_ERR((((uint32_t)listeninterval << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_DOZE_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_DOZE_CNTRL_1_ADDR) & ~((uint32_t)0x0000FFFF)) | ((uint32_t)listeninterval << 0));
}
/// @}
/**
* @name MAC_CNTRL_1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 26 rxRIFSEn 0
* 25 tsfMgtDisable 0
* 24 tsfUpdatedBySW 0
* 16:14 abgnMode 0x3
* 13 keyStoRAMReset 0
* 12 mibTableReset 0
* 11 rateControllerMPIF 1
* 10 disableBAResp 0
* 09 disableCTSResp 0
* 08 disableACKResp 0
* 07 activeClkGating 1
* 06 enableLPClkSwitch 0
* 05 lpClk32786Hz 0
* 03 cfpAware 0
* 02 pwrMgt 0
* 01 ap 0
* 00 bssType 1
* </pre>
*
* @{
*/
/// Address of the MAC_CNTRL_1 register
#define NXMAC_MAC_CNTRL_1_ADDR 0xC000004C
/// Offset of the MAC_CNTRL_1 register from the base address
#define NXMAC_MAC_CNTRL_1_OFFSET 0x0000004C
/// Index of the MAC_CNTRL_1 register
#define NXMAC_MAC_CNTRL_1_INDEX 0x00000013
/// Reset value of the MAC_CNTRL_1 register
#define NXMAC_MAC_CNTRL_1_RESET 0x0000C881
/**
* @brief Returns the current value of the MAC_CNTRL_1 register.
* The MAC_CNTRL_1 register will be read and its value returned.
* @return The current value of the MAC_CNTRL_1 register.
*/
__INLINE uint32_t nxmac_mac_cntrl_1_get(void)
{
return REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
}
/**
* @brief Sets the MAC_CNTRL_1 register to a value.
* The MAC_CNTRL_1 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_mac_cntrl_1_set(uint32_t value)
{
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, value);
}
// field definitions
/// RX_RIFS_EN field bit
#define NXMAC_RX_RIFS_EN_BIT ((uint32_t)0x04000000)
/// RX_RIFS_EN field position
#define NXMAC_RX_RIFS_EN_POS 26
/// TSF_MGT_DISABLE field bit
#define NXMAC_TSF_MGT_DISABLE_BIT ((uint32_t)0x02000000)
/// TSF_MGT_DISABLE field position
#define NXMAC_TSF_MGT_DISABLE_POS 25
/// TSF_UPDATED_BY_SW field bit
#define NXMAC_TSF_UPDATED_BY_SW_BIT ((uint32_t)0x01000000)
/// TSF_UPDATED_BY_SW field position
#define NXMAC_TSF_UPDATED_BY_SW_POS 24
/// ABGN_MODE field mask
#define NXMAC_ABGN_MODE_MASK ((uint32_t)0x0001C000)
/// ABGN_MODE field LSB position
#define NXMAC_ABGN_MODE_LSB 14
/// ABGN_MODE field width
#define NXMAC_ABGN_MODE_WIDTH ((uint32_t)0x00000003)
/// KEY_STO_RAM_RESET field bit
#define NXMAC_KEY_STO_RAM_RESET_BIT ((uint32_t)0x00002000)
/// KEY_STO_RAM_RESET field position
#define NXMAC_KEY_STO_RAM_RESET_POS 13
/// MIB_TABLE_RESET field bit
#define NXMAC_MIB_TABLE_RESET_BIT ((uint32_t)0x00001000)
/// MIB_TABLE_RESET field position
#define NXMAC_MIB_TABLE_RESET_POS 12
/// RATE_CONTROLLER_MPIF field bit
#define NXMAC_RATE_CONTROLLER_MPIF_BIT ((uint32_t)0x00000800)
/// RATE_CONTROLLER_MPIF field position
#define NXMAC_RATE_CONTROLLER_MPIF_POS 11
/// DISABLE_BA_RESP field bit
#define NXMAC_DISABLE_BA_RESP_BIT ((uint32_t)0x00000400)
/// DISABLE_BA_RESP field position
#define NXMAC_DISABLE_BA_RESP_POS 10
/// DISABLE_CTS_RESP field bit
#define NXMAC_DISABLE_CTS_RESP_BIT ((uint32_t)0x00000200)
/// DISABLE_CTS_RESP field position
#define NXMAC_DISABLE_CTS_RESP_POS 9
/// DISABLE_ACK_RESP field bit
#define NXMAC_DISABLE_ACK_RESP_BIT ((uint32_t)0x00000100)
/// DISABLE_ACK_RESP field position
#define NXMAC_DISABLE_ACK_RESP_POS 8
/// ACTIVE_CLK_GATING field bit
#define NXMAC_ACTIVE_CLK_GATING_BIT ((uint32_t)0x00000080)
/// ACTIVE_CLK_GATING field position
#define NXMAC_ACTIVE_CLK_GATING_POS 7
/// ENABLE_LP_CLK_SWITCH field bit
#define NXMAC_ENABLE_LP_CLK_SWITCH_BIT ((uint32_t)0x00000040)
/// ENABLE_LP_CLK_SWITCH field position
#define NXMAC_ENABLE_LP_CLK_SWITCH_POS 6
/// LP_CLK_32786_HZ field bit
#define NXMAC_LP_CLK_32786_HZ_BIT ((uint32_t)0x00000020)
/// LP_CLK_32786_HZ field position
#define NXMAC_LP_CLK_32786_HZ_POS 5
/// CFP_AWARE field bit
#define NXMAC_CFP_AWARE_BIT ((uint32_t)0x00000008)
/// CFP_AWARE field position
#define NXMAC_CFP_AWARE_POS 3
/// PWR_MGT field bit
#define NXMAC_PWR_MGT_BIT ((uint32_t)0x00000004)
/// PWR_MGT field position
#define NXMAC_PWR_MGT_POS 2
/// AP field bit
#define NXMAC_AP_BIT ((uint32_t)0x00000002)
/// AP field position
#define NXMAC_AP_POS 1
/// BSS_TYPE field bit
#define NXMAC_BSS_TYPE_BIT ((uint32_t)0x00000001)
/// BSS_TYPE field position
#define NXMAC_BSS_TYPE_POS 0
/// RX_RIFS_EN field reset value
#define NXMAC_RX_RIFS_EN_RST 0x0
/// TSF_MGT_DISABLE field reset value
#define NXMAC_TSF_MGT_DISABLE_RST 0x0
/// TSF_UPDATED_BY_SW field reset value
#define NXMAC_TSF_UPDATED_BY_SW_RST 0x0
/// ABGN_MODE field reset value
#define NXMAC_ABGN_MODE_RST 0x3
/// KEY_STO_RAM_RESET field reset value
#define NXMAC_KEY_STO_RAM_RESET_RST 0x0
/// MIB_TABLE_RESET field reset value
#define NXMAC_MIB_TABLE_RESET_RST 0x0
/// RATE_CONTROLLER_MPIF field reset value
#define NXMAC_RATE_CONTROLLER_MPIF_RST 0x1
/// DISABLE_BA_RESP field reset value
#define NXMAC_DISABLE_BA_RESP_RST 0x0
/// DISABLE_CTS_RESP field reset value
#define NXMAC_DISABLE_CTS_RESP_RST 0x0
/// DISABLE_ACK_RESP field reset value
#define NXMAC_DISABLE_ACK_RESP_RST 0x0
/// ACTIVE_CLK_GATING field reset value
#define NXMAC_ACTIVE_CLK_GATING_RST 0x1
/// ENABLE_LP_CLK_SWITCH field reset value
#define NXMAC_ENABLE_LP_CLK_SWITCH_RST 0x0
/// LP_CLK_32786_HZ field reset value
#define NXMAC_LP_CLK_32786_HZ_RST 0x0
/// CFP_AWARE field reset value
#define NXMAC_CFP_AWARE_RST 0x0
/// PWR_MGT field reset value
#define NXMAC_PWR_MGT_RST 0x0
/// AP field reset value
#define NXMAC_AP_RST 0x0
/// BSS_TYPE field reset value
#define NXMAC_BSS_TYPE_RST 0x1
/**
* @brief Constructs a value for the MAC_CNTRL_1 register given values for its fields
* and writes the value to the register.
*
* @param[in] rxrifsen - The value to use for the rxRIFSEn field.
* @param[in] tsfmgtdisable - The value to use for the tsfMgtDisable field.
* @param[in] tsfupdatedbysw - The value to use for the tsfUpdatedBySW field.
* @param[in] abgnmode - The value to use for the abgnMode field.
* @param[in] keystoramreset - The value to use for the keyStoRAMReset field.
* @param[in] mibtablereset - The value to use for the mibTableReset field.
* @param[in] ratecontrollermpif - The value to use for the rateControllerMPIF field.
* @param[in] disablebaresp - The value to use for the disableBAResp field.
* @param[in] disablectsresp - The value to use for the disableCTSResp field.
* @param[in] disableackresp - The value to use for the disableACKResp field.
* @param[in] activeclkgating - The value to use for the activeClkGating field.
* @param[in] enablelpclkswitch - The value to use for the enableLPClkSwitch field.
* @param[in] lpclk32786hz - The value to use for the lpClk32786Hz field.
* @param[in] cfpaware - The value to use for the cfpAware field.
* @param[in] pwrmgt - The value to use for the pwrMgt field.
* @param[in] ap - The value to use for the ap field.
* @param[in] bsstype - The value to use for the bssType field.
*/
__INLINE void nxmac_mac_cntrl_1_pack(uint8_t rxrifsen, uint8_t tsfmgtdisable, uint8_t tsfupdatedbysw, uint8_t abgnmode, uint8_t keystoramreset, uint8_t mibtablereset, uint8_t ratecontrollermpif, uint8_t disablebaresp, uint8_t disablectsresp, uint8_t disableackresp, uint8_t activeclkgating, uint8_t enablelpclkswitch, uint8_t lpclk32786hz, uint8_t cfpaware, uint8_t pwrmgt, uint8_t ap, uint8_t bsstype)
{
ASSERT_ERR((((uint32_t)rxrifsen << 26) & ~((uint32_t)0x04000000)) == 0);
ASSERT_ERR((((uint32_t)tsfmgtdisable << 25) & ~((uint32_t)0x02000000)) == 0);
ASSERT_ERR((((uint32_t)tsfupdatedbysw << 24) & ~((uint32_t)0x01000000)) == 0);
ASSERT_ERR((((uint32_t)abgnmode << 14) & ~((uint32_t)0x0001C000)) == 0);
ASSERT_ERR((((uint32_t)keystoramreset << 13) & ~((uint32_t)0x00002000)) == 0);
ASSERT_ERR((((uint32_t)mibtablereset << 12) & ~((uint32_t)0x00001000)) == 0);
ASSERT_ERR((((uint32_t)ratecontrollermpif << 11) & ~((uint32_t)0x00000800)) == 0);
ASSERT_ERR((((uint32_t)disablebaresp << 10) & ~((uint32_t)0x00000400)) == 0);
ASSERT_ERR((((uint32_t)disablectsresp << 9) & ~((uint32_t)0x00000200)) == 0);
ASSERT_ERR((((uint32_t)disableackresp << 8) & ~((uint32_t)0x00000100)) == 0);
ASSERT_ERR((((uint32_t)activeclkgating << 7) & ~((uint32_t)0x00000080)) == 0);
ASSERT_ERR((((uint32_t)enablelpclkswitch << 6) & ~((uint32_t)0x00000040)) == 0);
ASSERT_ERR((((uint32_t)lpclk32786hz << 5) & ~((uint32_t)0x00000020)) == 0);
ASSERT_ERR((((uint32_t)cfpaware << 3) & ~((uint32_t)0x00000008)) == 0);
ASSERT_ERR((((uint32_t)pwrmgt << 2) & ~((uint32_t)0x00000004)) == 0);
ASSERT_ERR((((uint32_t)ap << 1) & ~((uint32_t)0x00000002)) == 0);
ASSERT_ERR((((uint32_t)bsstype << 0) & ~((uint32_t)0x00000001)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, ((uint32_t)rxrifsen << 26) | ((uint32_t)tsfmgtdisable << 25) | ((uint32_t)tsfupdatedbysw << 24) | ((uint32_t)abgnmode << 14) | ((uint32_t)keystoramreset << 13) | ((uint32_t)mibtablereset << 12) | ((uint32_t)ratecontrollermpif << 11) | ((uint32_t)disablebaresp << 10) | ((uint32_t)disablectsresp << 9) | ((uint32_t)disableackresp << 8) | ((uint32_t)activeclkgating << 7) | ((uint32_t)enablelpclkswitch << 6) | ((uint32_t)lpclk32786hz << 5) | ((uint32_t)cfpaware << 3) | ((uint32_t)pwrmgt << 2) | ((uint32_t)ap << 1) | ((uint32_t)bsstype << 0));
}
/**
* @brief Unpacks MAC_CNTRL_1's fields from current value of the MAC_CNTRL_1 register.
*
* Reads the MAC_CNTRL_1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] rxrifsen - Will be populated with the current value of this field from the register.
* @param[out] tsfmgtdisable - Will be populated with the current value of this field from the register.
* @param[out] tsfupdatedbysw - Will be populated with the current value of this field from the register.
* @param[out] abgnmode - Will be populated with the current value of this field from the register.
* @param[out] keystoramreset - Will be populated with the current value of this field from the register.
* @param[out] mibtablereset - Will be populated with the current value of this field from the register.
* @param[out] ratecontrollermpif - Will be populated with the current value of this field from the register.
* @param[out] disablebaresp - Will be populated with the current value of this field from the register.
* @param[out] disablectsresp - Will be populated with the current value of this field from the register.
* @param[out] disableackresp - Will be populated with the current value of this field from the register.
* @param[out] activeclkgating - Will be populated with the current value of this field from the register.
* @param[out] enablelpclkswitch - Will be populated with the current value of this field from the register.
* @param[out] lpclk32786hz - Will be populated with the current value of this field from the register.
* @param[out] cfpaware - Will be populated with the current value of this field from the register.
* @param[out] pwrmgt - Will be populated with the current value of this field from the register.
* @param[out] ap - Will be populated with the current value of this field from the register.
* @param[out] bsstype - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_mac_cntrl_1_unpack(uint8_t *rxrifsen, uint8_t *tsfmgtdisable, uint8_t *tsfupdatedbysw, uint8_t *abgnmode, uint8_t *keystoramreset, uint8_t *mibtablereset, uint8_t *ratecontrollermpif, uint8_t *disablebaresp, uint8_t *disablectsresp, uint8_t *disableackresp, uint8_t *activeclkgating, uint8_t *enablelpclkswitch, uint8_t *lpclk32786hz, uint8_t *cfpaware, uint8_t *pwrmgt, uint8_t *ap, uint8_t *bsstype)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
*rxrifsen = (localVal & ((uint32_t)0x04000000)) >> 26;
*tsfmgtdisable = (localVal & ((uint32_t)0x02000000)) >> 25;
*tsfupdatedbysw = (localVal & ((uint32_t)0x01000000)) >> 24;
*abgnmode = (localVal & ((uint32_t)0x0001C000)) >> 14;
*keystoramreset = (localVal & ((uint32_t)0x00002000)) >> 13;
*mibtablereset = (localVal & ((uint32_t)0x00001000)) >> 12;
*ratecontrollermpif = (localVal & ((uint32_t)0x00000800)) >> 11;
*disablebaresp = (localVal & ((uint32_t)0x00000400)) >> 10;
*disablectsresp = (localVal & ((uint32_t)0x00000200)) >> 9;
*disableackresp = (localVal & ((uint32_t)0x00000100)) >> 8;
*activeclkgating = (localVal & ((uint32_t)0x00000080)) >> 7;
*enablelpclkswitch = (localVal & ((uint32_t)0x00000040)) >> 6;
*lpclk32786hz = (localVal & ((uint32_t)0x00000020)) >> 5;
*cfpaware = (localVal & ((uint32_t)0x00000008)) >> 3;
*pwrmgt = (localVal & ((uint32_t)0x00000004)) >> 2;
*ap = (localVal & ((uint32_t)0x00000002)) >> 1;
*bsstype = (localVal & ((uint32_t)0x00000001)) >> 0;
}
/**
* @brief Returns the current value of the rxRIFSEn field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the rxRIFSEn field's value will be returned.
*
* @return The current value of the rxRIFSEn field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_rx_rifs_en_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x04000000)) >> 26);
}
/**
* @brief Sets the rxRIFSEn field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] rxrifsen - The value to set the field to.
*/
__INLINE void nxmac_rx_rifs_en_setf(uint8_t rxrifsen)
{
ASSERT_ERR((((uint32_t)rxrifsen << 26) & ~((uint32_t)0x04000000)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x04000000)) | ((uint32_t)rxrifsen << 26));
}
/**
* @brief Returns the current value of the tsfMgtDisable field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the tsfMgtDisable field's value will be returned.
*
* @return The current value of the tsfMgtDisable field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_tsf_mgt_disable_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x02000000)) >> 25);
}
/**
* @brief Sets the tsfMgtDisable field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] tsfmgtdisable - The value to set the field to.
*/
__INLINE void nxmac_tsf_mgt_disable_setf(uint8_t tsfmgtdisable)
{
ASSERT_ERR((((uint32_t)tsfmgtdisable << 25) & ~((uint32_t)0x02000000)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x02000000)) | ((uint32_t)tsfmgtdisable << 25));
}
/**
* @brief Returns the current value of the tsfUpdatedBySW field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the tsfUpdatedBySW field's value will be returned.
*
* @return The current value of the tsfUpdatedBySW field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_tsf_updated_by_sw_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x01000000)) >> 24);
}
/**
* @brief Sets the tsfUpdatedBySW field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] tsfupdatedbysw - The value to set the field to.
*/
__INLINE void nxmac_tsf_updated_by_sw_setf(uint8_t tsfupdatedbysw)
{
ASSERT_ERR((((uint32_t)tsfupdatedbysw << 24) & ~((uint32_t)0x01000000)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x01000000)) | ((uint32_t)tsfupdatedbysw << 24));
}
/**
* @brief Returns the current value of the abgnMode field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the abgnMode field's value will be returned.
*
* @return The current value of the abgnMode field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_abgn_mode_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x0001C000)) >> 14);
}
/**
* @brief Sets the abgnMode field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] abgnmode - The value to set the field to.
*/
__INLINE void nxmac_abgn_mode_setf(uint8_t abgnmode)
{
ASSERT_ERR((((uint32_t)abgnmode << 14) & ~((uint32_t)0x0001C000)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x0001C000)) | ((uint32_t)abgnmode << 14));
}
/**
* @brief Returns the current value of the keyStoRAMReset field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the keyStoRAMReset field's value will be returned.
*
* @return The current value of the keyStoRAMReset field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_key_sto_ram_reset_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00002000)) >> 13);
}
/**
* @brief Sets the keyStoRAMReset field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] keystoramreset - The value to set the field to.
*/
__INLINE void nxmac_key_sto_ram_reset_setf(uint8_t keystoramreset)
{
ASSERT_ERR((((uint32_t)keystoramreset << 13) & ~((uint32_t)0x00002000)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00002000)) | ((uint32_t)keystoramreset << 13));
}
/**
* @brief Returns the current value of the mibTableReset field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the mibTableReset field's value will be returned.
*
* @return The current value of the mibTableReset field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_mib_table_reset_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00001000)) >> 12);
}
/**
* @brief Sets the mibTableReset field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] mibtablereset - The value to set the field to.
*/
__INLINE void nxmac_mib_table_reset_setf(uint8_t mibtablereset)
{
ASSERT_ERR((((uint32_t)mibtablereset << 12) & ~((uint32_t)0x00001000)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00001000)) | ((uint32_t)mibtablereset << 12));
}
/**
* @brief Returns the current value of the rateControllerMPIF field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the rateControllerMPIF field's value will be returned.
*
* @return The current value of the rateControllerMPIF field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_rate_controller_mpif_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00000800)) >> 11);
}
/**
* @brief Sets the rateControllerMPIF field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] ratecontrollermpif - The value to set the field to.
*/
__INLINE void nxmac_rate_controller_mpif_setf(uint8_t ratecontrollermpif)
{
ASSERT_ERR((((uint32_t)ratecontrollermpif << 11) & ~((uint32_t)0x00000800)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00000800)) | ((uint32_t)ratecontrollermpif << 11));
}
/**
* @brief Returns the current value of the disableBAResp field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the disableBAResp field's value will be returned.
*
* @return The current value of the disableBAResp field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_disable_ba_resp_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00000400)) >> 10);
}
/**
* @brief Sets the disableBAResp field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] disablebaresp - The value to set the field to.
*/
__INLINE void nxmac_disable_ba_resp_setf(uint8_t disablebaresp)
{
ASSERT_ERR((((uint32_t)disablebaresp << 10) & ~((uint32_t)0x00000400)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00000400)) | ((uint32_t)disablebaresp << 10));
}
/**
* @brief Returns the current value of the disableCTSResp field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the disableCTSResp field's value will be returned.
*
* @return The current value of the disableCTSResp field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_disable_cts_resp_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00000200)) >> 9);
}
/**
* @brief Sets the disableCTSResp field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] disablectsresp - The value to set the field to.
*/
__INLINE void nxmac_disable_cts_resp_setf(uint8_t disablectsresp)
{
ASSERT_ERR((((uint32_t)disablectsresp << 9) & ~((uint32_t)0x00000200)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00000200)) | ((uint32_t)disablectsresp << 9));
}
/**
* @brief Returns the current value of the disableACKResp field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the disableACKResp field's value will be returned.
*
* @return The current value of the disableACKResp field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_disable_ack_resp_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00000100)) >> 8);
}
/**
* @brief Sets the disableACKResp field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] disableackresp - The value to set the field to.
*/
__INLINE void nxmac_disable_ack_resp_setf(uint8_t disableackresp)
{
ASSERT_ERR((((uint32_t)disableackresp << 8) & ~((uint32_t)0x00000100)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00000100)) | ((uint32_t)disableackresp << 8));
}
/**
* @brief Returns the current value of the activeClkGating field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the activeClkGating field's value will be returned.
*
* @return The current value of the activeClkGating field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_active_clk_gating_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00000080)) >> 7);
}
/**
* @brief Sets the activeClkGating field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] activeclkgating - The value to set the field to.
*/
__INLINE void nxmac_active_clk_gating_setf(uint8_t activeclkgating)
{
ASSERT_ERR((((uint32_t)activeclkgating << 7) & ~((uint32_t)0x00000080)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00000080)) | ((uint32_t)activeclkgating << 7));
}
/**
* @brief Returns the current value of the enableLPClkSwitch field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the enableLPClkSwitch field's value will be returned.
*
* @return The current value of the enableLPClkSwitch field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_enable_lp_clk_switch_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00000040)) >> 6);
}
/**
* @brief Sets the enableLPClkSwitch field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] enablelpclkswitch - The value to set the field to.
*/
__INLINE void nxmac_enable_lp_clk_switch_setf(uint8_t enablelpclkswitch)
{
ASSERT_ERR((((uint32_t)enablelpclkswitch << 6) & ~((uint32_t)0x00000040)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00000040)) | ((uint32_t)enablelpclkswitch << 6));
}
/**
* @brief Returns the current value of the lpClk32786Hz field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the lpClk32786Hz field's value will be returned.
*
* @return The current value of the lpClk32786Hz field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_lp_clk_32786_hz_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00000020)) >> 5);
}
/**
* @brief Sets the lpClk32786Hz field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] lpclk32786hz - The value to set the field to.
*/
__INLINE void nxmac_lp_clk_32786_hz_setf(uint8_t lpclk32786hz)
{
ASSERT_ERR((((uint32_t)lpclk32786hz << 5) & ~((uint32_t)0x00000020)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00000020)) | ((uint32_t)lpclk32786hz << 5));
}
/**
* @brief Returns the current value of the cfpAware field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the cfpAware field's value will be returned.
*
* @return The current value of the cfpAware field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_cfp_aware_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00000008)) >> 3);
}
/**
* @brief Sets the cfpAware field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] cfpaware - The value to set the field to.
*/
__INLINE void nxmac_cfp_aware_setf(uint8_t cfpaware)
{
ASSERT_ERR((((uint32_t)cfpaware << 3) & ~((uint32_t)0x00000008)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00000008)) | ((uint32_t)cfpaware << 3));
}
/**
* @brief Returns the current value of the pwrMgt field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the pwrMgt field's value will be returned.
*
* @return The current value of the pwrMgt field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_pwr_mgt_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00000004)) >> 2);
}
/**
* @brief Sets the pwrMgt field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] pwrmgt - The value to set the field to.
*/
__INLINE void nxmac_pwr_mgt_setf(uint8_t pwrmgt)
{
ASSERT_ERR((((uint32_t)pwrmgt << 2) & ~((uint32_t)0x00000004)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00000004)) | ((uint32_t)pwrmgt << 2));
}
/**
* @brief Returns the current value of the ap field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the ap field's value will be returned.
*
* @return The current value of the ap field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_ap_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00000002)) >> 1);
}
/**
* @brief Sets the ap field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] ap - The value to set the field to.
*/
__INLINE void nxmac_ap_setf(uint8_t ap)
{
ASSERT_ERR((((uint32_t)ap << 1) & ~((uint32_t)0x00000002)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)ap << 1));
}
/**
* @brief Returns the current value of the bssType field in the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read and the bssType field's value will be returned.
*
* @return The current value of the bssType field in the MAC_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_bss_type_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00000001)) >> 0);
}
/**
* @brief Sets the bssType field of the MAC_CNTRL_1 register.
*
* The MAC_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] bsstype - The value to set the field to.
*/
__INLINE void nxmac_bss_type_setf(uint8_t bsstype)
{
ASSERT_ERR((((uint32_t)bsstype << 0) & ~((uint32_t)0x00000001)) == 0);
REG_PL_WR(NXMAC_MAC_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_MAC_CNTRL_1_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)bsstype << 0));
}
/// @}
/**
* @name MAC_ERR_REC_CNTRL register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 16 rxFlowCntrlEn 0
* 07 baPSBitmapReset 0
* 06 encrRxFIFOReset 0
* 05 macPHYIFFIFOReset 0
* 04 txFIFOReset 0
* 03 rxFIFOReset 0
* 02 hwFSMReset 0
* 01 useErrDet 0
* 00 useErrRec 0
* </pre>
*
* @{
*/
/// Address of the MAC_ERR_REC_CNTRL register
#define NXMAC_MAC_ERR_REC_CNTRL_ADDR 0xC0000054
/// Offset of the MAC_ERR_REC_CNTRL register from the base address
#define NXMAC_MAC_ERR_REC_CNTRL_OFFSET 0x00000054
/// Index of the MAC_ERR_REC_CNTRL register
#define NXMAC_MAC_ERR_REC_CNTRL_INDEX 0x00000015
/// Reset value of the MAC_ERR_REC_CNTRL register
#define NXMAC_MAC_ERR_REC_CNTRL_RESET 0x00000000
/**
* @brief Returns the current value of the MAC_ERR_REC_CNTRL register.
* The MAC_ERR_REC_CNTRL register will be read and its value returned.
* @return The current value of the MAC_ERR_REC_CNTRL register.
*/
__INLINE uint32_t nxmac_mac_err_rec_cntrl_get(void)
{
return REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR);
}
/**
* @brief Sets the MAC_ERR_REC_CNTRL register to a value.
* The MAC_ERR_REC_CNTRL register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_mac_err_rec_cntrl_set(uint32_t value)
{
REG_PL_WR(NXMAC_MAC_ERR_REC_CNTRL_ADDR, value);
}
// field definitions
/// RX_FLOW_CNTRL_EN field bit
#define NXMAC_RX_FLOW_CNTRL_EN_BIT ((uint32_t)0x00010000)
/// RX_FLOW_CNTRL_EN field position
#define NXMAC_RX_FLOW_CNTRL_EN_POS 16
/// BA_PS_BITMAP_RESET field bit
#define NXMAC_BA_PS_BITMAP_RESET_BIT ((uint32_t)0x00000080)
/// BA_PS_BITMAP_RESET field position
#define NXMAC_BA_PS_BITMAP_RESET_POS 7
/// ENCR_RX_FIFO_RESET field bit
#define NXMAC_ENCR_RX_FIFO_RESET_BIT ((uint32_t)0x00000040)
/// ENCR_RX_FIFO_RESET field position
#define NXMAC_ENCR_RX_FIFO_RESET_POS 6
/// MAC_PHYIFFIFO_RESET field bit
#define NXMAC_MAC_PHYIFFIFO_RESET_BIT ((uint32_t)0x00000020)
/// MAC_PHYIFFIFO_RESET field position
#define NXMAC_MAC_PHYIFFIFO_RESET_POS 5
/// TX_FIFO_RESET field bit
#define NXMAC_TX_FIFO_RESET_BIT ((uint32_t)0x00000010)
/// TX_FIFO_RESET field position
#define NXMAC_TX_FIFO_RESET_POS 4
/// RX_FIFO_RESET field bit
#define NXMAC_RX_FIFO_RESET_BIT ((uint32_t)0x00000008)
/// RX_FIFO_RESET field position
#define NXMAC_RX_FIFO_RESET_POS 3
/// HW_FSM_RESET field bit
#define NXMAC_HW_FSM_RESET_BIT ((uint32_t)0x00000004)
/// HW_FSM_RESET field position
#define NXMAC_HW_FSM_RESET_POS 2
/// USE_ERR_DET field bit
#define NXMAC_USE_ERR_DET_BIT ((uint32_t)0x00000002)
/// USE_ERR_DET field position
#define NXMAC_USE_ERR_DET_POS 1
/// USE_ERR_REC field bit
#define NXMAC_USE_ERR_REC_BIT ((uint32_t)0x00000001)
/// USE_ERR_REC field position
#define NXMAC_USE_ERR_REC_POS 0
/// RX_FLOW_CNTRL_EN field reset value
#define NXMAC_RX_FLOW_CNTRL_EN_RST 0x0
/// BA_PS_BITMAP_RESET field reset value
#define NXMAC_BA_PS_BITMAP_RESET_RST 0x0
/// ENCR_RX_FIFO_RESET field reset value
#define NXMAC_ENCR_RX_FIFO_RESET_RST 0x0
/// MAC_PHYIFFIFO_RESET field reset value
#define NXMAC_MAC_PHYIFFIFO_RESET_RST 0x0
/// TX_FIFO_RESET field reset value
#define NXMAC_TX_FIFO_RESET_RST 0x0
/// RX_FIFO_RESET field reset value
#define NXMAC_RX_FIFO_RESET_RST 0x0
/// HW_FSM_RESET field reset value
#define NXMAC_HW_FSM_RESET_RST 0x0
/// USE_ERR_DET field reset value
#define NXMAC_USE_ERR_DET_RST 0x0
/// USE_ERR_REC field reset value
#define NXMAC_USE_ERR_REC_RST 0x0
/**
* @brief Constructs a value for the MAC_ERR_REC_CNTRL register given values for its fields
* and writes the value to the register.
*
* @param[in] rxflowcntrlen - The value to use for the rxFlowCntrlEn field.
* @param[in] bapsbitmapreset - The value to use for the baPSBitmapReset field.
* @param[in] encrrxfiforeset - The value to use for the encrRxFIFOReset field.
* @param[in] macphyiffiforeset - The value to use for the macPHYIFFIFOReset field.
* @param[in] txfiforeset - The value to use for the txFIFOReset field.
* @param[in] rxfiforeset - The value to use for the rxFIFOReset field.
* @param[in] hwfsmreset - The value to use for the hwFSMReset field.
* @param[in] useerrdet - The value to use for the useErrDet field.
*/
__INLINE void nxmac_mac_err_rec_cntrl_pack(uint8_t rxflowcntrlen, uint8_t bapsbitmapreset, uint8_t encrrxfiforeset, uint8_t macphyiffiforeset, uint8_t txfiforeset, uint8_t rxfiforeset, uint8_t hwfsmreset, uint8_t useerrdet)
{
ASSERT_ERR((((uint32_t)rxflowcntrlen << 16) & ~((uint32_t)0x00010000)) == 0);
ASSERT_ERR((((uint32_t)bapsbitmapreset << 7) & ~((uint32_t)0x00000080)) == 0);
ASSERT_ERR((((uint32_t)encrrxfiforeset << 6) & ~((uint32_t)0x00000040)) == 0);
ASSERT_ERR((((uint32_t)macphyiffiforeset << 5) & ~((uint32_t)0x00000020)) == 0);
ASSERT_ERR((((uint32_t)txfiforeset << 4) & ~((uint32_t)0x00000010)) == 0);
ASSERT_ERR((((uint32_t)rxfiforeset << 3) & ~((uint32_t)0x00000008)) == 0);
ASSERT_ERR((((uint32_t)hwfsmreset << 2) & ~((uint32_t)0x00000004)) == 0);
ASSERT_ERR((((uint32_t)useerrdet << 1) & ~((uint32_t)0x00000002)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_REC_CNTRL_ADDR, ((uint32_t)rxflowcntrlen << 16) | ((uint32_t)bapsbitmapreset << 7) | ((uint32_t)encrrxfiforeset << 6) | ((uint32_t)macphyiffiforeset << 5) | ((uint32_t)txfiforeset << 4) | ((uint32_t)rxfiforeset << 3) | ((uint32_t)hwfsmreset << 2) | ((uint32_t)useerrdet << 1));
}
/**
* @brief Unpacks MAC_ERR_REC_CNTRL's fields from current value of the MAC_ERR_REC_CNTRL register.
*
* Reads the MAC_ERR_REC_CNTRL register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] rxflowcntrlen - Will be populated with the current value of this field from the register.
* @param[out] bapsbitmapreset - Will be populated with the current value of this field from the register.
* @param[out] encrrxfiforeset - Will be populated with the current value of this field from the register.
* @param[out] macphyiffiforeset - Will be populated with the current value of this field from the register.
* @param[out] txfiforeset - Will be populated with the current value of this field from the register.
* @param[out] rxfiforeset - Will be populated with the current value of this field from the register.
* @param[out] hwfsmreset - Will be populated with the current value of this field from the register.
* @param[out] useerrdet - Will be populated with the current value of this field from the register.
* @param[out] useerrrec - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_mac_err_rec_cntrl_unpack(uint8_t *rxflowcntrlen, uint8_t *bapsbitmapreset, uint8_t *encrrxfiforeset, uint8_t *macphyiffiforeset, uint8_t *txfiforeset, uint8_t *rxfiforeset, uint8_t *hwfsmreset, uint8_t *useerrdet, uint8_t *useerrrec)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR);
*rxflowcntrlen = (localVal & ((uint32_t)0x00010000)) >> 16;
*bapsbitmapreset = (localVal & ((uint32_t)0x00000080)) >> 7;
*encrrxfiforeset = (localVal & ((uint32_t)0x00000040)) >> 6;
*macphyiffiforeset = (localVal & ((uint32_t)0x00000020)) >> 5;
*txfiforeset = (localVal & ((uint32_t)0x00000010)) >> 4;
*rxfiforeset = (localVal & ((uint32_t)0x00000008)) >> 3;
*hwfsmreset = (localVal & ((uint32_t)0x00000004)) >> 2;
*useerrdet = (localVal & ((uint32_t)0x00000002)) >> 1;
*useerrrec = (localVal & ((uint32_t)0x00000001)) >> 0;
}
/**
* @brief Returns the current value of the rxFlowCntrlEn field in the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read and the rxFlowCntrlEn field's value will be returned.
*
* @return The current value of the rxFlowCntrlEn field in the MAC_ERR_REC_CNTRL register.
*/
__INLINE uint8_t nxmac_rx_flow_cntrl_en_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00010000)) >> 16);
}
/**
* @brief Sets the rxFlowCntrlEn field of the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] rxflowcntrlen - The value to set the field to.
*/
__INLINE void nxmac_rx_flow_cntrl_en_setf(uint8_t rxflowcntrlen)
{
ASSERT_ERR((((uint32_t)rxflowcntrlen << 16) & ~((uint32_t)0x00010000)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_REC_CNTRL_ADDR, (REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR) & ~((uint32_t)0x00010000)) | ((uint32_t)rxflowcntrlen << 16));
}
/**
* @brief Returns the current value of the baPSBitmapReset field in the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read and the baPSBitmapReset field's value will be returned.
*
* @return The current value of the baPSBitmapReset field in the MAC_ERR_REC_CNTRL register.
*/
__INLINE uint8_t nxmac_ba_ps_bitmap_reset_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000080)) >> 7);
}
/**
* @brief Sets the baPSBitmapReset field of the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] bapsbitmapreset - The value to set the field to.
*/
__INLINE void nxmac_ba_ps_bitmap_reset_setf(uint8_t bapsbitmapreset)
{
ASSERT_ERR((((uint32_t)bapsbitmapreset << 7) & ~((uint32_t)0x00000080)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_REC_CNTRL_ADDR, (REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR) & ~((uint32_t)0x00000080)) | ((uint32_t)bapsbitmapreset << 7));
}
/**
* @brief Returns the current value of the encrRxFIFOReset field in the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read and the encrRxFIFOReset field's value will be returned.
*
* @return The current value of the encrRxFIFOReset field in the MAC_ERR_REC_CNTRL register.
*/
__INLINE uint8_t nxmac_encr_rx_fifo_reset_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000040)) >> 6);
}
/**
* @brief Sets the encrRxFIFOReset field of the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] encrrxfiforeset - The value to set the field to.
*/
__INLINE void nxmac_encr_rx_fifo_reset_setf(uint8_t encrrxfiforeset)
{
ASSERT_ERR((((uint32_t)encrrxfiforeset << 6) & ~((uint32_t)0x00000040)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_REC_CNTRL_ADDR, (REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR) & ~((uint32_t)0x00000040)) | ((uint32_t)encrrxfiforeset << 6));
}
/**
* @brief Returns the current value of the macPHYIFFIFOReset field in the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read and the macPHYIFFIFOReset field's value will be returned.
*
* @return The current value of the macPHYIFFIFOReset field in the MAC_ERR_REC_CNTRL register.
*/
__INLINE uint8_t nxmac_mac_phyiffifo_reset_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000020)) >> 5);
}
/**
* @brief Sets the macPHYIFFIFOReset field of the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] macphyiffiforeset - The value to set the field to.
*/
__INLINE void nxmac_mac_phyiffifo_reset_setf(uint8_t macphyiffiforeset)
{
ASSERT_ERR((((uint32_t)macphyiffiforeset << 5) & ~((uint32_t)0x00000020)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_REC_CNTRL_ADDR, (REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR) & ~((uint32_t)0x00000020)) | ((uint32_t)macphyiffiforeset << 5));
}
/**
* @brief Returns the current value of the txFIFOReset field in the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read and the txFIFOReset field's value will be returned.
*
* @return The current value of the txFIFOReset field in the MAC_ERR_REC_CNTRL register.
*/
__INLINE uint8_t nxmac_tx_fifo_reset_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000010)) >> 4);
}
/**
* @brief Sets the txFIFOReset field of the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] txfiforeset - The value to set the field to.
*/
__INLINE void nxmac_tx_fifo_reset_setf(uint8_t txfiforeset)
{
ASSERT_ERR((((uint32_t)txfiforeset << 4) & ~((uint32_t)0x00000010)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_REC_CNTRL_ADDR, (REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR) & ~((uint32_t)0x00000010)) | ((uint32_t)txfiforeset << 4));
}
/**
* @brief Returns the current value of the rxFIFOReset field in the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read and the rxFIFOReset field's value will be returned.
*
* @return The current value of the rxFIFOReset field in the MAC_ERR_REC_CNTRL register.
*/
__INLINE uint8_t nxmac_rx_fifo_reset_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000008)) >> 3);
}
/**
* @brief Sets the rxFIFOReset field of the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] rxfiforeset - The value to set the field to.
*/
__INLINE void nxmac_rx_fifo_reset_setf(uint8_t rxfiforeset)
{
ASSERT_ERR((((uint32_t)rxfiforeset << 3) & ~((uint32_t)0x00000008)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_REC_CNTRL_ADDR, (REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR) & ~((uint32_t)0x00000008)) | ((uint32_t)rxfiforeset << 3));
}
/**
* @brief Returns the current value of the hwFSMReset field in the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read and the hwFSMReset field's value will be returned.
*
* @return The current value of the hwFSMReset field in the MAC_ERR_REC_CNTRL register.
*/
__INLINE uint8_t nxmac_hw_fsm_reset_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000004)) >> 2);
}
/**
* @brief Sets the hwFSMReset field of the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] hwfsmreset - The value to set the field to.
*/
__INLINE void nxmac_hw_fsm_reset_setf(uint8_t hwfsmreset)
{
ASSERT_ERR((((uint32_t)hwfsmreset << 2) & ~((uint32_t)0x00000004)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_REC_CNTRL_ADDR, (REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR) & ~((uint32_t)0x00000004)) | ((uint32_t)hwfsmreset << 2));
}
/**
* @brief Returns the current value of the useErrDet field in the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read and the useErrDet field's value will be returned.
*
* @return The current value of the useErrDet field in the MAC_ERR_REC_CNTRL register.
*/
__INLINE uint8_t nxmac_use_err_det_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000002)) >> 1);
}
/**
* @brief Sets the useErrDet field of the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] useerrdet - The value to set the field to.
*/
__INLINE void nxmac_use_err_det_setf(uint8_t useerrdet)
{
ASSERT_ERR((((uint32_t)useerrdet << 1) & ~((uint32_t)0x00000002)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_REC_CNTRL_ADDR, (REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)useerrdet << 1));
}
/**
* @brief Returns the current value of the useErrRec field in the MAC_ERR_REC_CNTRL register.
*
* The MAC_ERR_REC_CNTRL register will be read and the useErrRec field's value will be returned.
*
* @return The current value of the useErrRec field in the MAC_ERR_REC_CNTRL register.
*/
__INLINE uint8_t nxmac_use_err_rec_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_REC_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000001)) >> 0);
}
/// @}
/**
* @name MAC_ERR_SET_STATUS register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03 errInHWLevel3 0
* 02 errInTxRxLevel2 0
* 01 errInRxLevel1 0
* 00 errInTxLevel1 0
* </pre>
*
* @{
*/
/// Address of the MAC_ERR_SET_STATUS register
#define NXMAC_MAC_ERR_SET_STATUS_ADDR 0xC0000058
/// Offset of the MAC_ERR_SET_STATUS register from the base address
#define NXMAC_MAC_ERR_SET_STATUS_OFFSET 0x00000058
/// Index of the MAC_ERR_SET_STATUS register
#define NXMAC_MAC_ERR_SET_STATUS_INDEX 0x00000016
/// Reset value of the MAC_ERR_SET_STATUS register
#define NXMAC_MAC_ERR_SET_STATUS_RESET 0x00000000
/**
* @brief Returns the current value of the MAC_ERR_SET_STATUS register.
* The MAC_ERR_SET_STATUS register will be read and its value returned.
* @return The current value of the MAC_ERR_SET_STATUS register.
*/
__INLINE uint32_t nxmac_mac_err_set_status_get(void)
{
return REG_PL_RD(NXMAC_MAC_ERR_SET_STATUS_ADDR);
}
/**
* @brief Sets the MAC_ERR_SET_STATUS register to a value.
* The MAC_ERR_SET_STATUS register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_mac_err_set_status_set(uint32_t value)
{
REG_PL_WR(NXMAC_MAC_ERR_SET_STATUS_ADDR, value);
}
// field definitions
/// ERR_IN_HW_LEVEL_3 field bit
#define NXMAC_ERR_IN_HW_LEVEL_3_BIT ((uint32_t)0x00000008)
/// ERR_IN_HW_LEVEL_3 field position
#define NXMAC_ERR_IN_HW_LEVEL_3_POS 3
/// ERR_IN_TX_RX_LEVEL_2 field bit
#define NXMAC_ERR_IN_TX_RX_LEVEL_2_BIT ((uint32_t)0x00000004)
/// ERR_IN_TX_RX_LEVEL_2 field position
#define NXMAC_ERR_IN_TX_RX_LEVEL_2_POS 2
/// ERR_IN_RX_LEVEL_1 field bit
#define NXMAC_ERR_IN_RX_LEVEL_1_BIT ((uint32_t)0x00000002)
/// ERR_IN_RX_LEVEL_1 field position
#define NXMAC_ERR_IN_RX_LEVEL_1_POS 1
/// ERR_IN_TX_LEVEL_1 field bit
#define NXMAC_ERR_IN_TX_LEVEL_1_BIT ((uint32_t)0x00000001)
/// ERR_IN_TX_LEVEL_1 field position
#define NXMAC_ERR_IN_TX_LEVEL_1_POS 0
/// ERR_IN_HW_LEVEL_3 field reset value
#define NXMAC_ERR_IN_HW_LEVEL_3_RST 0x0
/// ERR_IN_TX_RX_LEVEL_2 field reset value
#define NXMAC_ERR_IN_TX_RX_LEVEL_2_RST 0x0
/// ERR_IN_RX_LEVEL_1 field reset value
#define NXMAC_ERR_IN_RX_LEVEL_1_RST 0x0
/// ERR_IN_TX_LEVEL_1 field reset value
#define NXMAC_ERR_IN_TX_LEVEL_1_RST 0x0
/**
* @brief Constructs a value for the MAC_ERR_SET_STATUS register given values for its fields
* and writes the value to the register.
*
* @param[in] errinhwlevel3 - The value to use for the errInHWLevel3 field.
* @param[in] errintxrxlevel2 - The value to use for the errInTxRxLevel2 field.
* @param[in] errinrxlevel1 - The value to use for the errInRxLevel1 field.
* @param[in] errintxlevel1 - The value to use for the errInTxLevel1 field.
*/
__INLINE void nxmac_mac_err_set_status_pack(uint8_t errinhwlevel3, uint8_t errintxrxlevel2, uint8_t errinrxlevel1, uint8_t errintxlevel1)
{
ASSERT_ERR((((uint32_t)errinhwlevel3 << 3) & ~((uint32_t)0x00000008)) == 0);
ASSERT_ERR((((uint32_t)errintxrxlevel2 << 2) & ~((uint32_t)0x00000004)) == 0);
ASSERT_ERR((((uint32_t)errinrxlevel1 << 1) & ~((uint32_t)0x00000002)) == 0);
ASSERT_ERR((((uint32_t)errintxlevel1 << 0) & ~((uint32_t)0x00000001)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_SET_STATUS_ADDR, ((uint32_t)errinhwlevel3 << 3) | ((uint32_t)errintxrxlevel2 << 2) | ((uint32_t)errinrxlevel1 << 1) | ((uint32_t)errintxlevel1 << 0));
}
/**
* @brief Unpacks MAC_ERR_SET_STATUS's fields from current value of the MAC_ERR_SET_STATUS register.
*
* Reads the MAC_ERR_SET_STATUS register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] errinhwlevel3 - Will be populated with the current value of this field from the register.
* @param[out] errintxrxlevel2 - Will be populated with the current value of this field from the register.
* @param[out] errinrxlevel1 - Will be populated with the current value of this field from the register.
* @param[out] errintxlevel1 - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_mac_err_set_status_unpack(uint8_t *errinhwlevel3, uint8_t *errintxrxlevel2, uint8_t *errinrxlevel1, uint8_t *errintxlevel1)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_SET_STATUS_ADDR);
*errinhwlevel3 = (localVal & ((uint32_t)0x00000008)) >> 3;
*errintxrxlevel2 = (localVal & ((uint32_t)0x00000004)) >> 2;
*errinrxlevel1 = (localVal & ((uint32_t)0x00000002)) >> 1;
*errintxlevel1 = (localVal & ((uint32_t)0x00000001)) >> 0;
}
/**
* @brief Returns the current value of the errInHWLevel3 field in the MAC_ERR_SET_STATUS register.
*
* The MAC_ERR_SET_STATUS register will be read and the errInHWLevel3 field's value will be returned.
*
* @return The current value of the errInHWLevel3 field in the MAC_ERR_SET_STATUS register.
*/
__INLINE uint8_t nxmac_err_in_hw_level_3_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_SET_STATUS_ADDR);
return ((localVal & ((uint32_t)0x00000008)) >> 3);
}
/**
* @brief Sets the errInHWLevel3 field of the MAC_ERR_SET_STATUS register.
*
* The MAC_ERR_SET_STATUS register will be read, modified to contain the new field value, and written.
*
* @param[in] errinhwlevel3 - The value to set the field to.
*/
__INLINE void nxmac_err_in_hw_level_3_setf(uint8_t errinhwlevel3)
{
ASSERT_ERR((((uint32_t)errinhwlevel3 << 3) & ~((uint32_t)0x00000008)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_SET_STATUS_ADDR, (uint32_t)errinhwlevel3 << 3);
}
/**
* @brief Returns the current value of the errInTxRxLevel2 field in the MAC_ERR_SET_STATUS register.
*
* The MAC_ERR_SET_STATUS register will be read and the errInTxRxLevel2 field's value will be returned.
*
* @return The current value of the errInTxRxLevel2 field in the MAC_ERR_SET_STATUS register.
*/
__INLINE uint8_t nxmac_err_in_tx_rx_level_2_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_SET_STATUS_ADDR);
return ((localVal & ((uint32_t)0x00000004)) >> 2);
}
/**
* @brief Sets the errInTxRxLevel2 field of the MAC_ERR_SET_STATUS register.
*
* The MAC_ERR_SET_STATUS register will be read, modified to contain the new field value, and written.
*
* @param[in] errintxrxlevel2 - The value to set the field to.
*/
__INLINE void nxmac_err_in_tx_rx_level_2_setf(uint8_t errintxrxlevel2)
{
ASSERT_ERR((((uint32_t)errintxrxlevel2 << 2) & ~((uint32_t)0x00000004)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_SET_STATUS_ADDR, (uint32_t)errintxrxlevel2 << 2);
}
/**
* @brief Returns the current value of the errInRxLevel1 field in the MAC_ERR_SET_STATUS register.
*
* The MAC_ERR_SET_STATUS register will be read and the errInRxLevel1 field's value will be returned.
*
* @return The current value of the errInRxLevel1 field in the MAC_ERR_SET_STATUS register.
*/
__INLINE uint8_t nxmac_err_in_rx_level_1_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_SET_STATUS_ADDR);
return ((localVal & ((uint32_t)0x00000002)) >> 1);
}
/**
* @brief Sets the errInRxLevel1 field of the MAC_ERR_SET_STATUS register.
*
* The MAC_ERR_SET_STATUS register will be read, modified to contain the new field value, and written.
*
* @param[in] errinrxlevel1 - The value to set the field to.
*/
__INLINE void nxmac_err_in_rx_level_1_setf(uint8_t errinrxlevel1)
{
ASSERT_ERR((((uint32_t)errinrxlevel1 << 1) & ~((uint32_t)0x00000002)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_SET_STATUS_ADDR, (uint32_t)errinrxlevel1 << 1);
}
/**
* @brief Returns the current value of the errInTxLevel1 field in the MAC_ERR_SET_STATUS register.
*
* The MAC_ERR_SET_STATUS register will be read and the errInTxLevel1 field's value will be returned.
*
* @return The current value of the errInTxLevel1 field in the MAC_ERR_SET_STATUS register.
*/
__INLINE uint8_t nxmac_err_in_tx_level_1_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_SET_STATUS_ADDR);
return ((localVal & ((uint32_t)0x00000001)) >> 0);
}
/**
* @brief Sets the errInTxLevel1 field of the MAC_ERR_SET_STATUS register.
*
* The MAC_ERR_SET_STATUS register will be read, modified to contain the new field value, and written.
*
* @param[in] errintxlevel1 - The value to set the field to.
*/
__INLINE void nxmac_err_in_tx_level_1_setf(uint8_t errintxlevel1)
{
ASSERT_ERR((((uint32_t)errintxlevel1 << 0) & ~((uint32_t)0x00000001)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_SET_STATUS_ADDR, (uint32_t)errintxlevel1 << 0);
}
/// @}
/**
* @name MAC_ERR_CLEAR_STATUS register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 03 clearErrInHWLevel3 0
* 02 clearErrInTxRxLevel2 0
* 01 clearErrInRxLevel1 0
* 00 clearErrInTxLevel1 0
* </pre>
*
* @{
*/
/// Address of the MAC_ERR_CLEAR_STATUS register
#define NXMAC_MAC_ERR_CLEAR_STATUS_ADDR 0xC000005C
/// Offset of the MAC_ERR_CLEAR_STATUS register from the base address
#define NXMAC_MAC_ERR_CLEAR_STATUS_OFFSET 0x0000005C
/// Index of the MAC_ERR_CLEAR_STATUS register
#define NXMAC_MAC_ERR_CLEAR_STATUS_INDEX 0x00000017
/// Reset value of the MAC_ERR_CLEAR_STATUS register
#define NXMAC_MAC_ERR_CLEAR_STATUS_RESET 0x00000000
/**
* @brief Returns the current value of the MAC_ERR_CLEAR_STATUS register.
* The MAC_ERR_CLEAR_STATUS register will be read and its value returned.
* @return The current value of the MAC_ERR_CLEAR_STATUS register.
*/
__INLINE uint32_t nxmac_mac_err_clear_status_get(void)
{
return REG_PL_RD(NXMAC_MAC_ERR_CLEAR_STATUS_ADDR);
}
/**
* @brief Sets the MAC_ERR_CLEAR_STATUS register to a value.
* The MAC_ERR_CLEAR_STATUS register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_mac_err_clear_status_clear(uint32_t value)
{
REG_PL_WR(NXMAC_MAC_ERR_CLEAR_STATUS_ADDR, value);
}
// field definitions
/// CLEAR_ERR_IN_HW_LEVEL_3 field bit
#define NXMAC_CLEAR_ERR_IN_HW_LEVEL_3_BIT ((uint32_t)0x00000008)
/// CLEAR_ERR_IN_HW_LEVEL_3 field position
#define NXMAC_CLEAR_ERR_IN_HW_LEVEL_3_POS 3
/// CLEAR_ERR_IN_TX_RX_LEVEL_2 field bit
#define NXMAC_CLEAR_ERR_IN_TX_RX_LEVEL_2_BIT ((uint32_t)0x00000004)
/// CLEAR_ERR_IN_TX_RX_LEVEL_2 field position
#define NXMAC_CLEAR_ERR_IN_TX_RX_LEVEL_2_POS 2
/// CLEAR_ERR_IN_RX_LEVEL_1 field bit
#define NXMAC_CLEAR_ERR_IN_RX_LEVEL_1_BIT ((uint32_t)0x00000002)
/// CLEAR_ERR_IN_RX_LEVEL_1 field position
#define NXMAC_CLEAR_ERR_IN_RX_LEVEL_1_POS 1
/// CLEAR_ERR_IN_TX_LEVEL_1 field bit
#define NXMAC_CLEAR_ERR_IN_TX_LEVEL_1_BIT ((uint32_t)0x00000001)
/// CLEAR_ERR_IN_TX_LEVEL_1 field position
#define NXMAC_CLEAR_ERR_IN_TX_LEVEL_1_POS 0
/// CLEAR_ERR_IN_HW_LEVEL_3 field reset value
#define NXMAC_CLEAR_ERR_IN_HW_LEVEL_3_RST 0x0
/// CLEAR_ERR_IN_TX_RX_LEVEL_2 field reset value
#define NXMAC_CLEAR_ERR_IN_TX_RX_LEVEL_2_RST 0x0
/// CLEAR_ERR_IN_RX_LEVEL_1 field reset value
#define NXMAC_CLEAR_ERR_IN_RX_LEVEL_1_RST 0x0
/// CLEAR_ERR_IN_TX_LEVEL_1 field reset value
#define NXMAC_CLEAR_ERR_IN_TX_LEVEL_1_RST 0x0
/**
* @brief Constructs a value for the MAC_ERR_CLEAR_STATUS register given values for its fields
* and writes the value to the register.
*
* @param[in] clearerrinhwlevel3 - The value to use for the clearErrInHWLevel3 field.
* @param[in] clearerrintxrxlevel2 - The value to use for the clearErrInTxRxLevel2 field.
* @param[in] clearerrinrxlevel1 - The value to use for the clearErrInRxLevel1 field.
* @param[in] clearerrintxlevel1 - The value to use for the clearErrInTxLevel1 field.
*/
__INLINE void nxmac_mac_err_clear_status_pack(uint8_t clearerrinhwlevel3, uint8_t clearerrintxrxlevel2, uint8_t clearerrinrxlevel1, uint8_t clearerrintxlevel1)
{
ASSERT_ERR((((uint32_t)clearerrinhwlevel3 << 3) & ~((uint32_t)0x00000008)) == 0);
ASSERT_ERR((((uint32_t)clearerrintxrxlevel2 << 2) & ~((uint32_t)0x00000004)) == 0);
ASSERT_ERR((((uint32_t)clearerrinrxlevel1 << 1) & ~((uint32_t)0x00000002)) == 0);
ASSERT_ERR((((uint32_t)clearerrintxlevel1 << 0) & ~((uint32_t)0x00000001)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_CLEAR_STATUS_ADDR, ((uint32_t)clearerrinhwlevel3 << 3) | ((uint32_t)clearerrintxrxlevel2 << 2) | ((uint32_t)clearerrinrxlevel1 << 1) | ((uint32_t)clearerrintxlevel1 << 0));
}
/**
* @brief Unpacks MAC_ERR_CLEAR_STATUS's fields from current value of the MAC_ERR_CLEAR_STATUS register.
*
* Reads the MAC_ERR_CLEAR_STATUS register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] clearerrinhwlevel3 - Will be populated with the current value of this field from the register.
* @param[out] clearerrintxrxlevel2 - Will be populated with the current value of this field from the register.
* @param[out] clearerrinrxlevel1 - Will be populated with the current value of this field from the register.
* @param[out] clearerrintxlevel1 - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_mac_err_clear_status_unpack(uint8_t *clearerrinhwlevel3, uint8_t *clearerrintxrxlevel2, uint8_t *clearerrinrxlevel1, uint8_t *clearerrintxlevel1)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_CLEAR_STATUS_ADDR);
*clearerrinhwlevel3 = (localVal & ((uint32_t)0x00000008)) >> 3;
*clearerrintxrxlevel2 = (localVal & ((uint32_t)0x00000004)) >> 2;
*clearerrinrxlevel1 = (localVal & ((uint32_t)0x00000002)) >> 1;
*clearerrintxlevel1 = (localVal & ((uint32_t)0x00000001)) >> 0;
}
/**
* @brief Returns the current value of the clearErrInHWLevel3 field in the MAC_ERR_CLEAR_STATUS register.
*
* The MAC_ERR_CLEAR_STATUS register will be read and the clearErrInHWLevel3 field's value will be returned.
*
* @return The current value of the clearErrInHWLevel3 field in the MAC_ERR_CLEAR_STATUS register.
*/
__INLINE uint8_t nxmac_clear_err_in_hw_level_3_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_CLEAR_STATUS_ADDR);
return ((localVal & ((uint32_t)0x00000008)) >> 3);
}
/**
* @brief Sets the clearErrInHWLevel3 field of the MAC_ERR_CLEAR_STATUS register.
*
* The MAC_ERR_CLEAR_STATUS register will be read, modified to contain the new field value, and written.
*
* @param[in] clearerrinhwlevel3 - The value to set the field to.
*/
__INLINE void nxmac_clear_err_in_hw_level_3_clearf(uint8_t clearerrinhwlevel3)
{
ASSERT_ERR((((uint32_t)clearerrinhwlevel3 << 3) & ~((uint32_t)0x00000008)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_CLEAR_STATUS_ADDR, (uint32_t)clearerrinhwlevel3 << 3);
}
/**
* @brief Returns the current value of the clearErrInTxRxLevel2 field in the MAC_ERR_CLEAR_STATUS register.
*
* The MAC_ERR_CLEAR_STATUS register will be read and the clearErrInTxRxLevel2 field's value will be returned.
*
* @return The current value of the clearErrInTxRxLevel2 field in the MAC_ERR_CLEAR_STATUS register.
*/
__INLINE uint8_t nxmac_clear_err_in_tx_rx_level_2_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_CLEAR_STATUS_ADDR);
return ((localVal & ((uint32_t)0x00000004)) >> 2);
}
/**
* @brief Sets the clearErrInTxRxLevel2 field of the MAC_ERR_CLEAR_STATUS register.
*
* The MAC_ERR_CLEAR_STATUS register will be read, modified to contain the new field value, and written.
*
* @param[in] clearerrintxrxlevel2 - The value to set the field to.
*/
__INLINE void nxmac_clear_err_in_tx_rx_level_2_clearf(uint8_t clearerrintxrxlevel2)
{
ASSERT_ERR((((uint32_t)clearerrintxrxlevel2 << 2) & ~((uint32_t)0x00000004)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_CLEAR_STATUS_ADDR, (uint32_t)clearerrintxrxlevel2 << 2);
}
/**
* @brief Returns the current value of the clearErrInRxLevel1 field in the MAC_ERR_CLEAR_STATUS register.
*
* The MAC_ERR_CLEAR_STATUS register will be read and the clearErrInRxLevel1 field's value will be returned.
*
* @return The current value of the clearErrInRxLevel1 field in the MAC_ERR_CLEAR_STATUS register.
*/
__INLINE uint8_t nxmac_clear_err_in_rx_level_1_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_CLEAR_STATUS_ADDR);
return ((localVal & ((uint32_t)0x00000002)) >> 1);
}
/**
* @brief Sets the clearErrInRxLevel1 field of the MAC_ERR_CLEAR_STATUS register.
*
* The MAC_ERR_CLEAR_STATUS register will be read, modified to contain the new field value, and written.
*
* @param[in] clearerrinrxlevel1 - The value to set the field to.
*/
__INLINE void nxmac_clear_err_in_rx_level_1_clearf(uint8_t clearerrinrxlevel1)
{
ASSERT_ERR((((uint32_t)clearerrinrxlevel1 << 1) & ~((uint32_t)0x00000002)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_CLEAR_STATUS_ADDR, (uint32_t)clearerrinrxlevel1 << 1);
}
/**
* @brief Returns the current value of the clearErrInTxLevel1 field in the MAC_ERR_CLEAR_STATUS register.
*
* The MAC_ERR_CLEAR_STATUS register will be read and the clearErrInTxLevel1 field's value will be returned.
*
* @return The current value of the clearErrInTxLevel1 field in the MAC_ERR_CLEAR_STATUS register.
*/
__INLINE uint8_t nxmac_clear_err_in_tx_level_1_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAC_ERR_CLEAR_STATUS_ADDR);
return ((localVal & ((uint32_t)0x00000001)) >> 0);
}
/**
* @brief Sets the clearErrInTxLevel1 field of the MAC_ERR_CLEAR_STATUS register.
*
* The MAC_ERR_CLEAR_STATUS register will be read, modified to contain the new field value, and written.
*
* @param[in] clearerrintxlevel1 - The value to set the field to.
*/
__INLINE void nxmac_clear_err_in_tx_level_1_clearf(uint8_t clearerrintxlevel1)
{
ASSERT_ERR((((uint32_t)clearerrintxlevel1 << 0) & ~((uint32_t)0x00000001)) == 0);
REG_PL_WR(NXMAC_MAC_ERR_CLEAR_STATUS_ADDR, (uint32_t)clearerrintxlevel1 << 0);
}
/// @}
/**
* @name RX_CNTRL register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31 enDuplicateDetection 0
* 30 acceptUnknown 0
* 29 acceptOtherDataFrames 0
* 28 acceptQoSNull 1
* 27 acceptQCFWOData 0
* 26 acceptQData 1
* 25 acceptCFWOData 0
* 24 acceptData 1
* 23 acceptOtherCntrlFrames 0
* 22 acceptCFEnd 0
* 21 acceptACK 0
* 20 acceptCTS 0
* 19 acceptRTS 0
* 18 acceptPSPoll 1
* 17 acceptBA 1
* 16 acceptBAR 1
* 15 acceptOtherMgmtFrames 1
* 14 acceptBfmeeFrames 0
* 13 acceptAllBeacon 0
* 12 acceptNotExpectedBA 0
* 11 acceptDecryptErrorFrames 0
* 10 acceptBeacon 1
* 09 acceptProbeResp 1
* 08 acceptProbeReq 1
* 07 acceptMyUnicast 1
* 06 acceptUnicast 0
* 05 acceptErrorFrames 0
* 04 acceptOtherBSSID 0
* 03 acceptBroadcast 1
* 02 acceptMulticast 0
* 01 dontDecrypt 0
* 00 excUnencrypted 0
* </pre>
*
* @{
*/
/// Address of the RX_CNTRL register
#define NXMAC_RX_CNTRL_ADDR 0xC0000060
/// Offset of the RX_CNTRL register from the base address
#define NXMAC_RX_CNTRL_OFFSET 0x00000060
/// Index of the RX_CNTRL register
#define NXMAC_RX_CNTRL_INDEX 0x00000018
/// Reset value of the RX_CNTRL register
#define NXMAC_RX_CNTRL_RESET 0x15078788
/**
* @brief Returns the current value of the RX_CNTRL register.
* The RX_CNTRL register will be read and its value returned.
* @return The current value of the RX_CNTRL register.
*/
__INLINE uint32_t nxmac_rx_cntrl_get(void)
{
return REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
}
/**
* @brief Sets the RX_CNTRL register to a value.
* The RX_CNTRL register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_rx_cntrl_set(uint32_t value)
{
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, value);
}
// field definitions
/// EN_DUPLICATE_DETECTION field bit
#define NXMAC_EN_DUPLICATE_DETECTION_BIT ((uint32_t)0x80000000)
/// EN_DUPLICATE_DETECTION field position
#define NXMAC_EN_DUPLICATE_DETECTION_POS 31
/// ACCEPT_UNKNOWN field bit
#define NXMAC_ACCEPT_UNKNOWN_BIT ((uint32_t)0x40000000)
/// ACCEPT_UNKNOWN field position
#define NXMAC_ACCEPT_UNKNOWN_POS 30
/// ACCEPT_OTHER_DATA_FRAMES field bit
#define NXMAC_ACCEPT_OTHER_DATA_FRAMES_BIT ((uint32_t)0x20000000)
/// ACCEPT_OTHER_DATA_FRAMES field position
#define NXMAC_ACCEPT_OTHER_DATA_FRAMES_POS 29
/// ACCEPT_QO_S_NULL field bit
#define NXMAC_ACCEPT_QO_S_NULL_BIT ((uint32_t)0x10000000)
/// ACCEPT_QO_S_NULL field position
#define NXMAC_ACCEPT_QO_S_NULL_POS 28
/// ACCEPT_QCFWO_DATA field bit
#define NXMAC_ACCEPT_QCFWO_DATA_BIT ((uint32_t)0x08000000)
/// ACCEPT_QCFWO_DATA field position
#define NXMAC_ACCEPT_QCFWO_DATA_POS 27
/// ACCEPT_Q_DATA field bit
#define NXMAC_ACCEPT_Q_DATA_BIT ((uint32_t)0x04000000)
/// ACCEPT_Q_DATA field position
#define NXMAC_ACCEPT_Q_DATA_POS 26
/// ACCEPT_CFWO_DATA field bit
#define NXMAC_ACCEPT_CFWO_DATA_BIT ((uint32_t)0x02000000)
/// ACCEPT_CFWO_DATA field position
#define NXMAC_ACCEPT_CFWO_DATA_POS 25
/// ACCEPT_DATA field bit
#define NXMAC_ACCEPT_DATA_BIT ((uint32_t)0x01000000)
/// ACCEPT_DATA field position
#define NXMAC_ACCEPT_DATA_POS 24
/// ACCEPT_OTHER_CNTRL_FRAMES field bit
#define NXMAC_ACCEPT_OTHER_CNTRL_FRAMES_BIT ((uint32_t)0x00800000)
/// ACCEPT_OTHER_CNTRL_FRAMES field position
#define NXMAC_ACCEPT_OTHER_CNTRL_FRAMES_POS 23
/// ACCEPT_CF_END field bit
#define NXMAC_ACCEPT_CF_END_BIT ((uint32_t)0x00400000)
/// ACCEPT_CF_END field position
#define NXMAC_ACCEPT_CF_END_POS 22
/// ACCEPT_ACK field bit
#define NXMAC_ACCEPT_ACK_BIT ((uint32_t)0x00200000)
/// ACCEPT_ACK field position
#define NXMAC_ACCEPT_ACK_POS 21
/// ACCEPT_CTS field bit
#define NXMAC_ACCEPT_CTS_BIT ((uint32_t)0x00100000)
/// ACCEPT_CTS field position
#define NXMAC_ACCEPT_CTS_POS 20
/// ACCEPT_RTS field bit
#define NXMAC_ACCEPT_RTS_BIT ((uint32_t)0x00080000)
/// ACCEPT_RTS field position
#define NXMAC_ACCEPT_RTS_POS 19
/// ACCEPT_PS_POLL field bit
#define NXMAC_ACCEPT_PS_POLL_BIT ((uint32_t)0x00040000)
/// ACCEPT_PS_POLL field position
#define NXMAC_ACCEPT_PS_POLL_POS 18
/// ACCEPT_BA field bit
#define NXMAC_ACCEPT_BA_BIT ((uint32_t)0x00020000)
/// ACCEPT_BA field position
#define NXMAC_ACCEPT_BA_POS 17
/// ACCEPT_BAR field bit
#define NXMAC_ACCEPT_BAR_BIT ((uint32_t)0x00010000)
/// ACCEPT_BAR field position
#define NXMAC_ACCEPT_BAR_POS 16
/// ACCEPT_OTHER_MGMT_FRAMES field bit
#define NXMAC_ACCEPT_OTHER_MGMT_FRAMES_BIT ((uint32_t)0x00008000)
/// ACCEPT_OTHER_MGMT_FRAMES field position
#define NXMAC_ACCEPT_OTHER_MGMT_FRAMES_POS 15
/// ACCEPT_BFMEE_FRAMES field bit
#define NXMAC_ACCEPT_BFMEE_FRAMES_BIT ((uint32_t)0x00004000)
/// ACCEPT_BFMEE_FRAMES field position
#define NXMAC_ACCEPT_BFMEE_FRAMES_POS 14
/// ACCEPT_ALL_BEACON field bit
#define NXMAC_ACCEPT_ALL_BEACON_BIT ((uint32_t)0x00002000)
/// ACCEPT_ALL_BEACON field position
#define NXMAC_ACCEPT_ALL_BEACON_POS 13
/// ACCEPT_NOT_EXPECTED_BA field bit
#define NXMAC_ACCEPT_NOT_EXPECTED_BA_BIT ((uint32_t)0x00001000)
/// ACCEPT_NOT_EXPECTED_BA field position
#define NXMAC_ACCEPT_NOT_EXPECTED_BA_POS 12
/// ACCEPT_DECRYPT_ERROR_FRAMES field bit
#define NXMAC_ACCEPT_DECRYPT_ERROR_FRAMES_BIT ((uint32_t)0x00000800)
/// ACCEPT_DECRYPT_ERROR_FRAMES field position
#define NXMAC_ACCEPT_DECRYPT_ERROR_FRAMES_POS 11
/// ACCEPT_BEACON field bit
#define NXMAC_ACCEPT_BEACON_BIT ((uint32_t)0x00000400)
/// ACCEPT_BEACON field position
#define NXMAC_ACCEPT_BEACON_POS 10
/// ACCEPT_PROBE_RESP field bit
#define NXMAC_ACCEPT_PROBE_RESP_BIT ((uint32_t)0x00000200)
/// ACCEPT_PROBE_RESP field position
#define NXMAC_ACCEPT_PROBE_RESP_POS 9
/// ACCEPT_PROBE_REQ field bit
#define NXMAC_ACCEPT_PROBE_REQ_BIT ((uint32_t)0x00000100)
/// ACCEPT_PROBE_REQ field position
#define NXMAC_ACCEPT_PROBE_REQ_POS 8
/// ACCEPT_MY_UNICAST field bit
#define NXMAC_ACCEPT_MY_UNICAST_BIT ((uint32_t)0x00000080)
/// ACCEPT_MY_UNICAST field position
#define NXMAC_ACCEPT_MY_UNICAST_POS 7
/// ACCEPT_UNICAST field bit
#define NXMAC_ACCEPT_UNICAST_BIT ((uint32_t)0x00000040)
/// ACCEPT_UNICAST field position
#define NXMAC_ACCEPT_UNICAST_POS 6
/// ACCEPT_ERROR_FRAMES field bit
#define NXMAC_ACCEPT_ERROR_FRAMES_BIT ((uint32_t)0x00000020)
/// ACCEPT_ERROR_FRAMES field position
#define NXMAC_ACCEPT_ERROR_FRAMES_POS 5
/// ACCEPT_OTHER_BSSID field bit
#define NXMAC_ACCEPT_OTHER_BSSID_BIT ((uint32_t)0x00000010)
/// ACCEPT_OTHER_BSSID field position
#define NXMAC_ACCEPT_OTHER_BSSID_POS 4
/// ACCEPT_BROADCAST field bit
#define NXMAC_ACCEPT_BROADCAST_BIT ((uint32_t)0x00000008)
/// ACCEPT_BROADCAST field position
#define NXMAC_ACCEPT_BROADCAST_POS 3
/// ACCEPT_MULTICAST field bit
#define NXMAC_ACCEPT_MULTICAST_BIT ((uint32_t)0x00000004)
/// ACCEPT_MULTICAST field position
#define NXMAC_ACCEPT_MULTICAST_POS 2
/// DONT_DECRYPT field bit
#define NXMAC_DONT_DECRYPT_BIT ((uint32_t)0x00000002)
/// DONT_DECRYPT field position
#define NXMAC_DONT_DECRYPT_POS 1
/// EXC_UNENCRYPTED field bit
#define NXMAC_EXC_UNENCRYPTED_BIT ((uint32_t)0x00000001)
/// EXC_UNENCRYPTED field position
#define NXMAC_EXC_UNENCRYPTED_POS 0
/// EN_DUPLICATE_DETECTION field reset value
#define NXMAC_EN_DUPLICATE_DETECTION_RST 0x0
/// ACCEPT_UNKNOWN field reset value
#define NXMAC_ACCEPT_UNKNOWN_RST 0x0
/// ACCEPT_OTHER_DATA_FRAMES field reset value
#define NXMAC_ACCEPT_OTHER_DATA_FRAMES_RST 0x0
/// ACCEPT_QO_S_NULL field reset value
#define NXMAC_ACCEPT_QO_S_NULL_RST 0x1
/// ACCEPT_QCFWO_DATA field reset value
#define NXMAC_ACCEPT_QCFWO_DATA_RST 0x0
/// ACCEPT_Q_DATA field reset value
#define NXMAC_ACCEPT_Q_DATA_RST 0x1
/// ACCEPT_CFWO_DATA field reset value
#define NXMAC_ACCEPT_CFWO_DATA_RST 0x0
/// ACCEPT_DATA field reset value
#define NXMAC_ACCEPT_DATA_RST 0x1
/// ACCEPT_OTHER_CNTRL_FRAMES field reset value
#define NXMAC_ACCEPT_OTHER_CNTRL_FRAMES_RST 0x0
/// ACCEPT_CF_END field reset value
#define NXMAC_ACCEPT_CF_END_RST 0x0
/// ACCEPT_ACK field reset value
#define NXMAC_ACCEPT_ACK_RST 0x0
/// ACCEPT_CTS field reset value
#define NXMAC_ACCEPT_CTS_RST 0x0
/// ACCEPT_RTS field reset value
#define NXMAC_ACCEPT_RTS_RST 0x0
/// ACCEPT_PS_POLL field reset value
#define NXMAC_ACCEPT_PS_POLL_RST 0x1
/// ACCEPT_BA field reset value
#define NXMAC_ACCEPT_BA_RST 0x1
/// ACCEPT_BAR field reset value
#define NXMAC_ACCEPT_BAR_RST 0x1
/// ACCEPT_OTHER_MGMT_FRAMES field reset value
#define NXMAC_ACCEPT_OTHER_MGMT_FRAMES_RST 0x1
/// ACCEPT_BFMEE_FRAMES field reset value
#define NXMAC_ACCEPT_BFMEE_FRAMES_RST 0x0
/// ACCEPT_ALL_BEACON field reset value
#define NXMAC_ACCEPT_ALL_BEACON_RST 0x0
/// ACCEPT_NOT_EXPECTED_BA field reset value
#define NXMAC_ACCEPT_NOT_EXPECTED_BA_RST 0x0
/// ACCEPT_DECRYPT_ERROR_FRAMES field reset value
#define NXMAC_ACCEPT_DECRYPT_ERROR_FRAMES_RST 0x0
/// ACCEPT_BEACON field reset value
#define NXMAC_ACCEPT_BEACON_RST 0x1
/// ACCEPT_PROBE_RESP field reset value
#define NXMAC_ACCEPT_PROBE_RESP_RST 0x1
/// ACCEPT_PROBE_REQ field reset value
#define NXMAC_ACCEPT_PROBE_REQ_RST 0x1
/// ACCEPT_MY_UNICAST field reset value
#define NXMAC_ACCEPT_MY_UNICAST_RST 0x1
/// ACCEPT_UNICAST field reset value
#define NXMAC_ACCEPT_UNICAST_RST 0x0
/// ACCEPT_ERROR_FRAMES field reset value
#define NXMAC_ACCEPT_ERROR_FRAMES_RST 0x0
/// ACCEPT_OTHER_BSSID field reset value
#define NXMAC_ACCEPT_OTHER_BSSID_RST 0x0
/// ACCEPT_BROADCAST field reset value
#define NXMAC_ACCEPT_BROADCAST_RST 0x1
/// ACCEPT_MULTICAST field reset value
#define NXMAC_ACCEPT_MULTICAST_RST 0x0
/// DONT_DECRYPT field reset value
#define NXMAC_DONT_DECRYPT_RST 0x0
/// EXC_UNENCRYPTED field reset value
#define NXMAC_EXC_UNENCRYPTED_RST 0x0
/**
* @brief Constructs a value for the RX_CNTRL register given values for its fields
* and writes the value to the register.
*
* @param[in] acceptunknown - The value to use for the acceptUnknown field.
* @param[in] acceptotherdataframes - The value to use for the acceptOtherDataFrames field.
* @param[in] acceptqosnull - The value to use for the acceptQoSNull field.
* @param[in] acceptqcfwodata - The value to use for the acceptQCFWOData field.
* @param[in] acceptqdata - The value to use for the acceptQData field.
* @param[in] acceptcfwodata - The value to use for the acceptCFWOData field.
* @param[in] acceptdata - The value to use for the acceptData field.
* @param[in] acceptothercntrlframes - The value to use for the acceptOtherCntrlFrames field.
* @param[in] acceptcfend - The value to use for the acceptCFEnd field.
* @param[in] acceptack - The value to use for the acceptACK field.
* @param[in] acceptcts - The value to use for the acceptCTS field.
* @param[in] acceptrts - The value to use for the acceptRTS field.
* @param[in] acceptpspoll - The value to use for the acceptPSPoll field.
* @param[in] acceptba - The value to use for the acceptBA field.
* @param[in] acceptbar - The value to use for the acceptBAR field.
* @param[in] acceptothermgmtframes - The value to use for the acceptOtherMgmtFrames field.
* @param[in] acceptbfmeeframes - The value to use for the acceptBfmeeFrames field.
* @param[in] acceptallbeacon - The value to use for the acceptAllBeacon field.
* @param[in] acceptnotexpectedba - The value to use for the acceptNotExpectedBA field.
* @param[in] acceptdecrypterrorframes - The value to use for the acceptDecryptErrorFrames field.
* @param[in] acceptbeacon - The value to use for the acceptBeacon field.
* @param[in] acceptproberesp - The value to use for the acceptProbeResp field.
* @param[in] acceptprobereq - The value to use for the acceptProbeReq field.
* @param[in] acceptmyunicast - The value to use for the acceptMyUnicast field.
* @param[in] acceptunicast - The value to use for the acceptUnicast field.
* @param[in] accepterrorframes - The value to use for the acceptErrorFrames field.
* @param[in] acceptotherbssid - The value to use for the acceptOtherBSSID field.
* @param[in] acceptbroadcast - The value to use for the acceptBroadcast field.
* @param[in] acceptmulticast - The value to use for the acceptMulticast field.
* @param[in] dontdecrypt - The value to use for the dontDecrypt field.
* @param[in] excunencrypted - The value to use for the excUnencrypted field.
*/
__INLINE void nxmac_rx_cntrl_pack(uint8_t acceptunknown, uint8_t acceptotherdataframes, uint8_t acceptqosnull, uint8_t acceptqcfwodata, uint8_t acceptqdata, uint8_t acceptcfwodata, uint8_t acceptdata, uint8_t acceptothercntrlframes, uint8_t acceptcfend, uint8_t acceptack, uint8_t acceptcts, uint8_t acceptrts, uint8_t acceptpspoll, uint8_t acceptba, uint8_t acceptbar, uint8_t acceptothermgmtframes, uint8_t acceptbfmeeframes, uint8_t acceptallbeacon, uint8_t acceptnotexpectedba, uint8_t acceptdecrypterrorframes, uint8_t acceptbeacon, uint8_t acceptproberesp, uint8_t acceptprobereq, uint8_t acceptmyunicast, uint8_t acceptunicast, uint8_t accepterrorframes, uint8_t acceptotherbssid, uint8_t acceptbroadcast, uint8_t acceptmulticast, uint8_t dontdecrypt, uint8_t excunencrypted)
{
ASSERT_ERR((((uint32_t)acceptunknown << 30) & ~((uint32_t)0x40000000)) == 0);
ASSERT_ERR((((uint32_t)acceptotherdataframes << 29) & ~((uint32_t)0x20000000)) == 0);
ASSERT_ERR((((uint32_t)acceptqosnull << 28) & ~((uint32_t)0x10000000)) == 0);
ASSERT_ERR((((uint32_t)acceptqcfwodata << 27) & ~((uint32_t)0x08000000)) == 0);
ASSERT_ERR((((uint32_t)acceptqdata << 26) & ~((uint32_t)0x04000000)) == 0);
ASSERT_ERR((((uint32_t)acceptcfwodata << 25) & ~((uint32_t)0x02000000)) == 0);
ASSERT_ERR((((uint32_t)acceptdata << 24) & ~((uint32_t)0x01000000)) == 0);
ASSERT_ERR((((uint32_t)acceptothercntrlframes << 23) & ~((uint32_t)0x00800000)) == 0);
ASSERT_ERR((((uint32_t)acceptcfend << 22) & ~((uint32_t)0x00400000)) == 0);
ASSERT_ERR((((uint32_t)acceptack << 21) & ~((uint32_t)0x00200000)) == 0);
ASSERT_ERR((((uint32_t)acceptcts << 20) & ~((uint32_t)0x00100000)) == 0);
ASSERT_ERR((((uint32_t)acceptrts << 19) & ~((uint32_t)0x00080000)) == 0);
ASSERT_ERR((((uint32_t)acceptpspoll << 18) & ~((uint32_t)0x00040000)) == 0);
ASSERT_ERR((((uint32_t)acceptba << 17) & ~((uint32_t)0x00020000)) == 0);
ASSERT_ERR((((uint32_t)acceptbar << 16) & ~((uint32_t)0x00010000)) == 0);
ASSERT_ERR((((uint32_t)acceptothermgmtframes << 15) & ~((uint32_t)0x00008000)) == 0);
ASSERT_ERR((((uint32_t)acceptbfmeeframes << 14) & ~((uint32_t)0x00004000)) == 0);
ASSERT_ERR((((uint32_t)acceptallbeacon << 13) & ~((uint32_t)0x00002000)) == 0);
ASSERT_ERR((((uint32_t)acceptnotexpectedba << 12) & ~((uint32_t)0x00001000)) == 0);
ASSERT_ERR((((uint32_t)acceptdecrypterrorframes << 11) & ~((uint32_t)0x00000800)) == 0);
ASSERT_ERR((((uint32_t)acceptbeacon << 10) & ~((uint32_t)0x00000400)) == 0);
ASSERT_ERR((((uint32_t)acceptproberesp << 9) & ~((uint32_t)0x00000200)) == 0);
ASSERT_ERR((((uint32_t)acceptprobereq << 8) & ~((uint32_t)0x00000100)) == 0);
ASSERT_ERR((((uint32_t)acceptmyunicast << 7) & ~((uint32_t)0x00000080)) == 0);
ASSERT_ERR((((uint32_t)acceptunicast << 6) & ~((uint32_t)0x00000040)) == 0);
ASSERT_ERR((((uint32_t)accepterrorframes << 5) & ~((uint32_t)0x00000020)) == 0);
ASSERT_ERR((((uint32_t)acceptotherbssid << 4) & ~((uint32_t)0x00000010)) == 0);
ASSERT_ERR((((uint32_t)acceptbroadcast << 3) & ~((uint32_t)0x00000008)) == 0);
ASSERT_ERR((((uint32_t)acceptmulticast << 2) & ~((uint32_t)0x00000004)) == 0);
ASSERT_ERR((((uint32_t)dontdecrypt << 1) & ~((uint32_t)0x00000002)) == 0);
ASSERT_ERR((((uint32_t)excunencrypted << 0) & ~((uint32_t)0x00000001)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, ((uint32_t)acceptunknown << 30) | ((uint32_t)acceptotherdataframes << 29) | ((uint32_t)acceptqosnull << 28) | ((uint32_t)acceptqcfwodata << 27) | ((uint32_t)acceptqdata << 26) | ((uint32_t)acceptcfwodata << 25) | ((uint32_t)acceptdata << 24) | ((uint32_t)acceptothercntrlframes << 23) | ((uint32_t)acceptcfend << 22) | ((uint32_t)acceptack << 21) | ((uint32_t)acceptcts << 20) | ((uint32_t)acceptrts << 19) | ((uint32_t)acceptpspoll << 18) | ((uint32_t)acceptba << 17) | ((uint32_t)acceptbar << 16) | ((uint32_t)acceptothermgmtframes << 15) | ((uint32_t)acceptbfmeeframes << 14) | ((uint32_t)acceptallbeacon << 13) | ((uint32_t)acceptnotexpectedba << 12) | ((uint32_t)acceptdecrypterrorframes << 11) | ((uint32_t)acceptbeacon << 10) | ((uint32_t)acceptproberesp << 9) | ((uint32_t)acceptprobereq << 8) | ((uint32_t)acceptmyunicast << 7) | ((uint32_t)acceptunicast << 6) | ((uint32_t)accepterrorframes << 5) | ((uint32_t)acceptotherbssid << 4) | ((uint32_t)acceptbroadcast << 3) | ((uint32_t)acceptmulticast << 2) | ((uint32_t)dontdecrypt << 1) | ((uint32_t)excunencrypted << 0));
}
/**
* @brief Unpacks RX_CNTRL's fields from current value of the RX_CNTRL register.
*
* Reads the RX_CNTRL register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] enduplicatedetection - Will be populated with the current value of this field from the register.
* @param[out] acceptunknown - Will be populated with the current value of this field from the register.
* @param[out] acceptotherdataframes - Will be populated with the current value of this field from the register.
* @param[out] acceptqosnull - Will be populated with the current value of this field from the register.
* @param[out] acceptqcfwodata - Will be populated with the current value of this field from the register.
* @param[out] acceptqdata - Will be populated with the current value of this field from the register.
* @param[out] acceptcfwodata - Will be populated with the current value of this field from the register.
* @param[out] acceptdata - Will be populated with the current value of this field from the register.
* @param[out] acceptothercntrlframes - Will be populated with the current value of this field from the register.
* @param[out] acceptcfend - Will be populated with the current value of this field from the register.
* @param[out] acceptack - Will be populated with the current value of this field from the register.
* @param[out] acceptcts - Will be populated with the current value of this field from the register.
* @param[out] acceptrts - Will be populated with the current value of this field from the register.
* @param[out] acceptpspoll - Will be populated with the current value of this field from the register.
* @param[out] acceptba - Will be populated with the current value of this field from the register.
* @param[out] acceptbar - Will be populated with the current value of this field from the register.
* @param[out] acceptothermgmtframes - Will be populated with the current value of this field from the register.
* @param[out] acceptbfmeeframes - Will be populated with the current value of this field from the register.
* @param[out] acceptallbeacon - Will be populated with the current value of this field from the register.
* @param[out] acceptnotexpectedba - Will be populated with the current value of this field from the register.
* @param[out] acceptdecrypterrorframes - Will be populated with the current value of this field from the register.
* @param[out] acceptbeacon - Will be populated with the current value of this field from the register.
* @param[out] acceptproberesp - Will be populated with the current value of this field from the register.
* @param[out] acceptprobereq - Will be populated with the current value of this field from the register.
* @param[out] acceptmyunicast - Will be populated with the current value of this field from the register.
* @param[out] acceptunicast - Will be populated with the current value of this field from the register.
* @param[out] accepterrorframes - Will be populated with the current value of this field from the register.
* @param[out] acceptotherbssid - Will be populated with the current value of this field from the register.
* @param[out] acceptbroadcast - Will be populated with the current value of this field from the register.
* @param[out] acceptmulticast - Will be populated with the current value of this field from the register.
* @param[out] dontdecrypt - Will be populated with the current value of this field from the register.
* @param[out] excunencrypted - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_rx_cntrl_unpack(uint8_t *enduplicatedetection, uint8_t *acceptunknown, uint8_t *acceptotherdataframes, uint8_t *acceptqosnull, uint8_t *acceptqcfwodata, uint8_t *acceptqdata, uint8_t *acceptcfwodata, uint8_t *acceptdata, uint8_t *acceptothercntrlframes, uint8_t *acceptcfend, uint8_t *acceptack, uint8_t *acceptcts, uint8_t *acceptrts, uint8_t *acceptpspoll, uint8_t *acceptba, uint8_t *acceptbar, uint8_t *acceptothermgmtframes, uint8_t *acceptbfmeeframes, uint8_t *acceptallbeacon, uint8_t *acceptnotexpectedba, uint8_t *acceptdecrypterrorframes, uint8_t *acceptbeacon, uint8_t *acceptproberesp, uint8_t *acceptprobereq, uint8_t *acceptmyunicast, uint8_t *acceptunicast, uint8_t *accepterrorframes, uint8_t *acceptotherbssid, uint8_t *acceptbroadcast, uint8_t *acceptmulticast, uint8_t *dontdecrypt, uint8_t *excunencrypted)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
*enduplicatedetection = (localVal & ((uint32_t)0x80000000)) >> 31;
*acceptunknown = (localVal & ((uint32_t)0x40000000)) >> 30;
*acceptotherdataframes = (localVal & ((uint32_t)0x20000000)) >> 29;
*acceptqosnull = (localVal & ((uint32_t)0x10000000)) >> 28;
*acceptqcfwodata = (localVal & ((uint32_t)0x08000000)) >> 27;
*acceptqdata = (localVal & ((uint32_t)0x04000000)) >> 26;
*acceptcfwodata = (localVal & ((uint32_t)0x02000000)) >> 25;
*acceptdata = (localVal & ((uint32_t)0x01000000)) >> 24;
*acceptothercntrlframes = (localVal & ((uint32_t)0x00800000)) >> 23;
*acceptcfend = (localVal & ((uint32_t)0x00400000)) >> 22;
*acceptack = (localVal & ((uint32_t)0x00200000)) >> 21;
*acceptcts = (localVal & ((uint32_t)0x00100000)) >> 20;
*acceptrts = (localVal & ((uint32_t)0x00080000)) >> 19;
*acceptpspoll = (localVal & ((uint32_t)0x00040000)) >> 18;
*acceptba = (localVal & ((uint32_t)0x00020000)) >> 17;
*acceptbar = (localVal & ((uint32_t)0x00010000)) >> 16;
*acceptothermgmtframes = (localVal & ((uint32_t)0x00008000)) >> 15;
*acceptbfmeeframes = (localVal & ((uint32_t)0x00004000)) >> 14;
*acceptallbeacon = (localVal & ((uint32_t)0x00002000)) >> 13;
*acceptnotexpectedba = (localVal & ((uint32_t)0x00001000)) >> 12;
*acceptdecrypterrorframes = (localVal & ((uint32_t)0x00000800)) >> 11;
*acceptbeacon = (localVal & ((uint32_t)0x00000400)) >> 10;
*acceptproberesp = (localVal & ((uint32_t)0x00000200)) >> 9;
*acceptprobereq = (localVal & ((uint32_t)0x00000100)) >> 8;
*acceptmyunicast = (localVal & ((uint32_t)0x00000080)) >> 7;
*acceptunicast = (localVal & ((uint32_t)0x00000040)) >> 6;
*accepterrorframes = (localVal & ((uint32_t)0x00000020)) >> 5;
*acceptotherbssid = (localVal & ((uint32_t)0x00000010)) >> 4;
*acceptbroadcast = (localVal & ((uint32_t)0x00000008)) >> 3;
*acceptmulticast = (localVal & ((uint32_t)0x00000004)) >> 2;
*dontdecrypt = (localVal & ((uint32_t)0x00000002)) >> 1;
*excunencrypted = (localVal & ((uint32_t)0x00000001)) >> 0;
}
/**
* @brief Returns the current value of the enDuplicateDetection field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the enDuplicateDetection field's value will be returned.
*
* @return The current value of the enDuplicateDetection field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_en_duplicate_detection_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x80000000)) >> 31);
}
/**
* @brief Returns the current value of the acceptUnknown field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptUnknown field's value will be returned.
*
* @return The current value of the acceptUnknown field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_unknown_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x40000000)) >> 30);
}
/**
* @brief Sets the acceptUnknown field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptunknown - The value to set the field to.
*/
__INLINE void nxmac_accept_unknown_setf(uint8_t acceptunknown)
{
ASSERT_ERR((((uint32_t)acceptunknown << 30) & ~((uint32_t)0x40000000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x40000000)) | ((uint32_t)acceptunknown << 30));
}
/**
* @brief Returns the current value of the acceptOtherDataFrames field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptOtherDataFrames field's value will be returned.
*
* @return The current value of the acceptOtherDataFrames field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_other_data_frames_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x20000000)) >> 29);
}
/**
* @brief Sets the acceptOtherDataFrames field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptotherdataframes - The value to set the field to.
*/
__INLINE void nxmac_accept_other_data_frames_setf(uint8_t acceptotherdataframes)
{
ASSERT_ERR((((uint32_t)acceptotherdataframes << 29) & ~((uint32_t)0x20000000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x20000000)) | ((uint32_t)acceptotherdataframes << 29));
}
/**
* @brief Returns the current value of the acceptQoSNull field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptQoSNull field's value will be returned.
*
* @return The current value of the acceptQoSNull field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_qo_s_null_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x10000000)) >> 28);
}
/**
* @brief Sets the acceptQoSNull field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptqosnull - The value to set the field to.
*/
__INLINE void nxmac_accept_qo_s_null_setf(uint8_t acceptqosnull)
{
ASSERT_ERR((((uint32_t)acceptqosnull << 28) & ~((uint32_t)0x10000000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x10000000)) | ((uint32_t)acceptqosnull << 28));
}
/**
* @brief Returns the current value of the acceptQCFWOData field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptQCFWOData field's value will be returned.
*
* @return The current value of the acceptQCFWOData field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_qcfwo_data_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x08000000)) >> 27);
}
/**
* @brief Sets the acceptQCFWOData field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptqcfwodata - The value to set the field to.
*/
__INLINE void nxmac_accept_qcfwo_data_setf(uint8_t acceptqcfwodata)
{
ASSERT_ERR((((uint32_t)acceptqcfwodata << 27) & ~((uint32_t)0x08000000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x08000000)) | ((uint32_t)acceptqcfwodata << 27));
}
/**
* @brief Returns the current value of the acceptQData field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptQData field's value will be returned.
*
* @return The current value of the acceptQData field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_q_data_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x04000000)) >> 26);
}
/**
* @brief Sets the acceptQData field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptqdata - The value to set the field to.
*/
__INLINE void nxmac_accept_q_data_setf(uint8_t acceptqdata)
{
ASSERT_ERR((((uint32_t)acceptqdata << 26) & ~((uint32_t)0x04000000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x04000000)) | ((uint32_t)acceptqdata << 26));
}
/**
* @brief Returns the current value of the acceptCFWOData field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptCFWOData field's value will be returned.
*
* @return The current value of the acceptCFWOData field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_cfwo_data_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x02000000)) >> 25);
}
/**
* @brief Sets the acceptCFWOData field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptcfwodata - The value to set the field to.
*/
__INLINE void nxmac_accept_cfwo_data_setf(uint8_t acceptcfwodata)
{
ASSERT_ERR((((uint32_t)acceptcfwodata << 25) & ~((uint32_t)0x02000000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x02000000)) | ((uint32_t)acceptcfwodata << 25));
}
/**
* @brief Returns the current value of the acceptData field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptData field's value will be returned.
*
* @return The current value of the acceptData field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_data_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x01000000)) >> 24);
}
/**
* @brief Sets the acceptData field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptdata - The value to set the field to.
*/
__INLINE void nxmac_accept_data_setf(uint8_t acceptdata)
{
ASSERT_ERR((((uint32_t)acceptdata << 24) & ~((uint32_t)0x01000000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x01000000)) | ((uint32_t)acceptdata << 24));
}
/**
* @brief Returns the current value of the acceptOtherCntrlFrames field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptOtherCntrlFrames field's value will be returned.
*
* @return The current value of the acceptOtherCntrlFrames field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_other_cntrl_frames_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00800000)) >> 23);
}
/**
* @brief Sets the acceptOtherCntrlFrames field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptothercntrlframes - The value to set the field to.
*/
__INLINE void nxmac_accept_other_cntrl_frames_setf(uint8_t acceptothercntrlframes)
{
ASSERT_ERR((((uint32_t)acceptothercntrlframes << 23) & ~((uint32_t)0x00800000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00800000)) | ((uint32_t)acceptothercntrlframes << 23));
}
/**
* @brief Returns the current value of the acceptCFEnd field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptCFEnd field's value will be returned.
*
* @return The current value of the acceptCFEnd field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_cf_end_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00400000)) >> 22);
}
/**
* @brief Sets the acceptCFEnd field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptcfend - The value to set the field to.
*/
__INLINE void nxmac_accept_cf_end_setf(uint8_t acceptcfend)
{
ASSERT_ERR((((uint32_t)acceptcfend << 22) & ~((uint32_t)0x00400000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00400000)) | ((uint32_t)acceptcfend << 22));
}
/**
* @brief Returns the current value of the acceptACK field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptACK field's value will be returned.
*
* @return The current value of the acceptACK field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_ack_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00200000)) >> 21);
}
/**
* @brief Sets the acceptACK field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptack - The value to set the field to.
*/
__INLINE void nxmac_accept_ack_setf(uint8_t acceptack)
{
ASSERT_ERR((((uint32_t)acceptack << 21) & ~((uint32_t)0x00200000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00200000)) | ((uint32_t)acceptack << 21));
}
/**
* @brief Returns the current value of the acceptCTS field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptCTS field's value will be returned.
*
* @return The current value of the acceptCTS field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_cts_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00100000)) >> 20);
}
/**
* @brief Sets the acceptCTS field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptcts - The value to set the field to.
*/
__INLINE void nxmac_accept_cts_setf(uint8_t acceptcts)
{
ASSERT_ERR((((uint32_t)acceptcts << 20) & ~((uint32_t)0x00100000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00100000)) | ((uint32_t)acceptcts << 20));
}
/**
* @brief Returns the current value of the acceptRTS field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptRTS field's value will be returned.
*
* @return The current value of the acceptRTS field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_rts_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00080000)) >> 19);
}
/**
* @brief Sets the acceptRTS field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptrts - The value to set the field to.
*/
__INLINE void nxmac_accept_rts_setf(uint8_t acceptrts)
{
ASSERT_ERR((((uint32_t)acceptrts << 19) & ~((uint32_t)0x00080000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00080000)) | ((uint32_t)acceptrts << 19));
}
/**
* @brief Returns the current value of the acceptPSPoll field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptPSPoll field's value will be returned.
*
* @return The current value of the acceptPSPoll field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_ps_poll_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00040000)) >> 18);
}
/**
* @brief Sets the acceptPSPoll field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptpspoll - The value to set the field to.
*/
__INLINE void nxmac_accept_ps_poll_setf(uint8_t acceptpspoll)
{
ASSERT_ERR((((uint32_t)acceptpspoll << 18) & ~((uint32_t)0x00040000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00040000)) | ((uint32_t)acceptpspoll << 18));
}
/**
* @brief Returns the current value of the acceptBA field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptBA field's value will be returned.
*
* @return The current value of the acceptBA field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_ba_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00020000)) >> 17);
}
/**
* @brief Sets the acceptBA field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptba - The value to set the field to.
*/
__INLINE void nxmac_accept_ba_setf(uint8_t acceptba)
{
ASSERT_ERR((((uint32_t)acceptba << 17) & ~((uint32_t)0x00020000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00020000)) | ((uint32_t)acceptba << 17));
}
/**
* @brief Returns the current value of the acceptBAR field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptBAR field's value will be returned.
*
* @return The current value of the acceptBAR field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_bar_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00010000)) >> 16);
}
/**
* @brief Sets the acceptBAR field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptbar - The value to set the field to.
*/
__INLINE void nxmac_accept_bar_setf(uint8_t acceptbar)
{
ASSERT_ERR((((uint32_t)acceptbar << 16) & ~((uint32_t)0x00010000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00010000)) | ((uint32_t)acceptbar << 16));
}
/**
* @brief Returns the current value of the acceptOtherMgmtFrames field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptOtherMgmtFrames field's value will be returned.
*
* @return The current value of the acceptOtherMgmtFrames field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_other_mgmt_frames_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00008000)) >> 15);
}
/**
* @brief Sets the acceptOtherMgmtFrames field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptothermgmtframes - The value to set the field to.
*/
__INLINE void nxmac_accept_other_mgmt_frames_setf(uint8_t acceptothermgmtframes)
{
ASSERT_ERR((((uint32_t)acceptothermgmtframes << 15) & ~((uint32_t)0x00008000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00008000)) | ((uint32_t)acceptothermgmtframes << 15));
}
/**
* @brief Returns the current value of the acceptBfmeeFrames field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptBfmeeFrames field's value will be returned.
*
* @return The current value of the acceptBfmeeFrames field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_bfmee_frames_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00004000)) >> 14);
}
/**
* @brief Sets the acceptBfmeeFrames field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptbfmeeframes - The value to set the field to.
*/
__INLINE void nxmac_accept_bfmee_frames_setf(uint8_t acceptbfmeeframes)
{
ASSERT_ERR((((uint32_t)acceptbfmeeframes << 14) & ~((uint32_t)0x00004000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00004000)) | ((uint32_t)acceptbfmeeframes << 14));
}
/**
* @brief Returns the current value of the acceptAllBeacon field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptAllBeacon field's value will be returned.
*
* @return The current value of the acceptAllBeacon field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_all_beacon_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00002000)) >> 13);
}
/**
* @brief Sets the acceptAllBeacon field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptallbeacon - The value to set the field to.
*/
__INLINE void nxmac_accept_all_beacon_setf(uint8_t acceptallbeacon)
{
ASSERT_ERR((((uint32_t)acceptallbeacon << 13) & ~((uint32_t)0x00002000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00002000)) | ((uint32_t)acceptallbeacon << 13));
}
/**
* @brief Returns the current value of the acceptNotExpectedBA field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptNotExpectedBA field's value will be returned.
*
* @return The current value of the acceptNotExpectedBA field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_not_expected_ba_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00001000)) >> 12);
}
/**
* @brief Sets the acceptNotExpectedBA field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptnotexpectedba - The value to set the field to.
*/
__INLINE void nxmac_accept_not_expected_ba_setf(uint8_t acceptnotexpectedba)
{
ASSERT_ERR((((uint32_t)acceptnotexpectedba << 12) & ~((uint32_t)0x00001000)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00001000)) | ((uint32_t)acceptnotexpectedba << 12));
}
/**
* @brief Returns the current value of the acceptDecryptErrorFrames field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptDecryptErrorFrames field's value will be returned.
*
* @return The current value of the acceptDecryptErrorFrames field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_decrypt_error_frames_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000800)) >> 11);
}
/**
* @brief Sets the acceptDecryptErrorFrames field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptdecrypterrorframes - The value to set the field to.
*/
__INLINE void nxmac_accept_decrypt_error_frames_setf(uint8_t acceptdecrypterrorframes)
{
ASSERT_ERR((((uint32_t)acceptdecrypterrorframes << 11) & ~((uint32_t)0x00000800)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00000800)) | ((uint32_t)acceptdecrypterrorframes << 11));
}
/**
* @brief Returns the current value of the acceptBeacon field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptBeacon field's value will be returned.
*
* @return The current value of the acceptBeacon field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_beacon_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000400)) >> 10);
}
/**
* @brief Sets the acceptBeacon field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptbeacon - The value to set the field to.
*/
__INLINE void nxmac_accept_beacon_setf(uint8_t acceptbeacon)
{
ASSERT_ERR((((uint32_t)acceptbeacon << 10) & ~((uint32_t)0x00000400)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00000400)) | ((uint32_t)acceptbeacon << 10));
}
/**
* @brief Returns the current value of the acceptProbeResp field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptProbeResp field's value will be returned.
*
* @return The current value of the acceptProbeResp field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_probe_resp_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000200)) >> 9);
}
/**
* @brief Sets the acceptProbeResp field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptproberesp - The value to set the field to.
*/
__INLINE void nxmac_accept_probe_resp_setf(uint8_t acceptproberesp)
{
ASSERT_ERR((((uint32_t)acceptproberesp << 9) & ~((uint32_t)0x00000200)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00000200)) | ((uint32_t)acceptproberesp << 9));
}
/**
* @brief Returns the current value of the acceptProbeReq field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptProbeReq field's value will be returned.
*
* @return The current value of the acceptProbeReq field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_probe_req_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000100)) >> 8);
}
/**
* @brief Sets the acceptProbeReq field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptprobereq - The value to set the field to.
*/
__INLINE void nxmac_accept_probe_req_setf(uint8_t acceptprobereq)
{
ASSERT_ERR((((uint32_t)acceptprobereq << 8) & ~((uint32_t)0x00000100)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00000100)) | ((uint32_t)acceptprobereq << 8));
}
/**
* @brief Returns the current value of the acceptMyUnicast field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptMyUnicast field's value will be returned.
*
* @return The current value of the acceptMyUnicast field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_my_unicast_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000080)) >> 7);
}
/**
* @brief Sets the acceptMyUnicast field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptmyunicast - The value to set the field to.
*/
__INLINE void nxmac_accept_my_unicast_setf(uint8_t acceptmyunicast)
{
ASSERT_ERR((((uint32_t)acceptmyunicast << 7) & ~((uint32_t)0x00000080)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00000080)) | ((uint32_t)acceptmyunicast << 7));
}
/**
* @brief Returns the current value of the acceptUnicast field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptUnicast field's value will be returned.
*
* @return The current value of the acceptUnicast field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_unicast_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000040)) >> 6);
}
/**
* @brief Sets the acceptUnicast field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptunicast - The value to set the field to.
*/
__INLINE void nxmac_accept_unicast_setf(uint8_t acceptunicast)
{
ASSERT_ERR((((uint32_t)acceptunicast << 6) & ~((uint32_t)0x00000040)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00000040)) | ((uint32_t)acceptunicast << 6));
}
/**
* @brief Returns the current value of the acceptErrorFrames field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptErrorFrames field's value will be returned.
*
* @return The current value of the acceptErrorFrames field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_error_frames_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000020)) >> 5);
}
/**
* @brief Sets the acceptErrorFrames field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] accepterrorframes - The value to set the field to.
*/
__INLINE void nxmac_accept_error_frames_setf(uint8_t accepterrorframes)
{
ASSERT_ERR((((uint32_t)accepterrorframes << 5) & ~((uint32_t)0x00000020)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00000020)) | ((uint32_t)accepterrorframes << 5));
}
/**
* @brief Returns the current value of the acceptOtherBSSID field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptOtherBSSID field's value will be returned.
*
* @return The current value of the acceptOtherBSSID field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_other_bssid_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000010)) >> 4);
}
/**
* @brief Sets the acceptOtherBSSID field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptotherbssid - The value to set the field to.
*/
__INLINE void nxmac_accept_other_bssid_setf(uint8_t acceptotherbssid)
{
ASSERT_ERR((((uint32_t)acceptotherbssid << 4) & ~((uint32_t)0x00000010)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00000010)) | ((uint32_t)acceptotherbssid << 4));
}
/**
* @brief Returns the current value of the acceptBroadcast field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptBroadcast field's value will be returned.
*
* @return The current value of the acceptBroadcast field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_broadcast_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000008)) >> 3);
}
/**
* @brief Sets the acceptBroadcast field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptbroadcast - The value to set the field to.
*/
__INLINE void nxmac_accept_broadcast_setf(uint8_t acceptbroadcast)
{
ASSERT_ERR((((uint32_t)acceptbroadcast << 3) & ~((uint32_t)0x00000008)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00000008)) | ((uint32_t)acceptbroadcast << 3));
}
/**
* @brief Returns the current value of the acceptMulticast field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the acceptMulticast field's value will be returned.
*
* @return The current value of the acceptMulticast field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_accept_multicast_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000004)) >> 2);
}
/**
* @brief Sets the acceptMulticast field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] acceptmulticast - The value to set the field to.
*/
__INLINE void nxmac_accept_multicast_setf(uint8_t acceptmulticast)
{
ASSERT_ERR((((uint32_t)acceptmulticast << 2) & ~((uint32_t)0x00000004)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00000004)) | ((uint32_t)acceptmulticast << 2));
}
/**
* @brief Returns the current value of the dontDecrypt field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the dontDecrypt field's value will be returned.
*
* @return The current value of the dontDecrypt field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_dont_decrypt_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000002)) >> 1);
}
/**
* @brief Sets the dontDecrypt field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] dontdecrypt - The value to set the field to.
*/
__INLINE void nxmac_dont_decrypt_setf(uint8_t dontdecrypt)
{
ASSERT_ERR((((uint32_t)dontdecrypt << 1) & ~((uint32_t)0x00000002)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)dontdecrypt << 1));
}
/**
* @brief Returns the current value of the excUnencrypted field in the RX_CNTRL register.
*
* The RX_CNTRL register will be read and the excUnencrypted field's value will be returned.
*
* @return The current value of the excUnencrypted field in the RX_CNTRL register.
*/
__INLINE uint8_t nxmac_exc_unencrypted_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000001)) >> 0);
}
/**
* @brief Sets the excUnencrypted field of the RX_CNTRL register.
*
* The RX_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] excunencrypted - The value to set the field to.
*/
__INLINE void nxmac_exc_unencrypted_setf(uint8_t excunencrypted)
{
ASSERT_ERR((((uint32_t)excunencrypted << 0) & ~((uint32_t)0x00000001)) == 0);
REG_PL_WR(NXMAC_RX_CNTRL_ADDR, (REG_PL_RD(NXMAC_RX_CNTRL_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)excunencrypted << 0));
}
/// @}
/**
* @name BCN_CNTRL_1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:24 noBcnTxTime 0x0
* 23 impTBTTIn128Us 0
* 22:16 impTBTTPeriod 0x0
* 15:00 beaconInt 0x0
* </pre>
*
* @{
*/
/// Address of the BCN_CNTRL_1 register
#define NXMAC_BCN_CNTRL_1_ADDR 0xC0000064
/// Offset of the BCN_CNTRL_1 register from the base address
#define NXMAC_BCN_CNTRL_1_OFFSET 0x00000064
/// Index of the BCN_CNTRL_1 register
#define NXMAC_BCN_CNTRL_1_INDEX 0x00000019
/// Reset value of the BCN_CNTRL_1 register
#define NXMAC_BCN_CNTRL_1_RESET 0x00000000
/**
* @brief Returns the current value of the BCN_CNTRL_1 register.
* The BCN_CNTRL_1 register will be read and its value returned.
* @return The current value of the BCN_CNTRL_1 register.
*/
__INLINE uint32_t nxmac_bcn_cntrl_1_get(void)
{
return REG_PL_RD(NXMAC_BCN_CNTRL_1_ADDR);
}
/**
* @brief Sets the BCN_CNTRL_1 register to a value.
* The BCN_CNTRL_1 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_bcn_cntrl_1_set(uint32_t value)
{
REG_PL_WR(NXMAC_BCN_CNTRL_1_ADDR, value);
}
// field definitions
/// NO_BCN_TX_TIME field mask
#define NXMAC_NO_BCN_TX_TIME_MASK ((uint32_t)0xFF000000)
/// NO_BCN_TX_TIME field LSB position
#define NXMAC_NO_BCN_TX_TIME_LSB 24
/// NO_BCN_TX_TIME field width
#define NXMAC_NO_BCN_TX_TIME_WIDTH ((uint32_t)0x00000008)
/// IMP_TBTT_IN_128_US field bit
#define NXMAC_IMP_TBTT_IN_128_US_BIT ((uint32_t)0x00800000)
/// IMP_TBTT_IN_128_US field position
#define NXMAC_IMP_TBTT_IN_128_US_POS 23
/// IMP_TBTT_PERIOD field mask
#define NXMAC_IMP_TBTT_PERIOD_MASK ((uint32_t)0x007F0000)
/// IMP_TBTT_PERIOD field LSB position
#define NXMAC_IMP_TBTT_PERIOD_LSB 16
/// IMP_TBTT_PERIOD field width
#define NXMAC_IMP_TBTT_PERIOD_WIDTH ((uint32_t)0x00000007)
/// BEACON_INT field mask
#define NXMAC_BEACON_INT_MASK ((uint32_t)0x0000FFFF)
/// BEACON_INT field LSB position
#define NXMAC_BEACON_INT_LSB 0
/// BEACON_INT field width
#define NXMAC_BEACON_INT_WIDTH ((uint32_t)0x00000010)
/// NO_BCN_TX_TIME field reset value
#define NXMAC_NO_BCN_TX_TIME_RST 0x0
/// IMP_TBTT_IN_128_US field reset value
#define NXMAC_IMP_TBTT_IN_128_US_RST 0x0
/// IMP_TBTT_PERIOD field reset value
#define NXMAC_IMP_TBTT_PERIOD_RST 0x0
/// BEACON_INT field reset value
#define NXMAC_BEACON_INT_RST 0x0
/**
* @brief Constructs a value for the BCN_CNTRL_1 register given values for its fields
* and writes the value to the register.
*
* @param[in] nobcntxtime - The value to use for the noBcnTxTime field.
* @param[in] imptbttin128us - The value to use for the impTBTTIn128Us field.
* @param[in] imptbttperiod - The value to use for the impTBTTPeriod field.
* @param[in] beaconint - The value to use for the beaconInt field.
*/
__INLINE void nxmac_bcn_cntrl_1_pack(uint8_t nobcntxtime, uint8_t imptbttin128us, uint8_t imptbttperiod, uint16_t beaconint)
{
ASSERT_ERR((((uint32_t)nobcntxtime << 24) & ~((uint32_t)0xFF000000)) == 0);
ASSERT_ERR((((uint32_t)imptbttin128us << 23) & ~((uint32_t)0x00800000)) == 0);
ASSERT_ERR((((uint32_t)imptbttperiod << 16) & ~((uint32_t)0x007F0000)) == 0);
ASSERT_ERR((((uint32_t)beaconint << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_BCN_CNTRL_1_ADDR, ((uint32_t)nobcntxtime << 24) | ((uint32_t)imptbttin128us << 23) | ((uint32_t)imptbttperiod << 16) | ((uint32_t)beaconint << 0));
}
/**
* @brief Unpacks BCN_CNTRL_1's fields from current value of the BCN_CNTRL_1 register.
*
* Reads the BCN_CNTRL_1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] nobcntxtime - Will be populated with the current value of this field from the register.
* @param[out] imptbttin128us - Will be populated with the current value of this field from the register.
* @param[out] imptbttperiod - Will be populated with the current value of this field from the register.
* @param[out] beaconint - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_bcn_cntrl_1_unpack(uint8_t *nobcntxtime, uint8_t *imptbttin128us, uint8_t *imptbttperiod, uint16_t *beaconint)
{
uint32_t localVal = REG_PL_RD(NXMAC_BCN_CNTRL_1_ADDR);
*nobcntxtime = (localVal & ((uint32_t)0xFF000000)) >> 24;
*imptbttin128us = (localVal & ((uint32_t)0x00800000)) >> 23;
*imptbttperiod = (localVal & ((uint32_t)0x007F0000)) >> 16;
*beaconint = (localVal & ((uint32_t)0x0000FFFF)) >> 0;
}
/**
* @brief Returns the current value of the noBcnTxTime field in the BCN_CNTRL_1 register.
*
* The BCN_CNTRL_1 register will be read and the noBcnTxTime field's value will be returned.
*
* @return The current value of the noBcnTxTime field in the BCN_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_no_bcn_tx_time_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BCN_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0xFF000000)) >> 24);
}
/**
* @brief Sets the noBcnTxTime field of the BCN_CNTRL_1 register.
*
* The BCN_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] nobcntxtime - The value to set the field to.
*/
__INLINE void nxmac_no_bcn_tx_time_setf(uint8_t nobcntxtime)
{
ASSERT_ERR((((uint32_t)nobcntxtime << 24) & ~((uint32_t)0xFF000000)) == 0);
REG_PL_WR(NXMAC_BCN_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_BCN_CNTRL_1_ADDR) & ~((uint32_t)0xFF000000)) | ((uint32_t)nobcntxtime << 24));
}
/**
* @brief Returns the current value of the impTBTTIn128Us field in the BCN_CNTRL_1 register.
*
* The BCN_CNTRL_1 register will be read and the impTBTTIn128Us field's value will be returned.
*
* @return The current value of the impTBTTIn128Us field in the BCN_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_imp_tbtt_in_128_us_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BCN_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x00800000)) >> 23);
}
/**
* @brief Sets the impTBTTIn128Us field of the BCN_CNTRL_1 register.
*
* The BCN_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] imptbttin128us - The value to set the field to.
*/
__INLINE void nxmac_imp_tbtt_in_128_us_setf(uint8_t imptbttin128us)
{
ASSERT_ERR((((uint32_t)imptbttin128us << 23) & ~((uint32_t)0x00800000)) == 0);
REG_PL_WR(NXMAC_BCN_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_BCN_CNTRL_1_ADDR) & ~((uint32_t)0x00800000)) | ((uint32_t)imptbttin128us << 23));
}
/**
* @brief Returns the current value of the impTBTTPeriod field in the BCN_CNTRL_1 register.
*
* The BCN_CNTRL_1 register will be read and the impTBTTPeriod field's value will be returned.
*
* @return The current value of the impTBTTPeriod field in the BCN_CNTRL_1 register.
*/
__INLINE uint8_t nxmac_imp_tbtt_period_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BCN_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x007F0000)) >> 16);
}
/**
* @brief Sets the impTBTTPeriod field of the BCN_CNTRL_1 register.
*
* The BCN_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] imptbttperiod - The value to set the field to.
*/
__INLINE void nxmac_imp_tbtt_period_setf(uint8_t imptbttperiod)
{
ASSERT_ERR((((uint32_t)imptbttperiod << 16) & ~((uint32_t)0x007F0000)) == 0);
REG_PL_WR(NXMAC_BCN_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_BCN_CNTRL_1_ADDR) & ~((uint32_t)0x007F0000)) | ((uint32_t)imptbttperiod << 16));
}
/**
* @brief Returns the current value of the beaconInt field in the BCN_CNTRL_1 register.
*
* The BCN_CNTRL_1 register will be read and the beaconInt field's value will be returned.
*
* @return The current value of the beaconInt field in the BCN_CNTRL_1 register.
*/
__INLINE uint16_t nxmac_beacon_int_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BCN_CNTRL_1_ADDR);
return ((localVal & ((uint32_t)0x0000FFFF)) >> 0);
}
/**
* @brief Sets the beaconInt field of the BCN_CNTRL_1 register.
*
* The BCN_CNTRL_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] beaconint - The value to set the field to.
*/
__INLINE void nxmac_beacon_int_setf(uint16_t beaconint)
{
ASSERT_ERR((((uint32_t)beaconint << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_BCN_CNTRL_1_ADDR, (REG_PL_RD(NXMAC_BCN_CNTRL_1_ADDR) & ~((uint32_t)0x0000FFFF)) | ((uint32_t)beaconint << 0));
}
/// @}
/**
* @name BCN_CNTRL_2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:16 aid 0x0
* 15:08 timOffset 0x0
* 07:00 bcnUpdateOffset 0x0
* </pre>
*
* @{
*/
/// Address of the BCN_CNTRL_2 register
#define NXMAC_BCN_CNTRL_2_ADDR 0xC0000068
/// Offset of the BCN_CNTRL_2 register from the base address
#define NXMAC_BCN_CNTRL_2_OFFSET 0x00000068
/// Index of the BCN_CNTRL_2 register
#define NXMAC_BCN_CNTRL_2_INDEX 0x0000001A
/// Reset value of the BCN_CNTRL_2 register
#define NXMAC_BCN_CNTRL_2_RESET 0x00000000
/**
* @brief Returns the current value of the BCN_CNTRL_2 register.
* The BCN_CNTRL_2 register will be read and its value returned.
* @return The current value of the BCN_CNTRL_2 register.
*/
__INLINE uint32_t nxmac_bcn_cntrl_2_get(void)
{
return REG_PL_RD(NXMAC_BCN_CNTRL_2_ADDR);
}
/**
* @brief Sets the BCN_CNTRL_2 register to a value.
* The BCN_CNTRL_2 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_bcn_cntrl_2_set(uint32_t value)
{
REG_PL_WR(NXMAC_BCN_CNTRL_2_ADDR, value);
}
// field definitions
/// AID field mask
#define NXMAC_AID_MASK ((uint32_t)0xFFFF0000)
/// AID field LSB position
#define NXMAC_AID_LSB 16
/// AID field width
#define NXMAC_AID_WIDTH ((uint32_t)0x00000010)
/// TIM_OFFSET field mask
#define NXMAC_TIM_OFFSET_MASK ((uint32_t)0x0000FF00)
/// TIM_OFFSET field LSB position
#define NXMAC_TIM_OFFSET_LSB 8
/// TIM_OFFSET field width
#define NXMAC_TIM_OFFSET_WIDTH ((uint32_t)0x00000008)
/// BCN_UPDATE_OFFSET field mask
#define NXMAC_BCN_UPDATE_OFFSET_MASK ((uint32_t)0x000000FF)
/// BCN_UPDATE_OFFSET field LSB position
#define NXMAC_BCN_UPDATE_OFFSET_LSB 0
/// BCN_UPDATE_OFFSET field width
#define NXMAC_BCN_UPDATE_OFFSET_WIDTH ((uint32_t)0x00000008)
/// AID field reset value
#define NXMAC_AID_RST 0x0
/// TIM_OFFSET field reset value
#define NXMAC_TIM_OFFSET_RST 0x0
/// BCN_UPDATE_OFFSET field reset value
#define NXMAC_BCN_UPDATE_OFFSET_RST 0x0
/**
* @brief Constructs a value for the BCN_CNTRL_2 register given values for its fields
* and writes the value to the register.
*
* @param[in] aid - The value to use for the aid field.
* @param[in] timoffset - The value to use for the timOffset field.
* @param[in] bcnupdateoffset - The value to use for the bcnUpdateOffset field.
*/
__INLINE void nxmac_bcn_cntrl_2_pack(uint16_t aid, uint8_t timoffset, uint8_t bcnupdateoffset)
{
ASSERT_ERR((((uint32_t)aid << 16) & ~((uint32_t)0xFFFF0000)) == 0);
ASSERT_ERR((((uint32_t)timoffset << 8) & ~((uint32_t)0x0000FF00)) == 0);
ASSERT_ERR((((uint32_t)bcnupdateoffset << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_BCN_CNTRL_2_ADDR, ((uint32_t)aid << 16) | ((uint32_t)timoffset << 8) | ((uint32_t)bcnupdateoffset << 0));
}
/**
* @brief Unpacks BCN_CNTRL_2's fields from current value of the BCN_CNTRL_2 register.
*
* Reads the BCN_CNTRL_2 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] aid - Will be populated with the current value of this field from the register.
* @param[out] timoffset - Will be populated with the current value of this field from the register.
* @param[out] bcnupdateoffset - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_bcn_cntrl_2_unpack(uint16_t *aid, uint8_t *timoffset, uint8_t *bcnupdateoffset)
{
uint32_t localVal = REG_PL_RD(NXMAC_BCN_CNTRL_2_ADDR);
*aid = (localVal & ((uint32_t)0xFFFF0000)) >> 16;
*timoffset = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*bcnupdateoffset = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the aid field in the BCN_CNTRL_2 register.
*
* The BCN_CNTRL_2 register will be read and the aid field's value will be returned.
*
* @return The current value of the aid field in the BCN_CNTRL_2 register.
*/
__INLINE uint16_t nxmac_aid_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BCN_CNTRL_2_ADDR);
return ((localVal & ((uint32_t)0xFFFF0000)) >> 16);
}
/**
* @brief Sets the aid field of the BCN_CNTRL_2 register.
*
* The BCN_CNTRL_2 register will be read, modified to contain the new field value, and written.
*
* @param[in] aid - The value to set the field to.
*/
__INLINE void nxmac_aid_setf(uint16_t aid)
{
ASSERT_ERR((((uint32_t)aid << 16) & ~((uint32_t)0xFFFF0000)) == 0);
REG_PL_WR(NXMAC_BCN_CNTRL_2_ADDR, (REG_PL_RD(NXMAC_BCN_CNTRL_2_ADDR) & ~((uint32_t)0xFFFF0000)) | ((uint32_t)aid << 16));
}
/**
* @brief Returns the current value of the timOffset field in the BCN_CNTRL_2 register.
*
* The BCN_CNTRL_2 register will be read and the timOffset field's value will be returned.
*
* @return The current value of the timOffset field in the BCN_CNTRL_2 register.
*/
__INLINE uint8_t nxmac_tim_offset_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BCN_CNTRL_2_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Sets the timOffset field of the BCN_CNTRL_2 register.
*
* The BCN_CNTRL_2 register will be read, modified to contain the new field value, and written.
*
* @param[in] timoffset - The value to set the field to.
*/
__INLINE void nxmac_tim_offset_setf(uint8_t timoffset)
{
ASSERT_ERR((((uint32_t)timoffset << 8) & ~((uint32_t)0x0000FF00)) == 0);
REG_PL_WR(NXMAC_BCN_CNTRL_2_ADDR, (REG_PL_RD(NXMAC_BCN_CNTRL_2_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)timoffset << 8));
}
/**
* @brief Returns the current value of the bcnUpdateOffset field in the BCN_CNTRL_2 register.
*
* The BCN_CNTRL_2 register will be read and the bcnUpdateOffset field's value will be returned.
*
* @return The current value of the bcnUpdateOffset field in the BCN_CNTRL_2 register.
*/
__INLINE uint8_t nxmac_bcn_update_offset_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BCN_CNTRL_2_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the bcnUpdateOffset field of the BCN_CNTRL_2 register.
*
* The BCN_CNTRL_2 register will be read, modified to contain the new field value, and written.
*
* @param[in] bcnupdateoffset - The value to set the field to.
*/
__INLINE void nxmac_bcn_update_offset_setf(uint8_t bcnupdateoffset)
{
ASSERT_ERR((((uint32_t)bcnupdateoffset << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_BCN_CNTRL_2_ADDR, (REG_PL_RD(NXMAC_BCN_CNTRL_2_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)bcnupdateoffset << 0));
}
/// @}
/**
* @name DTIM_CFP_1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31 dtimUpdatedBySW 0
* 15:08 cfpPeriod 0x0
* 07:00 dtimPeriod 0x0
* </pre>
*
* @{
*/
/// Address of the DTIM_CFP_1 register
#define NXMAC_DTIM_CFP_1_ADDR 0xC0000090
/// Offset of the DTIM_CFP_1 register from the base address
#define NXMAC_DTIM_CFP_1_OFFSET 0x00000090
/// Index of the DTIM_CFP_1 register
#define NXMAC_DTIM_CFP_1_INDEX 0x00000024
/// Reset value of the DTIM_CFP_1 register
#define NXMAC_DTIM_CFP_1_RESET 0x00000000
/**
* @brief Returns the current value of the DTIM_CFP_1 register.
* The DTIM_CFP_1 register will be read and its value returned.
* @return The current value of the DTIM_CFP_1 register.
*/
__INLINE uint32_t nxmac_dtim_cfp_1_get(void)
{
return REG_PL_RD(NXMAC_DTIM_CFP_1_ADDR);
}
/**
* @brief Sets the DTIM_CFP_1 register to a value.
* The DTIM_CFP_1 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_dtim_cfp_1_set(uint32_t value)
{
REG_PL_WR(NXMAC_DTIM_CFP_1_ADDR, value);
}
// field definitions
/// DTIM_UPDATED_BY_SW field bit
#define NXMAC_DTIM_UPDATED_BY_SW_BIT ((uint32_t)0x80000000)
/// DTIM_UPDATED_BY_SW field position
#define NXMAC_DTIM_UPDATED_BY_SW_POS 31
/// CFP_PERIOD field mask
#define NXMAC_CFP_PERIOD_MASK ((uint32_t)0x0000FF00)
/// CFP_PERIOD field LSB position
#define NXMAC_CFP_PERIOD_LSB 8
/// CFP_PERIOD field width
#define NXMAC_CFP_PERIOD_WIDTH ((uint32_t)0x00000008)
/// DTIM_PERIOD field mask
#define NXMAC_DTIM_PERIOD_MASK ((uint32_t)0x000000FF)
/// DTIM_PERIOD field LSB position
#define NXMAC_DTIM_PERIOD_LSB 0
/// DTIM_PERIOD field width
#define NXMAC_DTIM_PERIOD_WIDTH ((uint32_t)0x00000008)
/// DTIM_UPDATED_BY_SW field reset value
#define NXMAC_DTIM_UPDATED_BY_SW_RST 0x0
/// CFP_PERIOD field reset value
#define NXMAC_CFP_PERIOD_RST 0x0
/// DTIM_PERIOD field reset value
#define NXMAC_DTIM_PERIOD_RST 0x0
/**
* @brief Constructs a value for the DTIM_CFP_1 register given values for its fields
* and writes the value to the register.
*
* @param[in] dtimupdatedbysw - The value to use for the dtimUpdatedBySW field.
* @param[in] cfpperiod - The value to use for the cfpPeriod field.
* @param[in] dtimperiod - The value to use for the dtimPeriod field.
*/
__INLINE void nxmac_dtim_cfp_1_pack(uint8_t dtimupdatedbysw, uint8_t cfpperiod, uint8_t dtimperiod)
{
ASSERT_ERR((((uint32_t)dtimupdatedbysw << 31) & ~((uint32_t)0x80000000)) == 0);
ASSERT_ERR((((uint32_t)cfpperiod << 8) & ~((uint32_t)0x0000FF00)) == 0);
ASSERT_ERR((((uint32_t)dtimperiod << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_DTIM_CFP_1_ADDR, ((uint32_t)dtimupdatedbysw << 31) | ((uint32_t)cfpperiod << 8) | ((uint32_t)dtimperiod << 0));
}
/**
* @brief Unpacks DTIM_CFP_1's fields from current value of the DTIM_CFP_1 register.
*
* Reads the DTIM_CFP_1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] dtimupdatedbysw - Will be populated with the current value of this field from the register.
* @param[out] cfpperiod - Will be populated with the current value of this field from the register.
* @param[out] dtimperiod - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_dtim_cfp_1_unpack(uint8_t *dtimupdatedbysw, uint8_t *cfpperiod, uint8_t *dtimperiod)
{
uint32_t localVal = REG_PL_RD(NXMAC_DTIM_CFP_1_ADDR);
*dtimupdatedbysw = (localVal & ((uint32_t)0x80000000)) >> 31;
*cfpperiod = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*dtimperiod = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the dtimUpdatedBySW field in the DTIM_CFP_1 register.
*
* The DTIM_CFP_1 register will be read and the dtimUpdatedBySW field's value will be returned.
*
* @return The current value of the dtimUpdatedBySW field in the DTIM_CFP_1 register.
*/
__INLINE uint8_t nxmac_dtim_updated_by_sw_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_DTIM_CFP_1_ADDR);
return ((localVal & ((uint32_t)0x80000000)) >> 31);
}
/**
* @brief Sets the dtimUpdatedBySW field of the DTIM_CFP_1 register.
*
* The DTIM_CFP_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] dtimupdatedbysw - The value to set the field to.
*/
__INLINE void nxmac_dtim_updated_by_sw_setf(uint8_t dtimupdatedbysw)
{
ASSERT_ERR((((uint32_t)dtimupdatedbysw << 31) & ~((uint32_t)0x80000000)) == 0);
REG_PL_WR(NXMAC_DTIM_CFP_1_ADDR, (REG_PL_RD(NXMAC_DTIM_CFP_1_ADDR) & ~((uint32_t)0x80000000)) | ((uint32_t)dtimupdatedbysw << 31));
}
/**
* @brief Returns the current value of the cfpPeriod field in the DTIM_CFP_1 register.
*
* The DTIM_CFP_1 register will be read and the cfpPeriod field's value will be returned.
*
* @return The current value of the cfpPeriod field in the DTIM_CFP_1 register.
*/
__INLINE uint8_t nxmac_cfp_period_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_DTIM_CFP_1_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Sets the cfpPeriod field of the DTIM_CFP_1 register.
*
* The DTIM_CFP_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] cfpperiod - The value to set the field to.
*/
__INLINE void nxmac_cfp_period_setf(uint8_t cfpperiod)
{
ASSERT_ERR((((uint32_t)cfpperiod << 8) & ~((uint32_t)0x0000FF00)) == 0);
REG_PL_WR(NXMAC_DTIM_CFP_1_ADDR, (REG_PL_RD(NXMAC_DTIM_CFP_1_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)cfpperiod << 8));
}
/**
* @brief Returns the current value of the dtimPeriod field in the DTIM_CFP_1 register.
*
* The DTIM_CFP_1 register will be read and the dtimPeriod field's value will be returned.
*
* @return The current value of the dtimPeriod field in the DTIM_CFP_1 register.
*/
__INLINE uint8_t nxmac_dtim_period_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_DTIM_CFP_1_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the dtimPeriod field of the DTIM_CFP_1 register.
*
* The DTIM_CFP_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] dtimperiod - The value to set the field to.
*/
__INLINE void nxmac_dtim_period_setf(uint8_t dtimperiod)
{
ASSERT_ERR((((uint32_t)dtimperiod << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_DTIM_CFP_1_ADDR, (REG_PL_RD(NXMAC_DTIM_CFP_1_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)dtimperiod << 0));
}
/// @}
/**
* @name DTIM_CFP_2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 cfpMaxDuration 0x0
* </pre>
*
* @{
*/
/// Address of the DTIM_CFP_2 register
#define NXMAC_DTIM_CFP_2_ADDR 0xC0000094
/// Offset of the DTIM_CFP_2 register from the base address
#define NXMAC_DTIM_CFP_2_OFFSET 0x00000094
/// Index of the DTIM_CFP_2 register
#define NXMAC_DTIM_CFP_2_INDEX 0x00000025
/// Reset value of the DTIM_CFP_2 register
#define NXMAC_DTIM_CFP_2_RESET 0x00000000
/**
* @brief Returns the current value of the DTIM_CFP_2 register.
* The DTIM_CFP_2 register will be read and its value returned.
* @return The current value of the DTIM_CFP_2 register.
*/
__INLINE uint32_t nxmac_dtim_cfp_2_get(void)
{
return REG_PL_RD(NXMAC_DTIM_CFP_2_ADDR);
}
/**
* @brief Sets the DTIM_CFP_2 register to a value.
* The DTIM_CFP_2 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_dtim_cfp_2_set(uint32_t value)
{
REG_PL_WR(NXMAC_DTIM_CFP_2_ADDR, value);
}
// field definitions
/// CFP_MAX_DURATION field mask
#define NXMAC_CFP_MAX_DURATION_MASK ((uint32_t)0x0000FFFF)
/// CFP_MAX_DURATION field LSB position
#define NXMAC_CFP_MAX_DURATION_LSB 0
/// CFP_MAX_DURATION field width
#define NXMAC_CFP_MAX_DURATION_WIDTH ((uint32_t)0x00000010)
/// CFP_MAX_DURATION field reset value
#define NXMAC_CFP_MAX_DURATION_RST 0x0
/**
* @brief Returns the current value of the cfpMaxDuration field in the DTIM_CFP_2 register.
*
* The DTIM_CFP_2 register will be read and the cfpMaxDuration field's value will be returned.
*
* @return The current value of the cfpMaxDuration field in the DTIM_CFP_2 register.
*/
__INLINE uint16_t nxmac_cfp_max_duration_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_DTIM_CFP_2_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0x0000FFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the cfpMaxDuration field of the DTIM_CFP_2 register.
*
* The DTIM_CFP_2 register will be read, modified to contain the new field value, and written.
*
* @param[in] cfpmaxduration - The value to set the field to.
*/
__INLINE void nxmac_cfp_max_duration_setf(uint16_t cfpmaxduration)
{
ASSERT_ERR((((uint32_t)cfpmaxduration << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_DTIM_CFP_2_ADDR, (uint32_t)cfpmaxduration << 0);
}
/// @}
/**
* @name RETRY_LIMITS register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:08 dot11LongRetryLimit 0x4
* 07:00 dot11ShortRetryLimit 0x7
* </pre>
*
* @{
*/
/// Address of the RETRY_LIMITS register
#define NXMAC_RETRY_LIMITS_ADDR 0xC0000098
/// Offset of the RETRY_LIMITS register from the base address
#define NXMAC_RETRY_LIMITS_OFFSET 0x00000098
/// Index of the RETRY_LIMITS register
#define NXMAC_RETRY_LIMITS_INDEX 0x00000026
/// Reset value of the RETRY_LIMITS register
#define NXMAC_RETRY_LIMITS_RESET 0x00000407
/**
* @brief Returns the current value of the RETRY_LIMITS register.
* The RETRY_LIMITS register will be read and its value returned.
* @return The current value of the RETRY_LIMITS register.
*/
__INLINE uint32_t nxmac_retry_limits_get(void)
{
return REG_PL_RD(NXMAC_RETRY_LIMITS_ADDR);
}
/**
* @brief Sets the RETRY_LIMITS register to a value.
* The RETRY_LIMITS register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_retry_limits_set(uint32_t value)
{
REG_PL_WR(NXMAC_RETRY_LIMITS_ADDR, value);
}
// field definitions
/// DOT_11_LONG_RETRY_LIMIT field mask
#define NXMAC_DOT_11_LONG_RETRY_LIMIT_MASK ((uint32_t)0x0000FF00)
/// DOT_11_LONG_RETRY_LIMIT field LSB position
#define NXMAC_DOT_11_LONG_RETRY_LIMIT_LSB 8
/// DOT_11_LONG_RETRY_LIMIT field width
#define NXMAC_DOT_11_LONG_RETRY_LIMIT_WIDTH ((uint32_t)0x00000008)
/// DOT_11_SHORT_RETRY_LIMIT field mask
#define NXMAC_DOT_11_SHORT_RETRY_LIMIT_MASK ((uint32_t)0x000000FF)
/// DOT_11_SHORT_RETRY_LIMIT field LSB position
#define NXMAC_DOT_11_SHORT_RETRY_LIMIT_LSB 0
/// DOT_11_SHORT_RETRY_LIMIT field width
#define NXMAC_DOT_11_SHORT_RETRY_LIMIT_WIDTH ((uint32_t)0x00000008)
/// DOT_11_LONG_RETRY_LIMIT field reset value
#define NXMAC_DOT_11_LONG_RETRY_LIMIT_RST 0x4
/// DOT_11_SHORT_RETRY_LIMIT field reset value
#define NXMAC_DOT_11_SHORT_RETRY_LIMIT_RST 0x7
/**
* @brief Constructs a value for the RETRY_LIMITS register given values for its fields
* and writes the value to the register.
*
* @param[in] dot11longretrylimit - The value to use for the dot11LongRetryLimit field.
* @param[in] dot11shortretrylimit - The value to use for the dot11ShortRetryLimit field.
*/
__INLINE void nxmac_retry_limits_pack(uint8_t dot11longretrylimit, uint8_t dot11shortretrylimit)
{
ASSERT_ERR((((uint32_t)dot11longretrylimit << 8) & ~((uint32_t)0x0000FF00)) == 0);
ASSERT_ERR((((uint32_t)dot11shortretrylimit << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_RETRY_LIMITS_ADDR, ((uint32_t)dot11longretrylimit << 8) | ((uint32_t)dot11shortretrylimit << 0));
}
/**
* @brief Unpacks RETRY_LIMITS's fields from current value of the RETRY_LIMITS register.
*
* Reads the RETRY_LIMITS register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] dot11longretrylimit - Will be populated with the current value of this field from the register.
* @param[out] dot11shortretrylimit - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_retry_limits_unpack(uint8_t *dot11longretrylimit, uint8_t *dot11shortretrylimit)
{
uint32_t localVal = REG_PL_RD(NXMAC_RETRY_LIMITS_ADDR);
*dot11longretrylimit = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*dot11shortretrylimit = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the dot11LongRetryLimit field in the RETRY_LIMITS register.
*
* The RETRY_LIMITS register will be read and the dot11LongRetryLimit field's value will be returned.
*
* @return The current value of the dot11LongRetryLimit field in the RETRY_LIMITS register.
*/
__INLINE uint8_t nxmac_dot_11_long_retry_limit_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RETRY_LIMITS_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Sets the dot11LongRetryLimit field of the RETRY_LIMITS register.
*
* The RETRY_LIMITS register will be read, modified to contain the new field value, and written.
*
* @param[in] dot11longretrylimit - The value to set the field to.
*/
__INLINE void nxmac_dot_11_long_retry_limit_setf(uint8_t dot11longretrylimit)
{
ASSERT_ERR((((uint32_t)dot11longretrylimit << 8) & ~((uint32_t)0x0000FF00)) == 0);
REG_PL_WR(NXMAC_RETRY_LIMITS_ADDR, (REG_PL_RD(NXMAC_RETRY_LIMITS_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)dot11longretrylimit << 8));
}
/**
* @brief Returns the current value of the dot11ShortRetryLimit field in the RETRY_LIMITS register.
*
* The RETRY_LIMITS register will be read and the dot11ShortRetryLimit field's value will be returned.
*
* @return The current value of the dot11ShortRetryLimit field in the RETRY_LIMITS register.
*/
__INLINE uint8_t nxmac_dot_11_short_retry_limit_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RETRY_LIMITS_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the dot11ShortRetryLimit field of the RETRY_LIMITS register.
*
* The RETRY_LIMITS register will be read, modified to contain the new field value, and written.
*
* @param[in] dot11shortretrylimit - The value to set the field to.
*/
__INLINE void nxmac_dot_11_short_retry_limit_setf(uint8_t dot11shortretrylimit)
{
ASSERT_ERR((((uint32_t)dot11shortretrylimit << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_RETRY_LIMITS_ADDR, (REG_PL_RD(NXMAC_RETRY_LIMITS_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)dot11shortretrylimit << 0));
}
/// @}
/**
* @name BB_SERVICE register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 28:26 maxPHYNtx 0x2
* 23:16 bbServiceB 0x0
* 15:00 bbServiceA 0x0
* </pre>
*
* @{
*/
/// Address of the BB_SERVICE register
#define NXMAC_BB_SERVICE_ADDR 0xC000009C
/// Offset of the BB_SERVICE register from the base address
#define NXMAC_BB_SERVICE_OFFSET 0x0000009C
/// Index of the BB_SERVICE register
#define NXMAC_BB_SERVICE_INDEX 0x00000027
/// Reset value of the BB_SERVICE register
#define NXMAC_BB_SERVICE_RESET 0x08000000
/**
* @brief Returns the current value of the BB_SERVICE register.
* The BB_SERVICE register will be read and its value returned.
* @return The current value of the BB_SERVICE register.
*/
__INLINE uint32_t nxmac_bb_service_get(void)
{
return REG_PL_RD(NXMAC_BB_SERVICE_ADDR);
}
/**
* @brief Sets the BB_SERVICE register to a value.
* The BB_SERVICE register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_bb_service_set(uint32_t value)
{
REG_PL_WR(NXMAC_BB_SERVICE_ADDR, value);
}
// field definitions
/// MAX_PHY_NTX field mask
#define NXMAC_MAX_PHY_NTX_MASK ((uint32_t)0x1C000000)
/// MAX_PHY_NTX field LSB position
#define NXMAC_MAX_PHY_NTX_LSB 26
/// MAX_PHY_NTX field width
#define NXMAC_MAX_PHY_NTX_WIDTH ((uint32_t)0x00000003)
/// BB_SERVICE_B field mask
#define NXMAC_BB_SERVICE_B_MASK ((uint32_t)0x00FF0000)
/// BB_SERVICE_B field LSB position
#define NXMAC_BB_SERVICE_B_LSB 16
/// BB_SERVICE_B field width
#define NXMAC_BB_SERVICE_B_WIDTH ((uint32_t)0x00000008)
/// BB_SERVICE_A field mask
#define NXMAC_BB_SERVICE_A_MASK ((uint32_t)0x0000FFFF)
/// BB_SERVICE_A field LSB position
#define NXMAC_BB_SERVICE_A_LSB 0
/// BB_SERVICE_A field width
#define NXMAC_BB_SERVICE_A_WIDTH ((uint32_t)0x00000010)
/// MAX_PHY_NTX field reset value
#define NXMAC_MAX_PHY_NTX_RST 0x2
/// BB_SERVICE_B field reset value
#define NXMAC_BB_SERVICE_B_RST 0x0
/// BB_SERVICE_A field reset value
#define NXMAC_BB_SERVICE_A_RST 0x0
/**
* @brief Constructs a value for the BB_SERVICE register given values for its fields
* and writes the value to the register.
*
* @param[in] maxphyntx - The value to use for the maxPHYNtx field.
* @param[in] bbserviceb - The value to use for the bbServiceB field.
* @param[in] bbservicea - The value to use for the bbServiceA field.
*/
__INLINE void nxmac_bb_service_pack(uint8_t maxphyntx, uint8_t bbserviceb, uint16_t bbservicea)
{
ASSERT_ERR((((uint32_t)maxphyntx << 26) & ~((uint32_t)0x1C000000)) == 0);
ASSERT_ERR((((uint32_t)bbserviceb << 16) & ~((uint32_t)0x00FF0000)) == 0);
ASSERT_ERR((((uint32_t)bbservicea << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_BB_SERVICE_ADDR, ((uint32_t)maxphyntx << 26) | ((uint32_t)bbserviceb << 16) | ((uint32_t)bbservicea << 0));
}
/**
* @brief Unpacks BB_SERVICE's fields from current value of the BB_SERVICE register.
*
* Reads the BB_SERVICE register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] maxphyntx - Will be populated with the current value of this field from the register.
* @param[out] bbserviceb - Will be populated with the current value of this field from the register.
* @param[out] bbservicea - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_bb_service_unpack(uint8_t *maxphyntx, uint8_t *bbserviceb, uint16_t *bbservicea)
{
uint32_t localVal = REG_PL_RD(NXMAC_BB_SERVICE_ADDR);
*maxphyntx = (localVal & ((uint32_t)0x1C000000)) >> 26;
*bbserviceb = (localVal & ((uint32_t)0x00FF0000)) >> 16;
*bbservicea = (localVal & ((uint32_t)0x0000FFFF)) >> 0;
}
/**
* @brief Returns the current value of the maxPHYNtx field in the BB_SERVICE register.
*
* The BB_SERVICE register will be read and the maxPHYNtx field's value will be returned.
*
* @return The current value of the maxPHYNtx field in the BB_SERVICE register.
*/
__INLINE uint8_t nxmac_max_phy_ntx_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BB_SERVICE_ADDR);
return ((localVal & ((uint32_t)0x1C000000)) >> 26);
}
/**
* @brief Sets the maxPHYNtx field of the BB_SERVICE register.
*
* The BB_SERVICE register will be read, modified to contain the new field value, and written.
*
* @param[in] maxphyntx - The value to set the field to.
*/
__INLINE void nxmac_max_phy_ntx_setf(uint8_t maxphyntx)
{
ASSERT_ERR((((uint32_t)maxphyntx << 26) & ~((uint32_t)0x1C000000)) == 0);
REG_PL_WR(NXMAC_BB_SERVICE_ADDR, (REG_PL_RD(NXMAC_BB_SERVICE_ADDR) & ~((uint32_t)0x1C000000)) | ((uint32_t)maxphyntx << 26));
}
/**
* @brief Returns the current value of the bbServiceB field in the BB_SERVICE register.
*
* The BB_SERVICE register will be read and the bbServiceB field's value will be returned.
*
* @return The current value of the bbServiceB field in the BB_SERVICE register.
*/
__INLINE uint8_t nxmac_bb_service_b_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BB_SERVICE_ADDR);
return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
}
/**
* @brief Sets the bbServiceB field of the BB_SERVICE register.
*
* The BB_SERVICE register will be read, modified to contain the new field value, and written.
*
* @param[in] bbserviceb - The value to set the field to.
*/
__INLINE void nxmac_bb_service_b_setf(uint8_t bbserviceb)
{
ASSERT_ERR((((uint32_t)bbserviceb << 16) & ~((uint32_t)0x00FF0000)) == 0);
REG_PL_WR(NXMAC_BB_SERVICE_ADDR, (REG_PL_RD(NXMAC_BB_SERVICE_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)bbserviceb << 16));
}
/**
* @brief Returns the current value of the bbServiceA field in the BB_SERVICE register.
*
* The BB_SERVICE register will be read and the bbServiceA field's value will be returned.
*
* @return The current value of the bbServiceA field in the BB_SERVICE register.
*/
__INLINE uint16_t nxmac_bb_service_a_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_BB_SERVICE_ADDR);
return ((localVal & ((uint32_t)0x0000FFFF)) >> 0);
}
/**
* @brief Sets the bbServiceA field of the BB_SERVICE register.
*
* The BB_SERVICE register will be read, modified to contain the new field value, and written.
*
* @param[in] bbservicea - The value to set the field to.
*/
__INLINE void nxmac_bb_service_a_setf(uint16_t bbservicea)
{
ASSERT_ERR((((uint32_t)bbservicea << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_BB_SERVICE_ADDR, (REG_PL_RD(NXMAC_BB_SERVICE_ADDR) & ~((uint32_t)0x0000FFFF)) | ((uint32_t)bbservicea << 0));
}
/// @}
/**
* @name MAX_POWER_LEVEL register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:08 dsssMaxPwrLevel 0x4
* 07:00 ofdmMaxPwrLevel 0x4
* </pre>
*
* @{
*/
/// Address of the MAX_POWER_LEVEL register
#define NXMAC_MAX_POWER_LEVEL_ADDR 0xC00000A0
/// Offset of the MAX_POWER_LEVEL register from the base address
#define NXMAC_MAX_POWER_LEVEL_OFFSET 0x000000A0
/// Index of the MAX_POWER_LEVEL register
#define NXMAC_MAX_POWER_LEVEL_INDEX 0x00000028
/// Reset value of the MAX_POWER_LEVEL register
#define NXMAC_MAX_POWER_LEVEL_RESET 0x00000404
/**
* @brief Returns the current value of the MAX_POWER_LEVEL register.
* The MAX_POWER_LEVEL register will be read and its value returned.
* @return The current value of the MAX_POWER_LEVEL register.
*/
__INLINE uint32_t nxmac_max_power_level_get(void)
{
return REG_PL_RD(NXMAC_MAX_POWER_LEVEL_ADDR);
}
/**
* @brief Sets the MAX_POWER_LEVEL register to a value.
* The MAX_POWER_LEVEL register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_max_power_level_set(uint32_t value)
{
REG_PL_WR(NXMAC_MAX_POWER_LEVEL_ADDR, value);
}
// field definitions
/// DSSS_MAX_PWR_LEVEL field mask
#define NXMAC_DSSS_MAX_PWR_LEVEL_MASK ((uint32_t)0x0000FF00)
/// DSSS_MAX_PWR_LEVEL field LSB position
#define NXMAC_DSSS_MAX_PWR_LEVEL_LSB 8
/// DSSS_MAX_PWR_LEVEL field width
#define NXMAC_DSSS_MAX_PWR_LEVEL_WIDTH ((uint32_t)0x00000008)
/// OFDM_MAX_PWR_LEVEL field mask
#define NXMAC_OFDM_MAX_PWR_LEVEL_MASK ((uint32_t)0x000000FF)
/// OFDM_MAX_PWR_LEVEL field LSB position
#define NXMAC_OFDM_MAX_PWR_LEVEL_LSB 0
/// OFDM_MAX_PWR_LEVEL field width
#define NXMAC_OFDM_MAX_PWR_LEVEL_WIDTH ((uint32_t)0x00000008)
/// DSSS_MAX_PWR_LEVEL field reset value
#define NXMAC_DSSS_MAX_PWR_LEVEL_RST 0x4
/// OFDM_MAX_PWR_LEVEL field reset value
#define NXMAC_OFDM_MAX_PWR_LEVEL_RST 0x4
/**
* @brief Constructs a value for the MAX_POWER_LEVEL register given values for its fields
* and writes the value to the register.
*
* @param[in] dsssmaxpwrlevel - The value to use for the dsssMaxPwrLevel field.
* @param[in] ofdmmaxpwrlevel - The value to use for the ofdmMaxPwrLevel field.
*/
__INLINE void nxmac_max_power_level_pack(uint8_t dsssmaxpwrlevel, uint8_t ofdmmaxpwrlevel)
{
ASSERT_ERR((((uint32_t)dsssmaxpwrlevel << 8) & ~((uint32_t)0x0000FF00)) == 0);
ASSERT_ERR((((uint32_t)ofdmmaxpwrlevel << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_MAX_POWER_LEVEL_ADDR, ((uint32_t)dsssmaxpwrlevel << 8) | ((uint32_t)ofdmmaxpwrlevel << 0));
}
/**
* @brief Unpacks MAX_POWER_LEVEL's fields from current value of the MAX_POWER_LEVEL register.
*
* Reads the MAX_POWER_LEVEL register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] dsssmaxpwrlevel - Will be populated with the current value of this field from the register.
* @param[out] ofdmmaxpwrlevel - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_max_power_level_unpack(uint8_t *dsssmaxpwrlevel, uint8_t *ofdmmaxpwrlevel)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAX_POWER_LEVEL_ADDR);
*dsssmaxpwrlevel = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*ofdmmaxpwrlevel = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the dsssMaxPwrLevel field in the MAX_POWER_LEVEL register.
*
* The MAX_POWER_LEVEL register will be read and the dsssMaxPwrLevel field's value will be returned.
*
* @return The current value of the dsssMaxPwrLevel field in the MAX_POWER_LEVEL register.
*/
__INLINE uint8_t nxmac_dsss_max_pwr_level_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAX_POWER_LEVEL_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Sets the dsssMaxPwrLevel field of the MAX_POWER_LEVEL register.
*
* The MAX_POWER_LEVEL register will be read, modified to contain the new field value, and written.
*
* @param[in] dsssmaxpwrlevel - The value to set the field to.
*/
__INLINE void nxmac_dsss_max_pwr_level_setf(uint8_t dsssmaxpwrlevel)
{
ASSERT_ERR((((uint32_t)dsssmaxpwrlevel << 8) & ~((uint32_t)0x0000FF00)) == 0);
REG_PL_WR(NXMAC_MAX_POWER_LEVEL_ADDR, (REG_PL_RD(NXMAC_MAX_POWER_LEVEL_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)dsssmaxpwrlevel << 8));
}
/**
* @brief Returns the current value of the ofdmMaxPwrLevel field in the MAX_POWER_LEVEL register.
*
* The MAX_POWER_LEVEL register will be read and the ofdmMaxPwrLevel field's value will be returned.
*
* @return The current value of the ofdmMaxPwrLevel field in the MAX_POWER_LEVEL register.
*/
__INLINE uint8_t nxmac_ofdm_max_pwr_level_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAX_POWER_LEVEL_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the ofdmMaxPwrLevel field of the MAX_POWER_LEVEL register.
*
* The MAX_POWER_LEVEL register will be read, modified to contain the new field value, and written.
*
* @param[in] ofdmmaxpwrlevel - The value to set the field to.
*/
__INLINE void nxmac_ofdm_max_pwr_level_setf(uint8_t ofdmmaxpwrlevel)
{
ASSERT_ERR((((uint32_t)ofdmmaxpwrlevel << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_MAX_POWER_LEVEL_ADDR, (REG_PL_RD(NXMAC_MAX_POWER_LEVEL_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)ofdmmaxpwrlevel << 0));
}
/// @}
/**
* @name ENCR_KEY_0 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 encrKeyRAMWord0 0x0
* </pre>
*
* @{
*/
/// Address of the ENCR_KEY_0 register
#define NXMAC_ENCR_KEY_0_ADDR 0xC00000AC
/// Offset of the ENCR_KEY_0 register from the base address
#define NXMAC_ENCR_KEY_0_OFFSET 0x000000AC
/// Index of the ENCR_KEY_0 register
#define NXMAC_ENCR_KEY_0_INDEX 0x0000002B
/// Reset value of the ENCR_KEY_0 register
#define NXMAC_ENCR_KEY_0_RESET 0x00000000
/**
* @brief Returns the current value of the ENCR_KEY_0 register.
* The ENCR_KEY_0 register will be read and its value returned.
* @return The current value of the ENCR_KEY_0 register.
*/
__INLINE uint32_t nxmac_encr_key_0_get(void)
{
return REG_PL_RD(NXMAC_ENCR_KEY_0_ADDR);
}
/**
* @brief Sets the ENCR_KEY_0 register to a value.
* The ENCR_KEY_0 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_encr_key_0_set(uint32_t value)
{
REG_PL_WR(NXMAC_ENCR_KEY_0_ADDR, value);
}
// field definitions
/// ENCR_KEY_RAM_WORD_0 field mask
#define NXMAC_ENCR_KEY_RAM_WORD_0_MASK ((uint32_t)0xFFFFFFFF)
/// ENCR_KEY_RAM_WORD_0 field LSB position
#define NXMAC_ENCR_KEY_RAM_WORD_0_LSB 0
/// ENCR_KEY_RAM_WORD_0 field width
#define NXMAC_ENCR_KEY_RAM_WORD_0_WIDTH ((uint32_t)0x00000020)
/// ENCR_KEY_RAM_WORD_0 field reset value
#define NXMAC_ENCR_KEY_RAM_WORD_0_RST 0x0
/**
* @brief Returns the current value of the encrKeyRAMWord0 field in the ENCR_KEY_0 register.
*
* The ENCR_KEY_0 register will be read and the encrKeyRAMWord0 field's value will be returned.
*
* @return The current value of the encrKeyRAMWord0 field in the ENCR_KEY_0 register.
*/
__INLINE uint32_t nxmac_encr_key_ram_word_0_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_KEY_0_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the encrKeyRAMWord0 field of the ENCR_KEY_0 register.
*
* The ENCR_KEY_0 register will be read, modified to contain the new field value, and written.
*
* @param[in] encrkeyramword0 - The value to set the field to.
*/
__INLINE void nxmac_encr_key_ram_word_0_setf(uint32_t encrkeyramword0)
{
ASSERT_ERR((((uint32_t)encrkeyramword0 << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_ENCR_KEY_0_ADDR, (uint32_t)encrkeyramword0 << 0);
}
/// @}
/**
* @name ENCR_KEY_1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 encrKeyRAMWord1 0x0
* </pre>
*
* @{
*/
/// Address of the ENCR_KEY_1 register
#define NXMAC_ENCR_KEY_1_ADDR 0xC00000B0
/// Offset of the ENCR_KEY_1 register from the base address
#define NXMAC_ENCR_KEY_1_OFFSET 0x000000B0
/// Index of the ENCR_KEY_1 register
#define NXMAC_ENCR_KEY_1_INDEX 0x0000002C
/// Reset value of the ENCR_KEY_1 register
#define NXMAC_ENCR_KEY_1_RESET 0x00000000
/**
* @brief Returns the current value of the ENCR_KEY_1 register.
* The ENCR_KEY_1 register will be read and its value returned.
* @return The current value of the ENCR_KEY_1 register.
*/
__INLINE uint32_t nxmac_encr_key_1_get(void)
{
return REG_PL_RD(NXMAC_ENCR_KEY_1_ADDR);
}
/**
* @brief Sets the ENCR_KEY_1 register to a value.
* The ENCR_KEY_1 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_encr_key_1_set(uint32_t value)
{
REG_PL_WR(NXMAC_ENCR_KEY_1_ADDR, value);
}
// field definitions
/// ENCR_KEY_RAM_WORD_1 field mask
#define NXMAC_ENCR_KEY_RAM_WORD_1_MASK ((uint32_t)0xFFFFFFFF)
/// ENCR_KEY_RAM_WORD_1 field LSB position
#define NXMAC_ENCR_KEY_RAM_WORD_1_LSB 0
/// ENCR_KEY_RAM_WORD_1 field width
#define NXMAC_ENCR_KEY_RAM_WORD_1_WIDTH ((uint32_t)0x00000020)
/// ENCR_KEY_RAM_WORD_1 field reset value
#define NXMAC_ENCR_KEY_RAM_WORD_1_RST 0x0
/**
* @brief Returns the current value of the encrKeyRAMWord1 field in the ENCR_KEY_1 register.
*
* The ENCR_KEY_1 register will be read and the encrKeyRAMWord1 field's value will be returned.
*
* @return The current value of the encrKeyRAMWord1 field in the ENCR_KEY_1 register.
*/
__INLINE uint32_t nxmac_encr_key_ram_word_1_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_KEY_1_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the encrKeyRAMWord1 field of the ENCR_KEY_1 register.
*
* The ENCR_KEY_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] encrkeyramword1 - The value to set the field to.
*/
__INLINE void nxmac_encr_key_ram_word_1_setf(uint32_t encrkeyramword1)
{
ASSERT_ERR((((uint32_t)encrkeyramword1 << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_ENCR_KEY_1_ADDR, (uint32_t)encrkeyramword1 << 0);
}
/// @}
/**
* @name ENCR_KEY_2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 encrKeyRAMWord2 0x0
* </pre>
*
* @{
*/
/// Address of the ENCR_KEY_2 register
#define NXMAC_ENCR_KEY_2_ADDR 0xC00000B4
/// Offset of the ENCR_KEY_2 register from the base address
#define NXMAC_ENCR_KEY_2_OFFSET 0x000000B4
/// Index of the ENCR_KEY_2 register
#define NXMAC_ENCR_KEY_2_INDEX 0x0000002D
/// Reset value of the ENCR_KEY_2 register
#define NXMAC_ENCR_KEY_2_RESET 0x00000000
/**
* @brief Returns the current value of the ENCR_KEY_2 register.
* The ENCR_KEY_2 register will be read and its value returned.
* @return The current value of the ENCR_KEY_2 register.
*/
__INLINE uint32_t nxmac_encr_key_2_get(void)
{
return REG_PL_RD(NXMAC_ENCR_KEY_2_ADDR);
}
/**
* @brief Sets the ENCR_KEY_2 register to a value.
* The ENCR_KEY_2 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_encr_key_2_set(uint32_t value)
{
REG_PL_WR(NXMAC_ENCR_KEY_2_ADDR, value);
}
// field definitions
/// ENCR_KEY_RAM_WORD_2 field mask
#define NXMAC_ENCR_KEY_RAM_WORD_2_MASK ((uint32_t)0xFFFFFFFF)
/// ENCR_KEY_RAM_WORD_2 field LSB position
#define NXMAC_ENCR_KEY_RAM_WORD_2_LSB 0
/// ENCR_KEY_RAM_WORD_2 field width
#define NXMAC_ENCR_KEY_RAM_WORD_2_WIDTH ((uint32_t)0x00000020)
/// ENCR_KEY_RAM_WORD_2 field reset value
#define NXMAC_ENCR_KEY_RAM_WORD_2_RST 0x0
/**
* @brief Returns the current value of the encrKeyRAMWord2 field in the ENCR_KEY_2 register.
*
* The ENCR_KEY_2 register will be read and the encrKeyRAMWord2 field's value will be returned.
*
* @return The current value of the encrKeyRAMWord2 field in the ENCR_KEY_2 register.
*/
__INLINE uint32_t nxmac_encr_key_ram_word_2_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_KEY_2_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the encrKeyRAMWord2 field of the ENCR_KEY_2 register.
*
* The ENCR_KEY_2 register will be read, modified to contain the new field value, and written.
*
* @param[in] encrkeyramword2 - The value to set the field to.
*/
__INLINE void nxmac_encr_key_ram_word_2_setf(uint32_t encrkeyramword2)
{
ASSERT_ERR((((uint32_t)encrkeyramword2 << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_ENCR_KEY_2_ADDR, (uint32_t)encrkeyramword2 << 0);
}
/// @}
/**
* @name ENCR_KEY_3 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 encrKeyRAMWord3 0x0
* </pre>
*
* @{
*/
/// Address of the ENCR_KEY_3 register
#define NXMAC_ENCR_KEY_3_ADDR 0xC00000B8
/// Offset of the ENCR_KEY_3 register from the base address
#define NXMAC_ENCR_KEY_3_OFFSET 0x000000B8
/// Index of the ENCR_KEY_3 register
#define NXMAC_ENCR_KEY_3_INDEX 0x0000002E
/// Reset value of the ENCR_KEY_3 register
#define NXMAC_ENCR_KEY_3_RESET 0x00000000
/**
* @brief Returns the current value of the ENCR_KEY_3 register.
* The ENCR_KEY_3 register will be read and its value returned.
* @return The current value of the ENCR_KEY_3 register.
*/
__INLINE uint32_t nxmac_encr_key_3_get(void)
{
return REG_PL_RD(NXMAC_ENCR_KEY_3_ADDR);
}
/**
* @brief Sets the ENCR_KEY_3 register to a value.
* The ENCR_KEY_3 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_encr_key_3_set(uint32_t value)
{
REG_PL_WR(NXMAC_ENCR_KEY_3_ADDR, value);
}
// field definitions
/// ENCR_KEY_RAM_WORD_3 field mask
#define NXMAC_ENCR_KEY_RAM_WORD_3_MASK ((uint32_t)0xFFFFFFFF)
/// ENCR_KEY_RAM_WORD_3 field LSB position
#define NXMAC_ENCR_KEY_RAM_WORD_3_LSB 0
/// ENCR_KEY_RAM_WORD_3 field width
#define NXMAC_ENCR_KEY_RAM_WORD_3_WIDTH ((uint32_t)0x00000020)
/// ENCR_KEY_RAM_WORD_3 field reset value
#define NXMAC_ENCR_KEY_RAM_WORD_3_RST 0x0
/**
* @brief Returns the current value of the encrKeyRAMWord3 field in the ENCR_KEY_3 register.
*
* The ENCR_KEY_3 register will be read and the encrKeyRAMWord3 field's value will be returned.
*
* @return The current value of the encrKeyRAMWord3 field in the ENCR_KEY_3 register.
*/
__INLINE uint32_t nxmac_encr_key_ram_word_3_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_KEY_3_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the encrKeyRAMWord3 field of the ENCR_KEY_3 register.
*
* The ENCR_KEY_3 register will be read, modified to contain the new field value, and written.
*
* @param[in] encrkeyramword3 - The value to set the field to.
*/
__INLINE void nxmac_encr_key_ram_word_3_setf(uint32_t encrkeyramword3)
{
ASSERT_ERR((((uint32_t)encrkeyramword3 << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_ENCR_KEY_3_ADDR, (uint32_t)encrkeyramword3 << 0);
}
/// @}
/**
* @name ENCR_MAC_ADDR_LOW register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 macAddrRAMLow 0xFFFFFFFF
* </pre>
*
* @{
*/
/// Address of the ENCR_MAC_ADDR_LOW register
#define NXMAC_ENCR_MAC_ADDR_LOW_ADDR 0xC00000BC
/// Offset of the ENCR_MAC_ADDR_LOW register from the base address
#define NXMAC_ENCR_MAC_ADDR_LOW_OFFSET 0x000000BC
/// Index of the ENCR_MAC_ADDR_LOW register
#define NXMAC_ENCR_MAC_ADDR_LOW_INDEX 0x0000002F
/// Reset value of the ENCR_MAC_ADDR_LOW register
#define NXMAC_ENCR_MAC_ADDR_LOW_RESET 0xFFFFFFFF
/**
* @brief Returns the current value of the ENCR_MAC_ADDR_LOW register.
* The ENCR_MAC_ADDR_LOW register will be read and its value returned.
* @return The current value of the ENCR_MAC_ADDR_LOW register.
*/
__INLINE uint32_t nxmac_encr_mac_addr_low_get(void)
{
return REG_PL_RD(NXMAC_ENCR_MAC_ADDR_LOW_ADDR);
}
/**
* @brief Sets the ENCR_MAC_ADDR_LOW register to a value.
* The ENCR_MAC_ADDR_LOW register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_encr_mac_addr_low_set(uint32_t value)
{
REG_PL_WR(NXMAC_ENCR_MAC_ADDR_LOW_ADDR, value);
}
// field definitions
/// MAC_ADDR_RAM_LOW field mask
#define NXMAC_MAC_ADDR_RAM_LOW_MASK ((uint32_t)0xFFFFFFFF)
/// MAC_ADDR_RAM_LOW field LSB position
#define NXMAC_MAC_ADDR_RAM_LOW_LSB 0
/// MAC_ADDR_RAM_LOW field width
#define NXMAC_MAC_ADDR_RAM_LOW_WIDTH ((uint32_t)0x00000020)
/// MAC_ADDR_RAM_LOW field reset value
#define NXMAC_MAC_ADDR_RAM_LOW_RST 0xFFFFFFFF
/**
* @brief Returns the current value of the macAddrRAMLow field in the ENCR_MAC_ADDR_LOW register.
*
* The ENCR_MAC_ADDR_LOW register will be read and the macAddrRAMLow field's value will be returned.
*
* @return The current value of the macAddrRAMLow field in the ENCR_MAC_ADDR_LOW register.
*/
__INLINE uint32_t nxmac_mac_addr_ram_low_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_MAC_ADDR_LOW_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the macAddrRAMLow field of the ENCR_MAC_ADDR_LOW register.
*
* The ENCR_MAC_ADDR_LOW register will be read, modified to contain the new field value, and written.
*
* @param[in] macaddrramlow - The value to set the field to.
*/
__INLINE void nxmac_mac_addr_ram_low_setf(uint32_t macaddrramlow)
{
ASSERT_ERR((((uint32_t)macaddrramlow << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_ENCR_MAC_ADDR_LOW_ADDR, (uint32_t)macaddrramlow << 0);
}
/// @}
/**
* @name ENCR_MAC_ADDR_HIGH register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:00 macAddrRAMHigh 0xFFFF
* </pre>
*
* @{
*/
/// Address of the ENCR_MAC_ADDR_HIGH register
#define NXMAC_ENCR_MAC_ADDR_HIGH_ADDR 0xC00000C0
/// Offset of the ENCR_MAC_ADDR_HIGH register from the base address
#define NXMAC_ENCR_MAC_ADDR_HIGH_OFFSET 0x000000C0
/// Index of the ENCR_MAC_ADDR_HIGH register
#define NXMAC_ENCR_MAC_ADDR_HIGH_INDEX 0x00000030
/// Reset value of the ENCR_MAC_ADDR_HIGH register
#define NXMAC_ENCR_MAC_ADDR_HIGH_RESET 0x0000FFFF
/**
* @brief Returns the current value of the ENCR_MAC_ADDR_HIGH register.
* The ENCR_MAC_ADDR_HIGH register will be read and its value returned.
* @return The current value of the ENCR_MAC_ADDR_HIGH register.
*/
__INLINE uint32_t nxmac_encr_mac_addr_high_get(void)
{
return REG_PL_RD(NXMAC_ENCR_MAC_ADDR_HIGH_ADDR);
}
/**
* @brief Sets the ENCR_MAC_ADDR_HIGH register to a value.
* The ENCR_MAC_ADDR_HIGH register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_encr_mac_addr_high_set(uint32_t value)
{
REG_PL_WR(NXMAC_ENCR_MAC_ADDR_HIGH_ADDR, value);
}
// field definitions
/// MAC_ADDR_RAM_HIGH field mask
#define NXMAC_MAC_ADDR_RAM_HIGH_MASK ((uint32_t)0x0000FFFF)
/// MAC_ADDR_RAM_HIGH field LSB position
#define NXMAC_MAC_ADDR_RAM_HIGH_LSB 0
/// MAC_ADDR_RAM_HIGH field width
#define NXMAC_MAC_ADDR_RAM_HIGH_WIDTH ((uint32_t)0x00000010)
/// MAC_ADDR_RAM_HIGH field reset value
#define NXMAC_MAC_ADDR_RAM_HIGH_RST 0xFFFF
/**
* @brief Returns the current value of the macAddrRAMHigh field in the ENCR_MAC_ADDR_HIGH register.
*
* The ENCR_MAC_ADDR_HIGH register will be read and the macAddrRAMHigh field's value will be returned.
*
* @return The current value of the macAddrRAMHigh field in the ENCR_MAC_ADDR_HIGH register.
*/
__INLINE uint16_t nxmac_mac_addr_ram_high_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_MAC_ADDR_HIGH_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0x0000FFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the macAddrRAMHigh field of the ENCR_MAC_ADDR_HIGH register.
*
* The ENCR_MAC_ADDR_HIGH register will be read, modified to contain the new field value, and written.
*
* @param[in] macaddrramhigh - The value to set the field to.
*/
__INLINE void nxmac_mac_addr_ram_high_setf(uint16_t macaddrramhigh)
{
ASSERT_ERR((((uint32_t)macaddrramhigh << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_ENCR_MAC_ADDR_HIGH_ADDR, (uint32_t)macaddrramhigh << 0);
}
/// @}
/**
* @name ENCR_CNTRL register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31 newRead 0
* 30 newWrite 0
* 29 newSearch 0
* 28 searchError 0
* 25:16 keyIndexRAM 0x0
* 10:08 cTypeRAM 0x0
* 07:04 vlanIDRAM 0x0
* 03:02 sppRAM 0x0
* 01 useDefKeyRAM 0
* 00 cLenRAM 0
* </pre>
*
* @{
*/
enum
{
CTYPERAM_NULL_KEY = 0,
CTYPERAM_WEP,
CTYPERAM_TKIP,
CTYPERAM_CCMP,
};
/// Address of the ENCR_CNTRL register
#define NXMAC_ENCR_CNTRL_ADDR 0xC00000C4
/// Offset of the ENCR_CNTRL register from the base address
#define NXMAC_ENCR_CNTRL_OFFSET 0x000000C4
/// Index of the ENCR_CNTRL register
#define NXMAC_ENCR_CNTRL_INDEX 0x00000031
/// Reset value of the ENCR_CNTRL register
#define NXMAC_ENCR_CNTRL_RESET 0x00000000
/**
* @brief Returns the current value of the ENCR_CNTRL register.
* The ENCR_CNTRL register will be read and its value returned.
* @return The current value of the ENCR_CNTRL register.
*/
__INLINE uint32_t nxmac_encr_cntrl_get(void)
{
return REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR);
}
/**
* @brief Sets the ENCR_CNTRL register to a value.
* The ENCR_CNTRL register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_encr_cntrl_set(uint32_t value)
{
REG_PL_WR(NXMAC_ENCR_CNTRL_ADDR, value);
}
// field definitions
/// NEW_READ field bit
#define NXMAC_NEW_READ_BIT ((uint32_t)0x80000000)
/// NEW_READ field position
#define NXMAC_NEW_READ_POS 31
/// NEW_WRITE field bit
#define NXMAC_NEW_WRITE_BIT ((uint32_t)0x40000000)
/// NEW_WRITE field position
#define NXMAC_NEW_WRITE_POS 30
/// NEW_SEARCH field bit
#define NXMAC_NEW_SEARCH_BIT ((uint32_t)0x20000000)
/// NEW_SEARCH field position
#define NXMAC_NEW_SEARCH_POS 29
/// SEARCH_ERROR field bit
#define NXMAC_SEARCH_ERROR_BIT ((uint32_t)0x10000000)
/// SEARCH_ERROR field position
#define NXMAC_SEARCH_ERROR_POS 28
/// KEY_INDEX_RAM field mask
#define NXMAC_KEY_INDEX_RAM_MASK ((uint32_t)0x03FF0000)
/// KEY_INDEX_RAM field LSB position
#define NXMAC_KEY_INDEX_RAM_LSB 16
/// KEY_INDEX_RAM field width
#define NXMAC_KEY_INDEX_RAM_WIDTH ((uint32_t)0x0000000A)
/// C_TYPE_RAM field mask
#define NXMAC_C_TYPE_RAM_MASK ((uint32_t)0x00000700)
/// C_TYPE_RAM field LSB position
#define NXMAC_C_TYPE_RAM_LSB 8
/// C_TYPE_RAM field width
#define NXMAC_C_TYPE_RAM_WIDTH ((uint32_t)0x00000003)
/// VLAN_IDRAM field mask
#define NXMAC_VLAN_IDRAM_MASK ((uint32_t)0x000000F0)
/// VLAN_IDRAM field LSB position
#define NXMAC_VLAN_IDRAM_LSB 4
/// VLAN_IDRAM field width
#define NXMAC_VLAN_IDRAM_WIDTH ((uint32_t)0x00000004)
/// SPP_RAM field mask
#define NXMAC_SPP_RAM_MASK ((uint32_t)0x0000000C)
/// SPP_RAM field LSB position
#define NXMAC_SPP_RAM_LSB 2
/// SPP_RAM field width
#define NXMAC_SPP_RAM_WIDTH ((uint32_t)0x00000002)
/// USE_DEF_KEY_RAM field bit
#define NXMAC_USE_DEF_KEY_RAM_BIT ((uint32_t)0x00000002)
/// USE_DEF_KEY_RAM field position
#define NXMAC_USE_DEF_KEY_RAM_POS 1
/// C_LEN_RAM field bit
#define NXMAC_C_LEN_RAM_BIT ((uint32_t)0x00000001)
/// C_LEN_RAM field position
#define NXMAC_C_LEN_RAM_POS 0
/// NEW_READ field reset value
#define NXMAC_NEW_READ_RST 0x0
/// NEW_WRITE field reset value
#define NXMAC_NEW_WRITE_RST 0x0
/// NEW_SEARCH field reset value
#define NXMAC_NEW_SEARCH_RST 0x0
/// SEARCH_ERROR field reset value
#define NXMAC_SEARCH_ERROR_RST 0x0
/// KEY_INDEX_RAM field reset value
#define NXMAC_KEY_INDEX_RAM_RST 0x0
/// C_TYPE_RAM field reset value
#define NXMAC_C_TYPE_RAM_RST 0x0
/// VLAN_IDRAM field reset value
#define NXMAC_VLAN_IDRAM_RST 0x0
/// SPP_RAM field reset value
#define NXMAC_SPP_RAM_RST 0x0
/// USE_DEF_KEY_RAM field reset value
#define NXMAC_USE_DEF_KEY_RAM_RST 0x0
/// C_LEN_RAM field reset value
#define NXMAC_C_LEN_RAM_RST 0x0
/**
* @brief Constructs a value for the ENCR_CNTRL register given values for its fields
* and writes the value to the register.
*
* @param[in] newread - The value to use for the newRead field.
* @param[in] newwrite - The value to use for the newWrite field.
* @param[in] newsearch - The value to use for the newSearch field.
* @param[in] searcherror - The value to use for the searchError field.
* @param[in] keyindexram - The value to use for the keyIndexRAM field.
* @param[in] ctyperam - The value to use for the cTypeRAM field.
* @param[in] vlanidram - The value to use for the vlanIDRAM field.
* @param[in] sppram - The value to use for the sppRAM field.
* @param[in] usedefkeyram - The value to use for the useDefKeyRAM field.
* @param[in] clenram - The value to use for the cLenRAM field.
*/
__INLINE void nxmac_encr_cntrl_pack(uint8_t newread, uint8_t newwrite, uint8_t newsearch, uint8_t searcherror, uint16_t keyindexram, uint8_t ctyperam, uint8_t vlanidram, uint8_t sppram, uint8_t usedefkeyram, uint8_t clenram)
{
ASSERT_ERR((((uint32_t)newread << 31) & ~((uint32_t)0x80000000)) == 0);
ASSERT_ERR((((uint32_t)newwrite << 30) & ~((uint32_t)0x40000000)) == 0);
ASSERT_ERR((((uint32_t)newsearch << 29) & ~((uint32_t)0x20000000)) == 0);
ASSERT_ERR((((uint32_t)searcherror << 28) & ~((uint32_t)0x10000000)) == 0);
ASSERT_ERR((((uint32_t)keyindexram << 16) & ~((uint32_t)0x03FF0000)) == 0);
ASSERT_ERR((((uint32_t)ctyperam << 8) & ~((uint32_t)0x00000700)) == 0);
ASSERT_ERR((((uint32_t)vlanidram << 4) & ~((uint32_t)0x000000F0)) == 0);
ASSERT_ERR((((uint32_t)sppram << 2) & ~((uint32_t)0x0000000C)) == 0);
ASSERT_ERR((((uint32_t)usedefkeyram << 1) & ~((uint32_t)0x00000002)) == 0);
ASSERT_ERR((((uint32_t)clenram << 0) & ~((uint32_t)0x00000001)) == 0);
REG_PL_WR(NXMAC_ENCR_CNTRL_ADDR, ((uint32_t)newread << 31) | ((uint32_t)newwrite << 30) | ((uint32_t)newsearch << 29) | ((uint32_t)searcherror << 28) | ((uint32_t)keyindexram << 16) | ((uint32_t)ctyperam << 8) | ((uint32_t)vlanidram << 4) | ((uint32_t)sppram << 2) | ((uint32_t)usedefkeyram << 1) | ((uint32_t)clenram << 0));
}
/**
* @brief Unpacks ENCR_CNTRL's fields from current value of the ENCR_CNTRL register.
*
* Reads the ENCR_CNTRL register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] newread - Will be populated with the current value of this field from the register.
* @param[out] newwrite - Will be populated with the current value of this field from the register.
* @param[out] newsearch - Will be populated with the current value of this field from the register.
* @param[out] searcherror - Will be populated with the current value of this field from the register.
* @param[out] keyindexram - Will be populated with the current value of this field from the register.
* @param[out] ctyperam - Will be populated with the current value of this field from the register.
* @param[out] vlanidram - Will be populated with the current value of this field from the register.
* @param[out] sppram - Will be populated with the current value of this field from the register.
* @param[out] usedefkeyram - Will be populated with the current value of this field from the register.
* @param[out] clenram - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_encr_cntrl_unpack(uint8_t *newread, uint8_t *newwrite, uint8_t *newsearch, uint8_t *searcherror, uint16_t *keyindexram, uint8_t *ctyperam, uint8_t *vlanidram, uint8_t *sppram, uint8_t *usedefkeyram, uint8_t *clenram)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR);
*newread = (localVal & ((uint32_t)0x80000000)) >> 31;
*newwrite = (localVal & ((uint32_t)0x40000000)) >> 30;
*newsearch = (localVal & ((uint32_t)0x20000000)) >> 29;
*searcherror = (localVal & ((uint32_t)0x10000000)) >> 28;
*keyindexram = (localVal & ((uint32_t)0x03FF0000)) >> 16;
*ctyperam = (localVal & ((uint32_t)0x00000700)) >> 8;
*vlanidram = (localVal & ((uint32_t)0x000000F0)) >> 4;
*sppram = (localVal & ((uint32_t)0x0000000C)) >> 2;
*usedefkeyram = (localVal & ((uint32_t)0x00000002)) >> 1;
*clenram = (localVal & ((uint32_t)0x00000001)) >> 0;
}
/**
* @brief Returns the current value of the newRead field in the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read and the newRead field's value will be returned.
*
* @return The current value of the newRead field in the ENCR_CNTRL register.
*/
__INLINE uint8_t nxmac_new_read_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x80000000)) >> 31);
}
/**
* @brief Sets the newRead field of the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] newread - The value to set the field to.
*/
__INLINE void nxmac_new_read_setf(uint8_t newread)
{
ASSERT_ERR((((uint32_t)newread << 31) & ~((uint32_t)0x80000000)) == 0);
REG_PL_WR(NXMAC_ENCR_CNTRL_ADDR, (REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR) & ~((uint32_t)0x80000000)) | ((uint32_t)newread << 31));
}
/**
* @brief Returns the current value of the newWrite field in the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read and the newWrite field's value will be returned.
*
* @return The current value of the newWrite field in the ENCR_CNTRL register.
*/
__INLINE uint8_t nxmac_new_write_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x40000000)) >> 30);
}
/**
* @brief Sets the newWrite field of the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] newwrite - The value to set the field to.
*/
__INLINE void nxmac_new_write_setf(uint8_t newwrite)
{
ASSERT_ERR((((uint32_t)newwrite << 30) & ~((uint32_t)0x40000000)) == 0);
REG_PL_WR(NXMAC_ENCR_CNTRL_ADDR, (REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR) & ~((uint32_t)0x40000000)) | ((uint32_t)newwrite << 30));
}
/**
* @brief Returns the current value of the newSearch field in the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read and the newSearch field's value will be returned.
*
* @return The current value of the newSearch field in the ENCR_CNTRL register.
*/
__INLINE uint8_t nxmac_new_search_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x20000000)) >> 29);
}
/**
* @brief Sets the newSearch field of the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] newsearch - The value to set the field to.
*/
__INLINE void nxmac_new_search_setf(uint8_t newsearch)
{
ASSERT_ERR((((uint32_t)newsearch << 29) & ~((uint32_t)0x20000000)) == 0);
REG_PL_WR(NXMAC_ENCR_CNTRL_ADDR, (REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR) & ~((uint32_t)0x20000000)) | ((uint32_t)newsearch << 29));
}
/**
* @brief Returns the current value of the searchError field in the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read and the searchError field's value will be returned.
*
* @return The current value of the searchError field in the ENCR_CNTRL register.
*/
__INLINE uint8_t nxmac_search_error_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x10000000)) >> 28);
}
/**
* @brief Sets the searchError field of the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] searcherror - The value to set the field to.
*/
__INLINE void nxmac_search_error_setf(uint8_t searcherror)
{
ASSERT_ERR((((uint32_t)searcherror << 28) & ~((uint32_t)0x10000000)) == 0);
REG_PL_WR(NXMAC_ENCR_CNTRL_ADDR, (REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR) & ~((uint32_t)0x10000000)) | ((uint32_t)searcherror << 28));
}
/**
* @brief Returns the current value of the keyIndexRAM field in the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read and the keyIndexRAM field's value will be returned.
*
* @return The current value of the keyIndexRAM field in the ENCR_CNTRL register.
*/
__INLINE uint16_t nxmac_key_index_ram_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x03FF0000)) >> 16);
}
/**
* @brief Sets the keyIndexRAM field of the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] keyindexram - The value to set the field to.
*/
__INLINE void nxmac_key_index_ram_setf(uint16_t keyindexram)
{
ASSERT_ERR((((uint32_t)keyindexram << 16) & ~((uint32_t)0x03FF0000)) == 0);
REG_PL_WR(NXMAC_ENCR_CNTRL_ADDR, (REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR) & ~((uint32_t)0x03FF0000)) | ((uint32_t)keyindexram << 16));
}
/**
* @brief Returns the current value of the cTypeRAM field in the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read and the cTypeRAM field's value will be returned.
*
* @return The current value of the cTypeRAM field in the ENCR_CNTRL register.
*/
__INLINE uint8_t nxmac_c_type_ram_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000700)) >> 8);
}
/**
* @brief Sets the cTypeRAM field of the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] ctyperam - The value to set the field to.
*/
__INLINE void nxmac_c_type_ram_setf(uint8_t ctyperam)
{
ASSERT_ERR((((uint32_t)ctyperam << 8) & ~((uint32_t)0x00000700)) == 0);
REG_PL_WR(NXMAC_ENCR_CNTRL_ADDR, (REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR) & ~((uint32_t)0x00000700)) | ((uint32_t)ctyperam << 8));
}
/**
* @brief Returns the current value of the vlanIDRAM field in the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read and the vlanIDRAM field's value will be returned.
*
* @return The current value of the vlanIDRAM field in the ENCR_CNTRL register.
*/
__INLINE uint8_t nxmac_vlan_idram_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x000000F0)) >> 4);
}
/**
* @brief Sets the vlanIDRAM field of the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] vlanidram - The value to set the field to.
*/
__INLINE void nxmac_vlan_idram_setf(uint8_t vlanidram)
{
ASSERT_ERR((((uint32_t)vlanidram << 4) & ~((uint32_t)0x000000F0)) == 0);
REG_PL_WR(NXMAC_ENCR_CNTRL_ADDR, (REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR) & ~((uint32_t)0x000000F0)) | ((uint32_t)vlanidram << 4));
}
/**
* @brief Returns the current value of the sppRAM field in the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read and the sppRAM field's value will be returned.
*
* @return The current value of the sppRAM field in the ENCR_CNTRL register.
*/
__INLINE uint8_t nxmac_spp_ram_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x0000000C)) >> 2);
}
/**
* @brief Sets the sppRAM field of the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] sppram - The value to set the field to.
*/
__INLINE void nxmac_spp_ram_setf(uint8_t sppram)
{
ASSERT_ERR((((uint32_t)sppram << 2) & ~((uint32_t)0x0000000C)) == 0);
REG_PL_WR(NXMAC_ENCR_CNTRL_ADDR, (REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR) & ~((uint32_t)0x0000000C)) | ((uint32_t)sppram << 2));
}
/**
* @brief Returns the current value of the useDefKeyRAM field in the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read and the useDefKeyRAM field's value will be returned.
*
* @return The current value of the useDefKeyRAM field in the ENCR_CNTRL register.
*/
__INLINE uint8_t nxmac_use_def_key_ram_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000002)) >> 1);
}
/**
* @brief Sets the useDefKeyRAM field of the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] usedefkeyram - The value to set the field to.
*/
__INLINE void nxmac_use_def_key_ram_setf(uint8_t usedefkeyram)
{
ASSERT_ERR((((uint32_t)usedefkeyram << 1) & ~((uint32_t)0x00000002)) == 0);
REG_PL_WR(NXMAC_ENCR_CNTRL_ADDR, (REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR) & ~((uint32_t)0x00000002)) | ((uint32_t)usedefkeyram << 1));
}
/**
* @brief Returns the current value of the cLenRAM field in the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read and the cLenRAM field's value will be returned.
*
* @return The current value of the cLenRAM field in the ENCR_CNTRL register.
*/
__INLINE uint8_t nxmac_c_len_ram_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR);
return ((localVal & ((uint32_t)0x00000001)) >> 0);
}
/**
* @brief Sets the cLenRAM field of the ENCR_CNTRL register.
*
* The ENCR_CNTRL register will be read, modified to contain the new field value, and written.
*
* @param[in] clenram - The value to set the field to.
*/
__INLINE void nxmac_c_len_ram_setf(uint8_t clenram)
{
ASSERT_ERR((((uint32_t)clenram << 0) & ~((uint32_t)0x00000001)) == 0);
REG_PL_WR(NXMAC_ENCR_CNTRL_ADDR, (REG_PL_RD(NXMAC_ENCR_CNTRL_ADDR) & ~((uint32_t)0x00000001)) | ((uint32_t)clenram << 0));
}
/// @}
#if RW_WAPI_EN
/**
* @name ENCR_WPI_INT_KEY_0 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 encrIntKeyRAMWord0 0x0
* </pre>
*
* @{
*/
/// Address of the ENCR_WPI_INT_KEY_0 register
#define NXMAC_ENCR_WPI_INT_KEY_0_ADDR 0xC00000C8
/// Offset of the ENCR_WPI_INT_KEY_0 register from the base address
#define NXMAC_ENCR_WPI_INT_KEY_0_OFFSET 0x000000C8
/// Index of the ENCR_WPI_INT_KEY_0 register
#define NXMAC_ENCR_WPI_INT_KEY_0_INDEX 0x00000032
/// Reset value of the ENCR_WPI_INT_KEY_0 register
#define NXMAC_ENCR_WPI_INT_KEY_0_RESET 0x00000000
/**
* @brief Returns the current value of the ENCR_WPI_INT_KEY_0 register.
* The ENCR_WPI_INT_KEY_0 register will be read and its value returned.
* @return The current value of the ENCR_WPI_INT_KEY_0 register.
*/
__INLINE uint32_t nxmac_encr_wpi_int_key_0_get(void)
{
return REG_PL_RD(NXMAC_ENCR_WPI_INT_KEY_0_ADDR);
}
/**
* @brief Sets the ENCR_WPI_INT_KEY_0 register to a value.
* The ENCR_WPI_INT_KEY_0 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_encr_wpi_int_key_0_set(uint32_t value)
{
REG_PL_WR(NXMAC_ENCR_WPI_INT_KEY_0_ADDR, value);
}
// field definitions
/// ENCR_INT_KEY_RAM_WORD_0 field mask
#define NXMAC_ENCR_INT_KEY_RAM_WORD_0_MASK ((uint32_t)0xFFFFFFFF)
/// ENCR_INT_KEY_RAM_WORD_0 field LSB position
#define NXMAC_ENCR_INT_KEY_RAM_WORD_0_LSB 0
/// ENCR_INT_KEY_RAM_WORD_0 field width
#define NXMAC_ENCR_INT_KEY_RAM_WORD_0_WIDTH ((uint32_t)0x00000020)
/// ENCR_INT_KEY_RAM_WORD_0 field reset value
#define NXMAC_ENCR_INT_KEY_RAM_WORD_0_RST 0x0
/**
* @brief Returns the current value of the encrIntKeyRAMWord0 field in the ENCR_WPI_INT_KEY_0 register.
*
* The ENCR_WPI_INT_KEY_0 register will be read and the encrIntKeyRAMWord0 field's value will be returned.
*
* @return The current value of the encrIntKeyRAMWord0 field in the ENCR_WPI_INT_KEY_0 register.
*/
__INLINE uint32_t nxmac_encr_int_key_ram_word_0_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_WPI_INT_KEY_0_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the encrIntKeyRAMWord0 field of the ENCR_WPI_INT_KEY_0 register.
*
* The ENCR_WPI_INT_KEY_0 register will be read, modified to contain the new field value, and written.
*
* @param[in] encrintkeyramword0 - The value to set the field to.
*/
__INLINE void nxmac_encr_int_key_ram_word_0_setf(uint32_t encrintkeyramword0)
{
ASSERT_ERR((((uint32_t)encrintkeyramword0 << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_ENCR_WPI_INT_KEY_0_ADDR, (uint32_t)encrintkeyramword0 << 0);
}
#endif // RW_WAPI_EN
/// @}
#if RW_WAPI_EN
/**
* @name ENCR_WPI_INT_KEY_1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 encrIntKeyRAMWord1 0x0
* </pre>
*
* @{
*/
/// Address of the ENCR_WPI_INT_KEY_1 register
#define NXMAC_ENCR_WPI_INT_KEY_1_ADDR 0xC00000CC
/// Offset of the ENCR_WPI_INT_KEY_1 register from the base address
#define NXMAC_ENCR_WPI_INT_KEY_1_OFFSET 0x000000CC
/// Index of the ENCR_WPI_INT_KEY_1 register
#define NXMAC_ENCR_WPI_INT_KEY_1_INDEX 0x00000033
/// Reset value of the ENCR_WPI_INT_KEY_1 register
#define NXMAC_ENCR_WPI_INT_KEY_1_RESET 0x00000000
/**
* @brief Returns the current value of the ENCR_WPI_INT_KEY_1 register.
* The ENCR_WPI_INT_KEY_1 register will be read and its value returned.
* @return The current value of the ENCR_WPI_INT_KEY_1 register.
*/
__INLINE uint32_t nxmac_encr_wpi_int_key_1_get(void)
{
return REG_PL_RD(NXMAC_ENCR_WPI_INT_KEY_1_ADDR);
}
/**
* @brief Sets the ENCR_WPI_INT_KEY_1 register to a value.
* The ENCR_WPI_INT_KEY_1 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_encr_wpi_int_key_1_set(uint32_t value)
{
REG_PL_WR(NXMAC_ENCR_WPI_INT_KEY_1_ADDR, value);
}
// field definitions
/// ENCR_INT_KEY_RAM_WORD_1 field mask
#define NXMAC_ENCR_INT_KEY_RAM_WORD_1_MASK ((uint32_t)0xFFFFFFFF)
/// ENCR_INT_KEY_RAM_WORD_1 field LSB position
#define NXMAC_ENCR_INT_KEY_RAM_WORD_1_LSB 0
/// ENCR_INT_KEY_RAM_WORD_1 field width
#define NXMAC_ENCR_INT_KEY_RAM_WORD_1_WIDTH ((uint32_t)0x00000020)
/// ENCR_INT_KEY_RAM_WORD_1 field reset value
#define NXMAC_ENCR_INT_KEY_RAM_WORD_1_RST 0x0
/**
* @brief Returns the current value of the encrIntKeyRAMWord1 field in the ENCR_WPI_INT_KEY_1 register.
*
* The ENCR_WPI_INT_KEY_1 register will be read and the encrIntKeyRAMWord1 field's value will be returned.
*
* @return The current value of the encrIntKeyRAMWord1 field in the ENCR_WPI_INT_KEY_1 register.
*/
__INLINE uint32_t nxmac_encr_int_key_ram_word_1_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_WPI_INT_KEY_1_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the encrIntKeyRAMWord1 field of the ENCR_WPI_INT_KEY_1 register.
*
* The ENCR_WPI_INT_KEY_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] encrintkeyramword1 - The value to set the field to.
*/
__INLINE void nxmac_encr_int_key_ram_word_1_setf(uint32_t encrintkeyramword1)
{
ASSERT_ERR((((uint32_t)encrintkeyramword1 << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_ENCR_WPI_INT_KEY_1_ADDR, (uint32_t)encrintkeyramword1 << 0);
}
#endif // RW_WAPI_EN
/// @}
#if RW_WAPI_EN
/**
* @name ENCR_WPI_INT_KEY_2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 encrIntKeyRAMWord2 0x0
* </pre>
*
* @{
*/
/// Address of the ENCR_WPI_INT_KEY_2 register
#define NXMAC_ENCR_WPI_INT_KEY_2_ADDR 0xC00000D0
/// Offset of the ENCR_WPI_INT_KEY_2 register from the base address
#define NXMAC_ENCR_WPI_INT_KEY_2_OFFSET 0x000000D0
/// Index of the ENCR_WPI_INT_KEY_2 register
#define NXMAC_ENCR_WPI_INT_KEY_2_INDEX 0x00000034
/// Reset value of the ENCR_WPI_INT_KEY_2 register
#define NXMAC_ENCR_WPI_INT_KEY_2_RESET 0x00000000
/**
* @brief Returns the current value of the ENCR_WPI_INT_KEY_2 register.
* The ENCR_WPI_INT_KEY_2 register will be read and its value returned.
* @return The current value of the ENCR_WPI_INT_KEY_2 register.
*/
__INLINE uint32_t nxmac_encr_wpi_int_key_2_get(void)
{
return REG_PL_RD(NXMAC_ENCR_WPI_INT_KEY_2_ADDR);
}
/**
* @brief Sets the ENCR_WPI_INT_KEY_2 register to a value.
* The ENCR_WPI_INT_KEY_2 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_encr_wpi_int_key_2_set(uint32_t value)
{
REG_PL_WR(NXMAC_ENCR_WPI_INT_KEY_2_ADDR, value);
}
// field definitions
/// ENCR_INT_KEY_RAM_WORD_2 field mask
#define NXMAC_ENCR_INT_KEY_RAM_WORD_2_MASK ((uint32_t)0xFFFFFFFF)
/// ENCR_INT_KEY_RAM_WORD_2 field LSB position
#define NXMAC_ENCR_INT_KEY_RAM_WORD_2_LSB 0
/// ENCR_INT_KEY_RAM_WORD_2 field width
#define NXMAC_ENCR_INT_KEY_RAM_WORD_2_WIDTH ((uint32_t)0x00000020)
/// ENCR_INT_KEY_RAM_WORD_2 field reset value
#define NXMAC_ENCR_INT_KEY_RAM_WORD_2_RST 0x0
/**
* @brief Returns the current value of the encrIntKeyRAMWord2 field in the ENCR_WPI_INT_KEY_2 register.
*
* The ENCR_WPI_INT_KEY_2 register will be read and the encrIntKeyRAMWord2 field's value will be returned.
*
* @return The current value of the encrIntKeyRAMWord2 field in the ENCR_WPI_INT_KEY_2 register.
*/
__INLINE uint32_t nxmac_encr_int_key_ram_word_2_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_WPI_INT_KEY_2_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the encrIntKeyRAMWord2 field of the ENCR_WPI_INT_KEY_2 register.
*
* The ENCR_WPI_INT_KEY_2 register will be read, modified to contain the new field value, and written.
*
* @param[in] encrintkeyramword2 - The value to set the field to.
*/
__INLINE void nxmac_encr_int_key_ram_word_2_setf(uint32_t encrintkeyramword2)
{
ASSERT_ERR((((uint32_t)encrintkeyramword2 << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_ENCR_WPI_INT_KEY_2_ADDR, (uint32_t)encrintkeyramword2 << 0);
}
#endif // RW_WAPI_EN
/// @}
#if RW_WAPI_EN
/**
* @name ENCR_WPI_INT_KEY_3 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 encrIntKeyRAMWord3 0x0
* </pre>
*
* @{
*/
/// Address of the ENCR_WPI_INT_KEY_3 register
#define NXMAC_ENCR_WPI_INT_KEY_3_ADDR 0xC00000D4
/// Offset of the ENCR_WPI_INT_KEY_3 register from the base address
#define NXMAC_ENCR_WPI_INT_KEY_3_OFFSET 0x000000D4
/// Index of the ENCR_WPI_INT_KEY_3 register
#define NXMAC_ENCR_WPI_INT_KEY_3_INDEX 0x00000035
/// Reset value of the ENCR_WPI_INT_KEY_3 register
#define NXMAC_ENCR_WPI_INT_KEY_3_RESET 0x00000000
/**
* @brief Returns the current value of the ENCR_WPI_INT_KEY_3 register.
* The ENCR_WPI_INT_KEY_3 register will be read and its value returned.
* @return The current value of the ENCR_WPI_INT_KEY_3 register.
*/
__INLINE uint32_t nxmac_encr_wpi_int_key_3_get(void)
{
return REG_PL_RD(NXMAC_ENCR_WPI_INT_KEY_3_ADDR);
}
/**
* @brief Sets the ENCR_WPI_INT_KEY_3 register to a value.
* The ENCR_WPI_INT_KEY_3 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_encr_wpi_int_key_3_set(uint32_t value)
{
REG_PL_WR(NXMAC_ENCR_WPI_INT_KEY_3_ADDR, value);
}
// field definitions
/// ENCR_INT_KEY_RAM_WORD_3 field mask
#define NXMAC_ENCR_INT_KEY_RAM_WORD_3_MASK ((uint32_t)0xFFFFFFFF)
/// ENCR_INT_KEY_RAM_WORD_3 field LSB position
#define NXMAC_ENCR_INT_KEY_RAM_WORD_3_LSB 0
/// ENCR_INT_KEY_RAM_WORD_3 field width
#define NXMAC_ENCR_INT_KEY_RAM_WORD_3_WIDTH ((uint32_t)0x00000020)
/// ENCR_INT_KEY_RAM_WORD_3 field reset value
#define NXMAC_ENCR_INT_KEY_RAM_WORD_3_RST 0x0
/**
* @brief Returns the current value of the encrIntKeyRAMWord3 field in the ENCR_WPI_INT_KEY_3 register.
*
* The ENCR_WPI_INT_KEY_3 register will be read and the encrIntKeyRAMWord3 field's value will be returned.
*
* @return The current value of the encrIntKeyRAMWord3 field in the ENCR_WPI_INT_KEY_3 register.
*/
__INLINE uint32_t nxmac_encr_int_key_ram_word_3_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_WPI_INT_KEY_3_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the encrIntKeyRAMWord3 field of the ENCR_WPI_INT_KEY_3 register.
*
* The ENCR_WPI_INT_KEY_3 register will be read, modified to contain the new field value, and written.
*
* @param[in] encrintkeyramword3 - The value to set the field to.
*/
__INLINE void nxmac_encr_int_key_ram_word_3_setf(uint32_t encrintkeyramword3)
{
ASSERT_ERR((((uint32_t)encrintkeyramword3 << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_ENCR_WPI_INT_KEY_3_ADDR, (uint32_t)encrintkeyramword3 << 0);
}
#endif // RW_WAPI_EN
/// @}
/**
* @name ENCR_RAM_CONFIG register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:24 staKeyMaxIndex 0x0
* 19:16 nVAP 0x0
* 15:08 staKeyEndIndex 0x0
* 07:00 staKeyStartIndex 0x0
* </pre>
*
* @{
*/
/// Address of the ENCR_RAM_CONFIG register
#define NXMAC_ENCR_RAM_CONFIG_ADDR 0xC00000D8
/// Offset of the ENCR_RAM_CONFIG register from the base address
#define NXMAC_ENCR_RAM_CONFIG_OFFSET 0x000000D8
/// Index of the ENCR_RAM_CONFIG register
#define NXMAC_ENCR_RAM_CONFIG_INDEX 0x00000036
/// Reset value of the ENCR_RAM_CONFIG register
#define NXMAC_ENCR_RAM_CONFIG_RESET 0x00000000
/**
* @brief Returns the current value of the ENCR_RAM_CONFIG register.
* The ENCR_RAM_CONFIG register will be read and its value returned.
* @return The current value of the ENCR_RAM_CONFIG register.
*/
__INLINE uint32_t nxmac_encr_ram_config_get(void)
{
return REG_PL_RD(NXMAC_ENCR_RAM_CONFIG_ADDR);
}
/**
* @brief Sets the ENCR_RAM_CONFIG register to a value.
* The ENCR_RAM_CONFIG register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_encr_ram_config_set(uint32_t value)
{
REG_PL_WR(NXMAC_ENCR_RAM_CONFIG_ADDR, value);
}
// field definitions
/// STA_KEY_MAX_INDEX field mask
#define NXMAC_STA_KEY_MAX_INDEX_MASK ((uint32_t)0xFF000000)
/// STA_KEY_MAX_INDEX field LSB position
#define NXMAC_STA_KEY_MAX_INDEX_LSB 24
/// STA_KEY_MAX_INDEX field width
#define NXMAC_STA_KEY_MAX_INDEX_WIDTH ((uint32_t)0x00000008)
/// N_VAP field mask
#define NXMAC_N_VAP_MASK ((uint32_t)0x000F0000)
/// N_VAP field LSB position
#define NXMAC_N_VAP_LSB 16
/// N_VAP field width
#define NXMAC_N_VAP_WIDTH ((uint32_t)0x00000004)
/// STA_KEY_END_INDEX field mask
#define NXMAC_STA_KEY_END_INDEX_MASK ((uint32_t)0x0000FF00)
/// STA_KEY_END_INDEX field LSB position
#define NXMAC_STA_KEY_END_INDEX_LSB 8
/// STA_KEY_END_INDEX field width
#define NXMAC_STA_KEY_END_INDEX_WIDTH ((uint32_t)0x00000008)
/// STA_KEY_START_INDEX field mask
#define NXMAC_STA_KEY_START_INDEX_MASK ((uint32_t)0x000000FF)
/// STA_KEY_START_INDEX field LSB position
#define NXMAC_STA_KEY_START_INDEX_LSB 0
/// STA_KEY_START_INDEX field width
#define NXMAC_STA_KEY_START_INDEX_WIDTH ((uint32_t)0x00000008)
/// STA_KEY_MAX_INDEX field reset value
#define NXMAC_STA_KEY_MAX_INDEX_RST 0x0
/// N_VAP field reset value
#define NXMAC_N_VAP_RST 0x0
/// STA_KEY_END_INDEX field reset value
#define NXMAC_STA_KEY_END_INDEX_RST 0x0
/// STA_KEY_START_INDEX field reset value
#define NXMAC_STA_KEY_START_INDEX_RST 0x0
/**
* @brief Constructs a value for the ENCR_RAM_CONFIG register given values for its fields
* and writes the value to the register.
*
* @param[in] nvap - The value to use for the nVAP field.
* @param[in] stakeyendindex - The value to use for the staKeyEndIndex field.
* @param[in] stakeystartindex - The value to use for the staKeyStartIndex field.
*/
__INLINE void nxmac_encr_ram_config_pack(uint8_t nvap, uint8_t stakeyendindex, uint8_t stakeystartindex)
{
ASSERT_ERR((((uint32_t)nvap << 16) & ~((uint32_t)0x000F0000)) == 0);
ASSERT_ERR((((uint32_t)stakeyendindex << 8) & ~((uint32_t)0x0000FF00)) == 0);
ASSERT_ERR((((uint32_t)stakeystartindex << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_ENCR_RAM_CONFIG_ADDR, ((uint32_t)nvap << 16) | ((uint32_t)stakeyendindex << 8) | ((uint32_t)stakeystartindex << 0));
}
/**
* @brief Unpacks ENCR_RAM_CONFIG's fields from current value of the ENCR_RAM_CONFIG register.
*
* Reads the ENCR_RAM_CONFIG register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] stakeymaxindex - Will be populated with the current value of this field from the register.
* @param[out] nvap - Will be populated with the current value of this field from the register.
* @param[out] stakeyendindex - Will be populated with the current value of this field from the register.
* @param[out] stakeystartindex - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_encr_ram_config_unpack(uint8_t *stakeymaxindex, uint8_t *nvap, uint8_t *stakeyendindex, uint8_t *stakeystartindex)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_RAM_CONFIG_ADDR);
*stakeymaxindex = (localVal & ((uint32_t)0xFF000000)) >> 24;
*nvap = (localVal & ((uint32_t)0x000F0000)) >> 16;
*stakeyendindex = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*stakeystartindex = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the staKeyMaxIndex field in the ENCR_RAM_CONFIG register.
*
* The ENCR_RAM_CONFIG register will be read and the staKeyMaxIndex field's value will be returned.
*
* @return The current value of the staKeyMaxIndex field in the ENCR_RAM_CONFIG register.
*/
__INLINE uint8_t nxmac_sta_key_max_index_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_RAM_CONFIG_ADDR);
return ((localVal & ((uint32_t)0xFF000000)) >> 24);
}
/**
* @brief Returns the current value of the nVAP field in the ENCR_RAM_CONFIG register.
*
* The ENCR_RAM_CONFIG register will be read and the nVAP field's value will be returned.
*
* @return The current value of the nVAP field in the ENCR_RAM_CONFIG register.
*/
__INLINE uint8_t nxmac_n_vap_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_RAM_CONFIG_ADDR);
return ((localVal & ((uint32_t)0x000F0000)) >> 16);
}
/**
* @brief Sets the nVAP field of the ENCR_RAM_CONFIG register.
*
* The ENCR_RAM_CONFIG register will be read, modified to contain the new field value, and written.
*
* @param[in] nvap - The value to set the field to.
*/
__INLINE void nxmac_n_vap_setf(uint8_t nvap)
{
ASSERT_ERR((((uint32_t)nvap << 16) & ~((uint32_t)0x000F0000)) == 0);
REG_PL_WR(NXMAC_ENCR_RAM_CONFIG_ADDR, (REG_PL_RD(NXMAC_ENCR_RAM_CONFIG_ADDR) & ~((uint32_t)0x000F0000)) | ((uint32_t)nvap << 16));
}
/**
* @brief Returns the current value of the staKeyEndIndex field in the ENCR_RAM_CONFIG register.
*
* The ENCR_RAM_CONFIG register will be read and the staKeyEndIndex field's value will be returned.
*
* @return The current value of the staKeyEndIndex field in the ENCR_RAM_CONFIG register.
*/
__INLINE uint8_t nxmac_sta_key_end_index_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_RAM_CONFIG_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Sets the staKeyEndIndex field of the ENCR_RAM_CONFIG register.
*
* The ENCR_RAM_CONFIG register will be read, modified to contain the new field value, and written.
*
* @param[in] stakeyendindex - The value to set the field to.
*/
__INLINE void nxmac_sta_key_end_index_setf(uint8_t stakeyendindex)
{
ASSERT_ERR((((uint32_t)stakeyendindex << 8) & ~((uint32_t)0x0000FF00)) == 0);
REG_PL_WR(NXMAC_ENCR_RAM_CONFIG_ADDR, (REG_PL_RD(NXMAC_ENCR_RAM_CONFIG_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)stakeyendindex << 8));
}
/**
* @brief Returns the current value of the staKeyStartIndex field in the ENCR_RAM_CONFIG register.
*
* The ENCR_RAM_CONFIG register will be read and the staKeyStartIndex field's value will be returned.
*
* @return The current value of the staKeyStartIndex field in the ENCR_RAM_CONFIG register.
*/
__INLINE uint8_t nxmac_sta_key_start_index_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_ENCR_RAM_CONFIG_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the staKeyStartIndex field of the ENCR_RAM_CONFIG register.
*
* The ENCR_RAM_CONFIG register will be read, modified to contain the new field value, and written.
*
* @param[in] stakeystartindex - The value to set the field to.
*/
__INLINE void nxmac_sta_key_start_index_setf(uint8_t stakeystartindex)
{
ASSERT_ERR((((uint32_t)stakeystartindex << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_ENCR_RAM_CONFIG_ADDR, (REG_PL_RD(NXMAC_ENCR_RAM_CONFIG_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)stakeystartindex << 0));
}
/// @}
/**
* @name RATES register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 11:00 bssBasicRateSet 0x150
* </pre>
*
* @{
*/
/// Address of the RATES register
#define NXMAC_RATES_ADDR 0xC00000DC
/// Offset of the RATES register from the base address
#define NXMAC_RATES_OFFSET 0x000000DC
/// Index of the RATES register
#define NXMAC_RATES_INDEX 0x00000037
/// Reset value of the RATES register
#define NXMAC_RATES_RESET 0x00000150
/**
* @brief Returns the current value of the RATES register.
* The RATES register will be read and its value returned.
* @return The current value of the RATES register.
*/
__INLINE uint32_t nxmac_rates_get(void)
{
return REG_PL_RD(NXMAC_RATES_ADDR);
}
/**
* @brief Sets the RATES register to a value.
* The RATES register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_rates_set(uint32_t value)
{
REG_PL_WR(NXMAC_RATES_ADDR, value);
}
// field definitions
/// BSS_BASIC_RATE_SET field mask
#define NXMAC_BSS_BASIC_RATE_SET_MASK ((uint32_t)0x00000FFF)
/// BSS_BASIC_RATE_SET field LSB position
#define NXMAC_BSS_BASIC_RATE_SET_LSB 0
/// BSS_BASIC_RATE_SET field width
#define NXMAC_BSS_BASIC_RATE_SET_WIDTH ((uint32_t)0x0000000C)
/// BSS_BASIC_RATE_SET field reset value
#define NXMAC_BSS_BASIC_RATE_SET_RST 0x150
/**
* @brief Returns the current value of the bssBasicRateSet field in the RATES register.
*
* The RATES register will be read and the bssBasicRateSet field's value will be returned.
*
* @return The current value of the bssBasicRateSet field in the RATES register.
*/
__INLINE uint16_t nxmac_bss_basic_rate_set_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RATES_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0x00000FFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the bssBasicRateSet field of the RATES register.
*
* The RATES register will be read, modified to contain the new field value, and written.
*
* @param[in] bssbasicrateset - The value to set the field to.
*/
__INLINE void nxmac_bss_basic_rate_set_setf(uint16_t bssbasicrateset)
{
ASSERT_ERR((((uint32_t)bssbasicrateset << 0) & ~((uint32_t)0x00000FFF)) == 0);
REG_PL_WR(NXMAC_RATES_ADDR, (uint32_t)bssbasicrateset << 0);
}
/// @}
/**
* @name OLBC register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:24 dsssCount 0x0
* 23:16 ofdmCount 0x0
* 15:00 olbcTimer 0x0
* </pre>
*
* @{
*/
/// Address of the OLBC register
#define NXMAC_OLBC_ADDR 0xC00000E0
/// Offset of the OLBC register from the base address
#define NXMAC_OLBC_OFFSET 0x000000E0
/// Index of the OLBC register
#define NXMAC_OLBC_INDEX 0x00000038
/// Reset value of the OLBC register
#define NXMAC_OLBC_RESET 0x00000000
/**
* @brief Returns the current value of the OLBC register.
* The OLBC register will be read and its value returned.
* @return The current value of the OLBC register.
*/
__INLINE uint32_t nxmac_olbc_get(void)
{
return REG_PL_RD(NXMAC_OLBC_ADDR);
}
/**
* @brief Sets the OLBC register to a value.
* The OLBC register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_olbc_set(uint32_t value)
{
REG_PL_WR(NXMAC_OLBC_ADDR, value);
}
// field definitions
/// DSSS_COUNT field mask
#define NXMAC_DSSS_COUNT_MASK ((uint32_t)0xFF000000)
/// DSSS_COUNT field LSB position
#define NXMAC_DSSS_COUNT_LSB 24
/// DSSS_COUNT field width
#define NXMAC_DSSS_COUNT_WIDTH ((uint32_t)0x00000008)
/// OFDM_COUNT field mask
#define NXMAC_OFDM_COUNT_MASK ((uint32_t)0x00FF0000)
/// OFDM_COUNT field LSB position
#define NXMAC_OFDM_COUNT_LSB 16
/// OFDM_COUNT field width
#define NXMAC_OFDM_COUNT_WIDTH ((uint32_t)0x00000008)
/// OLBC_TIMER field mask
#define NXMAC_OLBC_TIMER_MASK ((uint32_t)0x0000FFFF)
/// OLBC_TIMER field LSB position
#define NXMAC_OLBC_TIMER_LSB 0
/// OLBC_TIMER field width
#define NXMAC_OLBC_TIMER_WIDTH ((uint32_t)0x00000010)
/// DSSS_COUNT field reset value
#define NXMAC_DSSS_COUNT_RST 0x0
/// OFDM_COUNT field reset value
#define NXMAC_OFDM_COUNT_RST 0x0
/// OLBC_TIMER field reset value
#define NXMAC_OLBC_TIMER_RST 0x0
/**
* @brief Constructs a value for the OLBC register given values for its fields
* and writes the value to the register.
*
* @param[in] dssscount - The value to use for the dsssCount field.
* @param[in] ofdmcount - The value to use for the ofdmCount field.
* @param[in] olbctimer - The value to use for the olbcTimer field.
*/
__INLINE void nxmac_olbc_pack(uint8_t dssscount, uint8_t ofdmcount, uint16_t olbctimer)
{
ASSERT_ERR((((uint32_t)dssscount << 24) & ~((uint32_t)0xFF000000)) == 0);
ASSERT_ERR((((uint32_t)ofdmcount << 16) & ~((uint32_t)0x00FF0000)) == 0);
ASSERT_ERR((((uint32_t)olbctimer << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_OLBC_ADDR, ((uint32_t)dssscount << 24) | ((uint32_t)ofdmcount << 16) | ((uint32_t)olbctimer << 0));
}
/**
* @brief Unpacks OLBC's fields from current value of the OLBC register.
*
* Reads the OLBC register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] dssscount - Will be populated with the current value of this field from the register.
* @param[out] ofdmcount - Will be populated with the current value of this field from the register.
* @param[out] olbctimer - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_olbc_unpack(uint8_t *dssscount, uint8_t *ofdmcount, uint16_t *olbctimer)
{
uint32_t localVal = REG_PL_RD(NXMAC_OLBC_ADDR);
*dssscount = (localVal & ((uint32_t)0xFF000000)) >> 24;
*ofdmcount = (localVal & ((uint32_t)0x00FF0000)) >> 16;
*olbctimer = (localVal & ((uint32_t)0x0000FFFF)) >> 0;
}
/**
* @brief Returns the current value of the dsssCount field in the OLBC register.
*
* The OLBC register will be read and the dsssCount field's value will be returned.
*
* @return The current value of the dsssCount field in the OLBC register.
*/
__INLINE uint8_t nxmac_dsss_count_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_OLBC_ADDR);
return ((localVal & ((uint32_t)0xFF000000)) >> 24);
}
/**
* @brief Sets the dsssCount field of the OLBC register.
*
* The OLBC register will be read, modified to contain the new field value, and written.
*
* @param[in] dssscount - The value to set the field to.
*/
__INLINE void nxmac_dsss_count_setf(uint8_t dssscount)
{
ASSERT_ERR((((uint32_t)dssscount << 24) & ~((uint32_t)0xFF000000)) == 0);
REG_PL_WR(NXMAC_OLBC_ADDR, (REG_PL_RD(NXMAC_OLBC_ADDR) & ~((uint32_t)0xFF000000)) | ((uint32_t)dssscount << 24));
}
/**
* @brief Returns the current value of the ofdmCount field in the OLBC register.
*
* The OLBC register will be read and the ofdmCount field's value will be returned.
*
* @return The current value of the ofdmCount field in the OLBC register.
*/
__INLINE uint8_t nxmac_ofdm_count_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_OLBC_ADDR);
return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
}
/**
* @brief Sets the ofdmCount field of the OLBC register.
*
* The OLBC register will be read, modified to contain the new field value, and written.
*
* @param[in] ofdmcount - The value to set the field to.
*/
__INLINE void nxmac_ofdm_count_setf(uint8_t ofdmcount)
{
ASSERT_ERR((((uint32_t)ofdmcount << 16) & ~((uint32_t)0x00FF0000)) == 0);
REG_PL_WR(NXMAC_OLBC_ADDR, (REG_PL_RD(NXMAC_OLBC_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)ofdmcount << 16));
}
/**
* @brief Returns the current value of the olbcTimer field in the OLBC register.
*
* The OLBC register will be read and the olbcTimer field's value will be returned.
*
* @return The current value of the olbcTimer field in the OLBC register.
*/
__INLINE uint16_t nxmac_olbc_timer_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_OLBC_ADDR);
return ((localVal & ((uint32_t)0x0000FFFF)) >> 0);
}
/**
* @brief Sets the olbcTimer field of the OLBC register.
*
* The OLBC register will be read, modified to contain the new field value, and written.
*
* @param[in] olbctimer - The value to set the field to.
*/
__INLINE void nxmac_olbc_timer_setf(uint16_t olbctimer)
{
ASSERT_ERR((((uint32_t)olbctimer << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_OLBC_ADDR, (REG_PL_RD(NXMAC_OLBC_ADDR) & ~((uint32_t)0x0000FFFF)) | ((uint32_t)olbctimer << 0));
}
/// @}
/**
* @name TIMINGS_1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 27:18 txChainDelayInMACClk 0x0
* 17:08 txRFDelayInMACClk 0x0
* 07:00 macCoreClkFreq 0x0
* </pre>
*
* @{
*/
/// Address of the TIMINGS_1 register
#define NXMAC_TIMINGS_1_ADDR 0xC00000E4
/// Offset of the TIMINGS_1 register from the base address
#define NXMAC_TIMINGS_1_OFFSET 0x000000E4
/// Index of the TIMINGS_1 register
#define NXMAC_TIMINGS_1_INDEX 0x00000039
/// Reset value of the TIMINGS_1 register
#define NXMAC_TIMINGS_1_RESET 0x00000000
/**
* @brief Returns the current value of the TIMINGS_1 register.
* The TIMINGS_1 register will be read and its value returned.
* @return The current value of the TIMINGS_1 register.
*/
__INLINE uint32_t nxmac_timings_1_get(void)
{
return REG_PL_RD(NXMAC_TIMINGS_1_ADDR);
}
/**
* @brief Sets the TIMINGS_1 register to a value.
* The TIMINGS_1 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_timings_1_set(uint32_t value)
{
REG_PL_WR(NXMAC_TIMINGS_1_ADDR, value);
}
// field definitions
/// TX_CHAIN_DELAY_IN_MAC_CLK field mask
#define NXMAC_TX_CHAIN_DELAY_IN_MAC_CLK_MASK ((uint32_t)0x0FFC0000)
/// TX_CHAIN_DELAY_IN_MAC_CLK field LSB position
#define NXMAC_TX_CHAIN_DELAY_IN_MAC_CLK_LSB 18
/// TX_CHAIN_DELAY_IN_MAC_CLK field width
#define NXMAC_TX_CHAIN_DELAY_IN_MAC_CLK_WIDTH ((uint32_t)0x0000000A)
/// TX_RF_DELAY_IN_MAC_CLK field mask
#define NXMAC_TX_RF_DELAY_IN_MAC_CLK_MASK ((uint32_t)0x0003FF00)
/// TX_RF_DELAY_IN_MAC_CLK field LSB position
#define NXMAC_TX_RF_DELAY_IN_MAC_CLK_LSB 8
/// TX_RF_DELAY_IN_MAC_CLK field width
#define NXMAC_TX_RF_DELAY_IN_MAC_CLK_WIDTH ((uint32_t)0x0000000A)
/// MAC_CORE_CLK_FREQ field mask
#define NXMAC_MAC_CORE_CLK_FREQ_MASK ((uint32_t)0x000000FF)
/// MAC_CORE_CLK_FREQ field LSB position
#define NXMAC_MAC_CORE_CLK_FREQ_LSB 0
/// MAC_CORE_CLK_FREQ field width
#define NXMAC_MAC_CORE_CLK_FREQ_WIDTH ((uint32_t)0x00000008)
/// TX_CHAIN_DELAY_IN_MAC_CLK field reset value
#define NXMAC_TX_CHAIN_DELAY_IN_MAC_CLK_RST 0x0
/// TX_RF_DELAY_IN_MAC_CLK field reset value
#define NXMAC_TX_RF_DELAY_IN_MAC_CLK_RST 0x0
/// MAC_CORE_CLK_FREQ field reset value
#define NXMAC_MAC_CORE_CLK_FREQ_RST 0x0
/**
* @brief Constructs a value for the TIMINGS_1 register given values for its fields
* and writes the value to the register.
*
* @param[in] txchaindelayinmacclk - The value to use for the txChainDelayInMACClk field.
* @param[in] txrfdelayinmacclk - The value to use for the txRFDelayInMACClk field.
* @param[in] maccoreclkfreq - The value to use for the macCoreClkFreq field.
*/
__INLINE void nxmac_timings_1_pack(uint16_t txchaindelayinmacclk, uint16_t txrfdelayinmacclk, uint8_t maccoreclkfreq)
{
ASSERT_ERR((((uint32_t)txchaindelayinmacclk << 18) & ~((uint32_t)0x0FFC0000)) == 0);
ASSERT_ERR((((uint32_t)txrfdelayinmacclk << 8) & ~((uint32_t)0x0003FF00)) == 0);
ASSERT_ERR((((uint32_t)maccoreclkfreq << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_1_ADDR, ((uint32_t)txchaindelayinmacclk << 18) | ((uint32_t)txrfdelayinmacclk << 8) | ((uint32_t)maccoreclkfreq << 0));
}
/**
* @brief Unpacks TIMINGS_1's fields from current value of the TIMINGS_1 register.
*
* Reads the TIMINGS_1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] txchaindelayinmacclk - Will be populated with the current value of this field from the register.
* @param[out] txrfdelayinmacclk - Will be populated with the current value of this field from the register.
* @param[out] maccoreclkfreq - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_timings_1_unpack(uint16_t *txchaindelayinmacclk, uint16_t *txrfdelayinmacclk, uint8_t *maccoreclkfreq)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_1_ADDR);
*txchaindelayinmacclk = (localVal & ((uint32_t)0x0FFC0000)) >> 18;
*txrfdelayinmacclk = (localVal & ((uint32_t)0x0003FF00)) >> 8;
*maccoreclkfreq = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the txChainDelayInMACClk field in the TIMINGS_1 register.
*
* The TIMINGS_1 register will be read and the txChainDelayInMACClk field's value will be returned.
*
* @return The current value of the txChainDelayInMACClk field in the TIMINGS_1 register.
*/
__INLINE uint16_t nxmac_tx_chain_delay_in_mac_clk_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_1_ADDR);
return ((localVal & ((uint32_t)0x0FFC0000)) >> 18);
}
/**
* @brief Sets the txChainDelayInMACClk field of the TIMINGS_1 register.
*
* The TIMINGS_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] txchaindelayinmacclk - The value to set the field to.
*/
__INLINE void nxmac_tx_chain_delay_in_mac_clk_setf(uint16_t txchaindelayinmacclk)
{
ASSERT_ERR((((uint32_t)txchaindelayinmacclk << 18) & ~((uint32_t)0x0FFC0000)) == 0);
REG_PL_WR(NXMAC_TIMINGS_1_ADDR, (REG_PL_RD(NXMAC_TIMINGS_1_ADDR) & ~((uint32_t)0x0FFC0000)) | ((uint32_t)txchaindelayinmacclk << 18));
}
/**
* @brief Returns the current value of the txRFDelayInMACClk field in the TIMINGS_1 register.
*
* The TIMINGS_1 register will be read and the txRFDelayInMACClk field's value will be returned.
*
* @return The current value of the txRFDelayInMACClk field in the TIMINGS_1 register.
*/
__INLINE uint16_t nxmac_tx_rf_delay_in_mac_clk_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_1_ADDR);
return ((localVal & ((uint32_t)0x0003FF00)) >> 8);
}
/**
* @brief Sets the txRFDelayInMACClk field of the TIMINGS_1 register.
*
* The TIMINGS_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] txrfdelayinmacclk - The value to set the field to.
*/
__INLINE void nxmac_tx_rf_delay_in_mac_clk_setf(uint16_t txrfdelayinmacclk)
{
ASSERT_ERR((((uint32_t)txrfdelayinmacclk << 8) & ~((uint32_t)0x0003FF00)) == 0);
REG_PL_WR(NXMAC_TIMINGS_1_ADDR, (REG_PL_RD(NXMAC_TIMINGS_1_ADDR) & ~((uint32_t)0x0003FF00)) | ((uint32_t)txrfdelayinmacclk << 8));
}
/**
* @brief Returns the current value of the macCoreClkFreq field in the TIMINGS_1 register.
*
* The TIMINGS_1 register will be read and the macCoreClkFreq field's value will be returned.
*
* @return The current value of the macCoreClkFreq field in the TIMINGS_1 register.
*/
__INLINE uint8_t nxmac_mac_core_clk_freq_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_1_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the macCoreClkFreq field of the TIMINGS_1 register.
*
* The TIMINGS_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] maccoreclkfreq - The value to set the field to.
*/
__INLINE void nxmac_mac_core_clk_freq_setf(uint8_t maccoreclkfreq)
{
ASSERT_ERR((((uint32_t)maccoreclkfreq << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_1_ADDR, (REG_PL_RD(NXMAC_TIMINGS_1_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)maccoreclkfreq << 0));
}
/// @}
/**
* @name TIMINGS_2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23:08 slotTimeInMACClk 0x0
* 07:00 slotTime 0x0
* </pre>
*
* @{
*/
/// Address of the TIMINGS_2 register
#define NXMAC_TIMINGS_2_ADDR 0xC00000E8
/// Offset of the TIMINGS_2 register from the base address
#define NXMAC_TIMINGS_2_OFFSET 0x000000E8
/// Index of the TIMINGS_2 register
#define NXMAC_TIMINGS_2_INDEX 0x0000003A
/// Reset value of the TIMINGS_2 register
#define NXMAC_TIMINGS_2_RESET 0x00000000
/**
* @brief Returns the current value of the TIMINGS_2 register.
* The TIMINGS_2 register will be read and its value returned.
* @return The current value of the TIMINGS_2 register.
*/
__INLINE uint32_t nxmac_timings_2_get(void)
{
return REG_PL_RD(NXMAC_TIMINGS_2_ADDR);
}
/**
* @brief Sets the TIMINGS_2 register to a value.
* The TIMINGS_2 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_timings_2_set(uint32_t value)
{
REG_PL_WR(NXMAC_TIMINGS_2_ADDR, value);
}
// field definitions
/// SLOT_TIME_IN_MAC_CLK field mask
#define NXMAC_SLOT_TIME_IN_MAC_CLK_MASK ((uint32_t)0x00FFFF00)
/// SLOT_TIME_IN_MAC_CLK field LSB position
#define NXMAC_SLOT_TIME_IN_MAC_CLK_LSB 8
/// SLOT_TIME_IN_MAC_CLK field width
#define NXMAC_SLOT_TIME_IN_MAC_CLK_WIDTH ((uint32_t)0x00000010)
/// SLOT_TIME field mask
#define NXMAC_SLOT_TIME_MASK ((uint32_t)0x000000FF)
/// SLOT_TIME field LSB position
#define NXMAC_SLOT_TIME_LSB 0
/// SLOT_TIME field width
#define NXMAC_SLOT_TIME_WIDTH ((uint32_t)0x00000008)
/// SLOT_TIME_IN_MAC_CLK field reset value
#define NXMAC_SLOT_TIME_IN_MAC_CLK_RST 0x0
/// SLOT_TIME field reset value
#define NXMAC_SLOT_TIME_RST 0x0
/**
* @brief Constructs a value for the TIMINGS_2 register given values for its fields
* and writes the value to the register.
*
* @param[in] slottimeinmacclk - The value to use for the slotTimeInMACClk field.
* @param[in] slottime - The value to use for the slotTime field.
*/
__INLINE void nxmac_timings_2_pack(uint16_t slottimeinmacclk, uint8_t slottime)
{
ASSERT_ERR((((uint32_t)slottimeinmacclk << 8) & ~((uint32_t)0x00FFFF00)) == 0);
ASSERT_ERR((((uint32_t)slottime << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_2_ADDR, ((uint32_t)slottimeinmacclk << 8) | ((uint32_t)slottime << 0));
}
/**
* @brief Unpacks TIMINGS_2's fields from current value of the TIMINGS_2 register.
*
* Reads the TIMINGS_2 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] slottimeinmacclk - Will be populated with the current value of this field from the register.
* @param[out] slottime - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_timings_2_unpack(uint16_t *slottimeinmacclk, uint8_t *slottime)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_2_ADDR);
*slottimeinmacclk = (localVal & ((uint32_t)0x00FFFF00)) >> 8;
*slottime = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the slotTimeInMACClk field in the TIMINGS_2 register.
*
* The TIMINGS_2 register will be read and the slotTimeInMACClk field's value will be returned.
*
* @return The current value of the slotTimeInMACClk field in the TIMINGS_2 register.
*/
__INLINE uint16_t nxmac_slot_time_in_mac_clk_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_2_ADDR);
return ((localVal & ((uint32_t)0x00FFFF00)) >> 8);
}
/**
* @brief Sets the slotTimeInMACClk field of the TIMINGS_2 register.
*
* The TIMINGS_2 register will be read, modified to contain the new field value, and written.
*
* @param[in] slottimeinmacclk - The value to set the field to.
*/
__INLINE void nxmac_slot_time_in_mac_clk_setf(uint16_t slottimeinmacclk)
{
ASSERT_ERR((((uint32_t)slottimeinmacclk << 8) & ~((uint32_t)0x00FFFF00)) == 0);
REG_PL_WR(NXMAC_TIMINGS_2_ADDR, (REG_PL_RD(NXMAC_TIMINGS_2_ADDR) & ~((uint32_t)0x00FFFF00)) | ((uint32_t)slottimeinmacclk << 8));
}
/**
* @brief Returns the current value of the slotTime field in the TIMINGS_2 register.
*
* The TIMINGS_2 register will be read and the slotTime field's value will be returned.
*
* @return The current value of the slotTime field in the TIMINGS_2 register.
*/
__INLINE uint8_t nxmac_slot_time_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_2_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the slotTime field of the TIMINGS_2 register.
*
* The TIMINGS_2 register will be read, modified to contain the new field value, and written.
*
* @param[in] slottime - The value to set the field to.
*/
__INLINE void nxmac_slot_time_setf(uint8_t slottime)
{
ASSERT_ERR((((uint32_t)slottime << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_2_ADDR, (REG_PL_RD(NXMAC_TIMINGS_2_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)slottime << 0));
}
/// @}
/**
* @name TIMINGS_3 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:20 rxRFDelayInMACClk 0x0
* 19:10 txDelayRFOnInMACClk 0x0
* 09:00 macProcDelayInMACClk 0x0
* </pre>
*
* @{
*/
/// Address of the TIMINGS_3 register
#define NXMAC_TIMINGS_3_ADDR 0xC00000EC
/// Offset of the TIMINGS_3 register from the base address
#define NXMAC_TIMINGS_3_OFFSET 0x000000EC
/// Index of the TIMINGS_3 register
#define NXMAC_TIMINGS_3_INDEX 0x0000003B
/// Reset value of the TIMINGS_3 register
#define NXMAC_TIMINGS_3_RESET 0x00000000
/**
* @brief Returns the current value of the TIMINGS_3 register.
* The TIMINGS_3 register will be read and its value returned.
* @return The current value of the TIMINGS_3 register.
*/
__INLINE uint32_t nxmac_timings_3_get(void)
{
return REG_PL_RD(NXMAC_TIMINGS_3_ADDR);
}
/**
* @brief Sets the TIMINGS_3 register to a value.
* The TIMINGS_3 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_timings_3_set(uint32_t value)
{
REG_PL_WR(NXMAC_TIMINGS_3_ADDR, value);
}
// field definitions
/// RX_RF_DELAY_IN_MAC_CLK field mask
#define NXMAC_RX_RF_DELAY_IN_MAC_CLK_MASK ((uint32_t)0x3FF00000)
/// RX_RF_DELAY_IN_MAC_CLK field LSB position
#define NXMAC_RX_RF_DELAY_IN_MAC_CLK_LSB 20
/// RX_RF_DELAY_IN_MAC_CLK field width
#define NXMAC_RX_RF_DELAY_IN_MAC_CLK_WIDTH ((uint32_t)0x0000000A)
/// TX_DELAY_RF_ON_IN_MAC_CLK field mask
#define NXMAC_TX_DELAY_RF_ON_IN_MAC_CLK_MASK ((uint32_t)0x000FFC00)
/// TX_DELAY_RF_ON_IN_MAC_CLK field LSB position
#define NXMAC_TX_DELAY_RF_ON_IN_MAC_CLK_LSB 10
/// TX_DELAY_RF_ON_IN_MAC_CLK field width
#define NXMAC_TX_DELAY_RF_ON_IN_MAC_CLK_WIDTH ((uint32_t)0x0000000A)
/// MAC_PROC_DELAY_IN_MAC_CLK field mask
#define NXMAC_MAC_PROC_DELAY_IN_MAC_CLK_MASK ((uint32_t)0x000003FF)
/// MAC_PROC_DELAY_IN_MAC_CLK field LSB position
#define NXMAC_MAC_PROC_DELAY_IN_MAC_CLK_LSB 0
/// MAC_PROC_DELAY_IN_MAC_CLK field width
#define NXMAC_MAC_PROC_DELAY_IN_MAC_CLK_WIDTH ((uint32_t)0x0000000A)
/// RX_RF_DELAY_IN_MAC_CLK field reset value
#define NXMAC_RX_RF_DELAY_IN_MAC_CLK_RST 0x0
/// TX_DELAY_RF_ON_IN_MAC_CLK field reset value
#define NXMAC_TX_DELAY_RF_ON_IN_MAC_CLK_RST 0x0
/// MAC_PROC_DELAY_IN_MAC_CLK field reset value
#define NXMAC_MAC_PROC_DELAY_IN_MAC_CLK_RST 0x0
/**
* @brief Constructs a value for the TIMINGS_3 register given values for its fields
* and writes the value to the register.
*
* @param[in] rxrfdelayinmacclk - The value to use for the rxRFDelayInMACClk field.
* @param[in] txdelayrfoninmacclk - The value to use for the txDelayRFOnInMACClk field.
* @param[in] macprocdelayinmacclk - The value to use for the macProcDelayInMACClk field.
*/
__INLINE void nxmac_timings_3_pack(uint16_t rxrfdelayinmacclk, uint16_t txdelayrfoninmacclk, uint16_t macprocdelayinmacclk)
{
ASSERT_ERR((((uint32_t)rxrfdelayinmacclk << 20) & ~((uint32_t)0x3FF00000)) == 0);
ASSERT_ERR((((uint32_t)txdelayrfoninmacclk << 10) & ~((uint32_t)0x000FFC00)) == 0);
ASSERT_ERR((((uint32_t)macprocdelayinmacclk << 0) & ~((uint32_t)0x000003FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_3_ADDR, ((uint32_t)rxrfdelayinmacclk << 20) | ((uint32_t)txdelayrfoninmacclk << 10) | ((uint32_t)macprocdelayinmacclk << 0));
}
/**
* @brief Unpacks TIMINGS_3's fields from current value of the TIMINGS_3 register.
*
* Reads the TIMINGS_3 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] rxrfdelayinmacclk - Will be populated with the current value of this field from the register.
* @param[out] txdelayrfoninmacclk - Will be populated with the current value of this field from the register.
* @param[out] macprocdelayinmacclk - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_timings_3_unpack(uint16_t *rxrfdelayinmacclk, uint16_t *txdelayrfoninmacclk, uint16_t *macprocdelayinmacclk)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_3_ADDR);
*rxrfdelayinmacclk = (localVal & ((uint32_t)0x3FF00000)) >> 20;
*txdelayrfoninmacclk = (localVal & ((uint32_t)0x000FFC00)) >> 10;
*macprocdelayinmacclk = (localVal & ((uint32_t)0x000003FF)) >> 0;
}
/**
* @brief Returns the current value of the rxRFDelayInMACClk field in the TIMINGS_3 register.
*
* The TIMINGS_3 register will be read and the rxRFDelayInMACClk field's value will be returned.
*
* @return The current value of the rxRFDelayInMACClk field in the TIMINGS_3 register.
*/
__INLINE uint16_t nxmac_rx_rf_delay_in_mac_clk_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_3_ADDR);
return ((localVal & ((uint32_t)0x3FF00000)) >> 20);
}
/**
* @brief Sets the rxRFDelayInMACClk field of the TIMINGS_3 register.
*
* The TIMINGS_3 register will be read, modified to contain the new field value, and written.
*
* @param[in] rxrfdelayinmacclk - The value to set the field to.
*/
__INLINE void nxmac_rx_rf_delay_in_mac_clk_setf(uint16_t rxrfdelayinmacclk)
{
ASSERT_ERR((((uint32_t)rxrfdelayinmacclk << 20) & ~((uint32_t)0x3FF00000)) == 0);
REG_PL_WR(NXMAC_TIMINGS_3_ADDR, (REG_PL_RD(NXMAC_TIMINGS_3_ADDR) & ~((uint32_t)0x3FF00000)) | ((uint32_t)rxrfdelayinmacclk << 20));
}
/**
* @brief Returns the current value of the txDelayRFOnInMACClk field in the TIMINGS_3 register.
*
* The TIMINGS_3 register will be read and the txDelayRFOnInMACClk field's value will be returned.
*
* @return The current value of the txDelayRFOnInMACClk field in the TIMINGS_3 register.
*/
__INLINE uint16_t nxmac_tx_delay_rf_on_in_mac_clk_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_3_ADDR);
return ((localVal & ((uint32_t)0x000FFC00)) >> 10);
}
/**
* @brief Sets the txDelayRFOnInMACClk field of the TIMINGS_3 register.
*
* The TIMINGS_3 register will be read, modified to contain the new field value, and written.
*
* @param[in] txdelayrfoninmacclk - The value to set the field to.
*/
__INLINE void nxmac_tx_delay_rf_on_in_mac_clk_setf(uint16_t txdelayrfoninmacclk)
{
ASSERT_ERR((((uint32_t)txdelayrfoninmacclk << 10) & ~((uint32_t)0x000FFC00)) == 0);
REG_PL_WR(NXMAC_TIMINGS_3_ADDR, (REG_PL_RD(NXMAC_TIMINGS_3_ADDR) & ~((uint32_t)0x000FFC00)) | ((uint32_t)txdelayrfoninmacclk << 10));
}
/**
* @brief Returns the current value of the macProcDelayInMACClk field in the TIMINGS_3 register.
*
* The TIMINGS_3 register will be read and the macProcDelayInMACClk field's value will be returned.
*
* @return The current value of the macProcDelayInMACClk field in the TIMINGS_3 register.
*/
__INLINE uint16_t nxmac_mac_proc_delay_in_mac_clk_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_3_ADDR);
return ((localVal & ((uint32_t)0x000003FF)) >> 0);
}
/**
* @brief Sets the macProcDelayInMACClk field of the TIMINGS_3 register.
*
* The TIMINGS_3 register will be read, modified to contain the new field value, and written.
*
* @param[in] macprocdelayinmacclk - The value to set the field to.
*/
__INLINE void nxmac_mac_proc_delay_in_mac_clk_setf(uint16_t macprocdelayinmacclk)
{
ASSERT_ERR((((uint32_t)macprocdelayinmacclk << 0) & ~((uint32_t)0x000003FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_3_ADDR, (REG_PL_RD(NXMAC_TIMINGS_3_ADDR) & ~((uint32_t)0x000003FF)) | ((uint32_t)macprocdelayinmacclk << 0));
}
/// @}
/**
* @name TIMINGS_4 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:22 radioWakeUpTime 0x0
* 21:12 radioChirpTime 0x0
* 01:00 wt2CryptClkRatio 0x0
* </pre>
*
* @{
*/
/// Address of the TIMINGS_4 register
#define NXMAC_TIMINGS_4_ADDR 0xC00000F0
/// Offset of the TIMINGS_4 register from the base address
#define NXMAC_TIMINGS_4_OFFSET 0x000000F0
/// Index of the TIMINGS_4 register
#define NXMAC_TIMINGS_4_INDEX 0x0000003C
/// Reset value of the TIMINGS_4 register
#define NXMAC_TIMINGS_4_RESET 0x00000000
/**
* @brief Returns the current value of the TIMINGS_4 register.
* The TIMINGS_4 register will be read and its value returned.
* @return The current value of the TIMINGS_4 register.
*/
__INLINE uint32_t nxmac_timings_4_get(void)
{
return REG_PL_RD(NXMAC_TIMINGS_4_ADDR);
}
/**
* @brief Sets the TIMINGS_4 register to a value.
* The TIMINGS_4 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_timings_4_set(uint32_t value)
{
REG_PL_WR(NXMAC_TIMINGS_4_ADDR, value);
}
// field definitions
/// RADIO_WAKE_UP_TIME field mask
#define NXMAC_RADIO_WAKE_UP_TIME_MASK ((uint32_t)0xFFC00000)
/// RADIO_WAKE_UP_TIME field LSB position
#define NXMAC_RADIO_WAKE_UP_TIME_LSB 22
/// RADIO_WAKE_UP_TIME field width
#define NXMAC_RADIO_WAKE_UP_TIME_WIDTH ((uint32_t)0x0000000A)
/// RADIO_CHIRP_TIME field mask
#define NXMAC_RADIO_CHIRP_TIME_MASK ((uint32_t)0x003FF000)
/// RADIO_CHIRP_TIME field LSB position
#define NXMAC_RADIO_CHIRP_TIME_LSB 12
/// RADIO_CHIRP_TIME field width
#define NXMAC_RADIO_CHIRP_TIME_WIDTH ((uint32_t)0x0000000A)
/// WT_2_CRYPT_CLK_RATIO field mask
#define NXMAC_WT_2_CRYPT_CLK_RATIO_MASK ((uint32_t)0x00000003)
/// WT_2_CRYPT_CLK_RATIO field LSB position
#define NXMAC_WT_2_CRYPT_CLK_RATIO_LSB 0
/// WT_2_CRYPT_CLK_RATIO field width
#define NXMAC_WT_2_CRYPT_CLK_RATIO_WIDTH ((uint32_t)0x00000002)
/// RADIO_WAKE_UP_TIME field reset value
#define NXMAC_RADIO_WAKE_UP_TIME_RST 0x0
/// RADIO_CHIRP_TIME field reset value
#define NXMAC_RADIO_CHIRP_TIME_RST 0x0
/// WT_2_CRYPT_CLK_RATIO field reset value
#define NXMAC_WT_2_CRYPT_CLK_RATIO_RST 0x0
/**
* @brief Constructs a value for the TIMINGS_4 register given values for its fields
* and writes the value to the register.
*
* @param[in] radiowakeuptime - The value to use for the radioWakeUpTime field.
* @param[in] radiochirptime - The value to use for the radioChirpTime field.
* @param[in] wt2cryptclkratio - The value to use for the wt2CryptClkRatio field.
*/
__INLINE void nxmac_timings_4_pack(uint16_t radiowakeuptime, uint16_t radiochirptime, uint8_t wt2cryptclkratio)
{
ASSERT_ERR((((uint32_t)radiowakeuptime << 22) & ~((uint32_t)0xFFC00000)) == 0);
ASSERT_ERR((((uint32_t)radiochirptime << 12) & ~((uint32_t)0x003FF000)) == 0);
ASSERT_ERR((((uint32_t)wt2cryptclkratio << 0) & ~((uint32_t)0x00000003)) == 0);
REG_PL_WR(NXMAC_TIMINGS_4_ADDR, ((uint32_t)radiowakeuptime << 22) | ((uint32_t)radiochirptime << 12) | ((uint32_t)wt2cryptclkratio << 0));
}
/**
* @brief Unpacks TIMINGS_4's fields from current value of the TIMINGS_4 register.
*
* Reads the TIMINGS_4 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] radiowakeuptime - Will be populated with the current value of this field from the register.
* @param[out] radiochirptime - Will be populated with the current value of this field from the register.
* @param[out] wt2cryptclkratio - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_timings_4_unpack(uint16_t *radiowakeuptime, uint16_t *radiochirptime, uint8_t *wt2cryptclkratio)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_4_ADDR);
*radiowakeuptime = (localVal & ((uint32_t)0xFFC00000)) >> 22;
*radiochirptime = (localVal & ((uint32_t)0x003FF000)) >> 12;
*wt2cryptclkratio = (localVal & ((uint32_t)0x00000003)) >> 0;
}
/**
* @brief Returns the current value of the radioWakeUpTime field in the TIMINGS_4 register.
*
* The TIMINGS_4 register will be read and the radioWakeUpTime field's value will be returned.
*
* @return The current value of the radioWakeUpTime field in the TIMINGS_4 register.
*/
__INLINE uint16_t nxmac_radio_wake_up_time_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_4_ADDR);
return ((localVal & ((uint32_t)0xFFC00000)) >> 22);
}
/**
* @brief Sets the radioWakeUpTime field of the TIMINGS_4 register.
*
* The TIMINGS_4 register will be read, modified to contain the new field value, and written.
*
* @param[in] radiowakeuptime - The value to set the field to.
*/
__INLINE void nxmac_radio_wake_up_time_setf(uint16_t radiowakeuptime)
{
ASSERT_ERR((((uint32_t)radiowakeuptime << 22) & ~((uint32_t)0xFFC00000)) == 0);
REG_PL_WR(NXMAC_TIMINGS_4_ADDR, (REG_PL_RD(NXMAC_TIMINGS_4_ADDR) & ~((uint32_t)0xFFC00000)) | ((uint32_t)radiowakeuptime << 22));
}
/**
* @brief Returns the current value of the radioChirpTime field in the TIMINGS_4 register.
*
* The TIMINGS_4 register will be read and the radioChirpTime field's value will be returned.
*
* @return The current value of the radioChirpTime field in the TIMINGS_4 register.
*/
__INLINE uint16_t nxmac_radio_chirp_time_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_4_ADDR);
return ((localVal & ((uint32_t)0x003FF000)) >> 12);
}
/**
* @brief Sets the radioChirpTime field of the TIMINGS_4 register.
*
* The TIMINGS_4 register will be read, modified to contain the new field value, and written.
*
* @param[in] radiochirptime - The value to set the field to.
*/
__INLINE void nxmac_radio_chirp_time_setf(uint16_t radiochirptime)
{
ASSERT_ERR((((uint32_t)radiochirptime << 12) & ~((uint32_t)0x003FF000)) == 0);
REG_PL_WR(NXMAC_TIMINGS_4_ADDR, (REG_PL_RD(NXMAC_TIMINGS_4_ADDR) & ~((uint32_t)0x003FF000)) | ((uint32_t)radiochirptime << 12));
}
/**
* @brief Returns the current value of the wt2CryptClkRatio field in the TIMINGS_4 register.
*
* The TIMINGS_4 register will be read and the wt2CryptClkRatio field's value will be returned.
*
* @return The current value of the wt2CryptClkRatio field in the TIMINGS_4 register.
*/
__INLINE uint8_t nxmac_wt_2_crypt_clk_ratio_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_4_ADDR);
return ((localVal & ((uint32_t)0x00000003)) >> 0);
}
/**
* @brief Sets the wt2CryptClkRatio field of the TIMINGS_4 register.
*
* The TIMINGS_4 register will be read, modified to contain the new field value, and written.
*
* @param[in] wt2cryptclkratio - The value to set the field to.
*/
__INLINE void nxmac_wt_2_crypt_clk_ratio_setf(uint8_t wt2cryptclkratio)
{
ASSERT_ERR((((uint32_t)wt2cryptclkratio << 0) & ~((uint32_t)0x00000003)) == 0);
REG_PL_WR(NXMAC_TIMINGS_4_ADDR, (REG_PL_RD(NXMAC_TIMINGS_4_ADDR) & ~((uint32_t)0x00000003)) | ((uint32_t)wt2cryptclkratio << 0));
}
/// @}
/**
* @name TIMINGS_5 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23:08 sifsBInMACClk 0x0
* 07:00 sifsB 0x0
* </pre>
*
* @{
*/
/// Address of the TIMINGS_5 register
#define NXMAC_TIMINGS_5_ADDR 0xC00000F4
/// Offset of the TIMINGS_5 register from the base address
#define NXMAC_TIMINGS_5_OFFSET 0x000000F4
/// Index of the TIMINGS_5 register
#define NXMAC_TIMINGS_5_INDEX 0x0000003D
/// Reset value of the TIMINGS_5 register
#define NXMAC_TIMINGS_5_RESET 0x00000000
/**
* @brief Returns the current value of the TIMINGS_5 register.
* The TIMINGS_5 register will be read and its value returned.
* @return The current value of the TIMINGS_5 register.
*/
__INLINE uint32_t nxmac_timings_5_get(void)
{
return REG_PL_RD(NXMAC_TIMINGS_5_ADDR);
}
/**
* @brief Sets the TIMINGS_5 register to a value.
* The TIMINGS_5 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_timings_5_set(uint32_t value)
{
REG_PL_WR(NXMAC_TIMINGS_5_ADDR, value);
}
// field definitions
/// SIFS_B_IN_MAC_CLK field mask
#define NXMAC_SIFS_B_IN_MAC_CLK_MASK ((uint32_t)0x00FFFF00)
/// SIFS_B_IN_MAC_CLK field LSB position
#define NXMAC_SIFS_B_IN_MAC_CLK_LSB 8
/// SIFS_B_IN_MAC_CLK field width
#define NXMAC_SIFS_B_IN_MAC_CLK_WIDTH ((uint32_t)0x00000010)
/// SIFS_B field mask
#define NXMAC_SIFS_B_MASK ((uint32_t)0x000000FF)
/// SIFS_B field LSB position
#define NXMAC_SIFS_B_LSB 0
/// SIFS_B field width
#define NXMAC_SIFS_B_WIDTH ((uint32_t)0x00000008)
/// SIFS_B_IN_MAC_CLK field reset value
#define NXMAC_SIFS_B_IN_MAC_CLK_RST 0x0
/// SIFS_B field reset value
#define NXMAC_SIFS_B_RST 0x0
/**
* @brief Constructs a value for the TIMINGS_5 register given values for its fields
* and writes the value to the register.
*
* @param[in] sifsbinmacclk - The value to use for the sifsBInMACClk field.
* @param[in] sifsb - The value to use for the sifsB field.
*/
__INLINE void nxmac_timings_5_pack(uint16_t sifsbinmacclk, uint8_t sifsb)
{
ASSERT_ERR((((uint32_t)sifsbinmacclk << 8) & ~((uint32_t)0x00FFFF00)) == 0);
ASSERT_ERR((((uint32_t)sifsb << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_5_ADDR, ((uint32_t)sifsbinmacclk << 8) | ((uint32_t)sifsb << 0));
}
/**
* @brief Unpacks TIMINGS_5's fields from current value of the TIMINGS_5 register.
*
* Reads the TIMINGS_5 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] sifsbinmacclk - Will be populated with the current value of this field from the register.
* @param[out] sifsb - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_timings_5_unpack(uint16_t *sifsbinmacclk, uint8_t *sifsb)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_5_ADDR);
*sifsbinmacclk = (localVal & ((uint32_t)0x00FFFF00)) >> 8;
*sifsb = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the sifsBInMACClk field in the TIMINGS_5 register.
*
* The TIMINGS_5 register will be read and the sifsBInMACClk field's value will be returned.
*
* @return The current value of the sifsBInMACClk field in the TIMINGS_5 register.
*/
__INLINE uint16_t nxmac_sifs_b_in_mac_clk_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_5_ADDR);
return ((localVal & ((uint32_t)0x00FFFF00)) >> 8);
}
/**
* @brief Sets the sifsBInMACClk field of the TIMINGS_5 register.
*
* The TIMINGS_5 register will be read, modified to contain the new field value, and written.
*
* @param[in] sifsbinmacclk - The value to set the field to.
*/
__INLINE void nxmac_sifs_b_in_mac_clk_setf(uint16_t sifsbinmacclk)
{
ASSERT_ERR((((uint32_t)sifsbinmacclk << 8) & ~((uint32_t)0x00FFFF00)) == 0);
REG_PL_WR(NXMAC_TIMINGS_5_ADDR, (REG_PL_RD(NXMAC_TIMINGS_5_ADDR) & ~((uint32_t)0x00FFFF00)) | ((uint32_t)sifsbinmacclk << 8));
}
/**
* @brief Returns the current value of the sifsB field in the TIMINGS_5 register.
*
* The TIMINGS_5 register will be read and the sifsB field's value will be returned.
*
* @return The current value of the sifsB field in the TIMINGS_5 register.
*/
__INLINE uint8_t nxmac_sifs_b_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_5_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the sifsB field of the TIMINGS_5 register.
*
* The TIMINGS_5 register will be read, modified to contain the new field value, and written.
*
* @param[in] sifsb - The value to set the field to.
*/
__INLINE void nxmac_sifs_b_setf(uint8_t sifsb)
{
ASSERT_ERR((((uint32_t)sifsb << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_5_ADDR, (REG_PL_RD(NXMAC_TIMINGS_5_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)sifsb << 0));
}
/// @}
/**
* @name TIMINGS_6 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23:08 sifsAInMACClk 0x0
* 07:00 sifsA 0x0
* </pre>
*
* @{
*/
/// Address of the TIMINGS_6 register
#define NXMAC_TIMINGS_6_ADDR 0xC00000F8
/// Offset of the TIMINGS_6 register from the base address
#define NXMAC_TIMINGS_6_OFFSET 0x000000F8
/// Index of the TIMINGS_6 register
#define NXMAC_TIMINGS_6_INDEX 0x0000003E
/// Reset value of the TIMINGS_6 register
#define NXMAC_TIMINGS_6_RESET 0x00000000
/**
* @brief Returns the current value of the TIMINGS_6 register.
* The TIMINGS_6 register will be read and its value returned.
* @return The current value of the TIMINGS_6 register.
*/
__INLINE uint32_t nxmac_timings_6_get(void)
{
return REG_PL_RD(NXMAC_TIMINGS_6_ADDR);
}
/**
* @brief Sets the TIMINGS_6 register to a value.
* The TIMINGS_6 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_timings_6_set(uint32_t value)
{
REG_PL_WR(NXMAC_TIMINGS_6_ADDR, value);
}
// field definitions
/// SIFS_A_IN_MAC_CLK field mask
#define NXMAC_SIFS_A_IN_MAC_CLK_MASK ((uint32_t)0x00FFFF00)
/// SIFS_A_IN_MAC_CLK field LSB position
#define NXMAC_SIFS_A_IN_MAC_CLK_LSB 8
/// SIFS_A_IN_MAC_CLK field width
#define NXMAC_SIFS_A_IN_MAC_CLK_WIDTH ((uint32_t)0x00000010)
/// SIFS_A field mask
#define NXMAC_SIFS_A_MASK ((uint32_t)0x000000FF)
/// SIFS_A field LSB position
#define NXMAC_SIFS_A_LSB 0
/// SIFS_A field width
#define NXMAC_SIFS_A_WIDTH ((uint32_t)0x00000008)
/// SIFS_A_IN_MAC_CLK field reset value
#define NXMAC_SIFS_A_IN_MAC_CLK_RST 0x0
/// SIFS_A field reset value
#define NXMAC_SIFS_A_RST 0x0
/**
* @brief Constructs a value for the TIMINGS_6 register given values for its fields
* and writes the value to the register.
*
* @param[in] sifsainmacclk - The value to use for the sifsAInMACClk field.
* @param[in] sifsa - The value to use for the sifsA field.
*/
__INLINE void nxmac_timings_6_pack(uint16_t sifsainmacclk, uint8_t sifsa)
{
ASSERT_ERR((((uint32_t)sifsainmacclk << 8) & ~((uint32_t)0x00FFFF00)) == 0);
ASSERT_ERR((((uint32_t)sifsa << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_6_ADDR, ((uint32_t)sifsainmacclk << 8) | ((uint32_t)sifsa << 0));
}
/**
* @brief Unpacks TIMINGS_6's fields from current value of the TIMINGS_6 register.
*
* Reads the TIMINGS_6 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] sifsainmacclk - Will be populated with the current value of this field from the register.
* @param[out] sifsa - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_timings_6_unpack(uint16_t *sifsainmacclk, uint8_t *sifsa)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_6_ADDR);
*sifsainmacclk = (localVal & ((uint32_t)0x00FFFF00)) >> 8;
*sifsa = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the sifsAInMACClk field in the TIMINGS_6 register.
*
* The TIMINGS_6 register will be read and the sifsAInMACClk field's value will be returned.
*
* @return The current value of the sifsAInMACClk field in the TIMINGS_6 register.
*/
__INLINE uint16_t nxmac_sifs_a_in_mac_clk_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_6_ADDR);
return ((localVal & ((uint32_t)0x00FFFF00)) >> 8);
}
/**
* @brief Sets the sifsAInMACClk field of the TIMINGS_6 register.
*
* The TIMINGS_6 register will be read, modified to contain the new field value, and written.
*
* @param[in] sifsainmacclk - The value to set the field to.
*/
__INLINE void nxmac_sifs_a_in_mac_clk_setf(uint16_t sifsainmacclk)
{
ASSERT_ERR((((uint32_t)sifsainmacclk << 8) & ~((uint32_t)0x00FFFF00)) == 0);
REG_PL_WR(NXMAC_TIMINGS_6_ADDR, (REG_PL_RD(NXMAC_TIMINGS_6_ADDR) & ~((uint32_t)0x00FFFF00)) | ((uint32_t)sifsainmacclk << 8));
}
/**
* @brief Returns the current value of the sifsA field in the TIMINGS_6 register.
*
* The TIMINGS_6 register will be read and the sifsA field's value will be returned.
*
* @return The current value of the sifsA field in the TIMINGS_6 register.
*/
__INLINE uint8_t nxmac_sifs_a_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_6_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the sifsA field of the TIMINGS_6 register.
*
* The TIMINGS_6 register will be read, modified to contain the new field value, and written.
*
* @param[in] sifsa - The value to set the field to.
*/
__INLINE void nxmac_sifs_a_setf(uint8_t sifsa)
{
ASSERT_ERR((((uint32_t)sifsa << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_6_ADDR, (REG_PL_RD(NXMAC_TIMINGS_6_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)sifsa << 0));
}
/// @}
/**
* @name TIMINGS_7 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 11:08 rxCCADelay 0x0
* 07:00 rifs 0x0
* </pre>
*
* @{
*/
/// Address of the TIMINGS_7 register
#define NXMAC_TIMINGS_7_ADDR 0xC00000FC
/// Offset of the TIMINGS_7 register from the base address
#define NXMAC_TIMINGS_7_OFFSET 0x000000FC
/// Index of the TIMINGS_7 register
#define NXMAC_TIMINGS_7_INDEX 0x0000003F
/// Reset value of the TIMINGS_7 register
#define NXMAC_TIMINGS_7_RESET 0x00000000
/**
* @brief Returns the current value of the TIMINGS_7 register.
* The TIMINGS_7 register will be read and its value returned.
* @return The current value of the TIMINGS_7 register.
*/
__INLINE uint32_t nxmac_timings_7_get(void)
{
return REG_PL_RD(NXMAC_TIMINGS_7_ADDR);
}
/**
* @brief Sets the TIMINGS_7 register to a value.
* The TIMINGS_7 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_timings_7_set(uint32_t value)
{
REG_PL_WR(NXMAC_TIMINGS_7_ADDR, value);
}
// field definitions
/// RX_CCA_DELAY field mask
#define NXMAC_RX_CCA_DELAY_MASK ((uint32_t)0x00000F00)
/// RX_CCA_DELAY field LSB position
#define NXMAC_RX_CCA_DELAY_LSB 8
/// RX_CCA_DELAY field width
#define NXMAC_RX_CCA_DELAY_WIDTH ((uint32_t)0x00000004)
/// RIFS field mask
#define NXMAC_RIFS_MASK ((uint32_t)0x000000FF)
/// RIFS field LSB position
#define NXMAC_RIFS_LSB 0
/// RIFS field width
#define NXMAC_RIFS_WIDTH ((uint32_t)0x00000008)
/// RX_CCA_DELAY field reset value
#define NXMAC_RX_CCA_DELAY_RST 0x0
/// RIFS field reset value
#define NXMAC_RIFS_RST 0x0
/**
* @brief Constructs a value for the TIMINGS_7 register given values for its fields
* and writes the value to the register.
*
* @param[in] rxccadelay - The value to use for the rxCCADelay field.
* @param[in] rifs - The value to use for the rifs field.
*/
__INLINE void nxmac_timings_7_pack(uint8_t rxccadelay, uint8_t rifs)
{
ASSERT_ERR((((uint32_t)rxccadelay << 8) & ~((uint32_t)0x00000F00)) == 0);
ASSERT_ERR((((uint32_t)rifs << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_7_ADDR, ((uint32_t)rxccadelay << 8) | ((uint32_t)rifs << 0));
}
/**
* @brief Unpacks TIMINGS_7's fields from current value of the TIMINGS_7 register.
*
* Reads the TIMINGS_7 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] rxccadelay - Will be populated with the current value of this field from the register.
* @param[out] rifs - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_timings_7_unpack(uint8_t *rxccadelay, uint8_t *rifs)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_7_ADDR);
*rxccadelay = (localVal & ((uint32_t)0x00000F00)) >> 8;
*rifs = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the rxCCADelay field in the TIMINGS_7 register.
*
* The TIMINGS_7 register will be read and the rxCCADelay field's value will be returned.
*
* @return The current value of the rxCCADelay field in the TIMINGS_7 register.
*/
__INLINE uint8_t nxmac_rx_cca_delay_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_7_ADDR);
return ((localVal & ((uint32_t)0x00000F00)) >> 8);
}
/**
* @brief Sets the rxCCADelay field of the TIMINGS_7 register.
*
* The TIMINGS_7 register will be read, modified to contain the new field value, and written.
*
* @param[in] rxccadelay - The value to set the field to.
*/
__INLINE void nxmac_rx_cca_delay_setf(uint8_t rxccadelay)
{
ASSERT_ERR((((uint32_t)rxccadelay << 8) & ~((uint32_t)0x00000F00)) == 0);
REG_PL_WR(NXMAC_TIMINGS_7_ADDR, (REG_PL_RD(NXMAC_TIMINGS_7_ADDR) & ~((uint32_t)0x00000F00)) | ((uint32_t)rxccadelay << 8));
}
/**
* @brief Returns the current value of the rifs field in the TIMINGS_7 register.
*
* The TIMINGS_7 register will be read and the rifs field's value will be returned.
*
* @return The current value of the rifs field in the TIMINGS_7 register.
*/
__INLINE uint8_t nxmac_rifs_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_7_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the rifs field of the TIMINGS_7 register.
*
* The TIMINGS_7 register will be read, modified to contain the new field value, and written.
*
* @param[in] rifs - The value to set the field to.
*/
__INLINE void nxmac_rifs_setf(uint8_t rifs)
{
ASSERT_ERR((((uint32_t)rifs << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_7_ADDR, (REG_PL_RD(NXMAC_TIMINGS_7_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)rifs << 0));
}
/// @}
/**
* @name TIMINGS_8 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:24 rxStartDelayMIMO 0x21
* 23:16 rxStartDelayShort 0x66
* 15:08 rxStartDelayLong 0xC6
* 07:00 rxStartDelayOFDM 0x21
* </pre>
*
* @{
*/
/// Address of the TIMINGS_8 register
#define NXMAC_TIMINGS_8_ADDR 0xC0000100
/// Offset of the TIMINGS_8 register from the base address
#define NXMAC_TIMINGS_8_OFFSET 0x00000100
/// Index of the TIMINGS_8 register
#define NXMAC_TIMINGS_8_INDEX 0x00000040
/// Reset value of the TIMINGS_8 register
#define NXMAC_TIMINGS_8_RESET 0x2166C621
/**
* @brief Returns the current value of the TIMINGS_8 register.
* The TIMINGS_8 register will be read and its value returned.
* @return The current value of the TIMINGS_8 register.
*/
__INLINE uint32_t nxmac_timings_8_get(void)
{
return REG_PL_RD(NXMAC_TIMINGS_8_ADDR);
}
/**
* @brief Sets the TIMINGS_8 register to a value.
* The TIMINGS_8 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_timings_8_set(uint32_t value)
{
REG_PL_WR(NXMAC_TIMINGS_8_ADDR, value);
}
// field definitions
/// RX_START_DELAY_MIMO field mask
#define NXMAC_RX_START_DELAY_MIMO_MASK ((uint32_t)0xFF000000)
/// RX_START_DELAY_MIMO field LSB position
#define NXMAC_RX_START_DELAY_MIMO_LSB 24
/// RX_START_DELAY_MIMO field width
#define NXMAC_RX_START_DELAY_MIMO_WIDTH ((uint32_t)0x00000008)
/// RX_START_DELAY_SHORT field mask
#define NXMAC_RX_START_DELAY_SHORT_MASK ((uint32_t)0x00FF0000)
/// RX_START_DELAY_SHORT field LSB position
#define NXMAC_RX_START_DELAY_SHORT_LSB 16
/// RX_START_DELAY_SHORT field width
#define NXMAC_RX_START_DELAY_SHORT_WIDTH ((uint32_t)0x00000008)
/// RX_START_DELAY_LONG field mask
#define NXMAC_RX_START_DELAY_LONG_MASK ((uint32_t)0x0000FF00)
/// RX_START_DELAY_LONG field LSB position
#define NXMAC_RX_START_DELAY_LONG_LSB 8
/// RX_START_DELAY_LONG field width
#define NXMAC_RX_START_DELAY_LONG_WIDTH ((uint32_t)0x00000008)
/// RX_START_DELAY_OFDM field mask
#define NXMAC_RX_START_DELAY_OFDM_MASK ((uint32_t)0x000000FF)
/// RX_START_DELAY_OFDM field LSB position
#define NXMAC_RX_START_DELAY_OFDM_LSB 0
/// RX_START_DELAY_OFDM field width
#define NXMAC_RX_START_DELAY_OFDM_WIDTH ((uint32_t)0x00000008)
/// RX_START_DELAY_MIMO field reset value
#define NXMAC_RX_START_DELAY_MIMO_RST 0x21
/// RX_START_DELAY_SHORT field reset value
#define NXMAC_RX_START_DELAY_SHORT_RST 0x66
/// RX_START_DELAY_LONG field reset value
#define NXMAC_RX_START_DELAY_LONG_RST 0xC6
/// RX_START_DELAY_OFDM field reset value
#define NXMAC_RX_START_DELAY_OFDM_RST 0x21
/**
* @brief Constructs a value for the TIMINGS_8 register given values for its fields
* and writes the value to the register.
*
* @param[in] rxstartdelaymimo - The value to use for the rxStartDelayMIMO field.
* @param[in] rxstartdelayshort - The value to use for the rxStartDelayShort field.
* @param[in] rxstartdelaylong - The value to use for the rxStartDelayLong field.
* @param[in] rxstartdelayofdm - The value to use for the rxStartDelayOFDM field.
*/
__INLINE void nxmac_timings_8_pack(uint8_t rxstartdelaymimo, uint8_t rxstartdelayshort, uint8_t rxstartdelaylong, uint8_t rxstartdelayofdm)
{
ASSERT_ERR((((uint32_t)rxstartdelaymimo << 24) & ~((uint32_t)0xFF000000)) == 0);
ASSERT_ERR((((uint32_t)rxstartdelayshort << 16) & ~((uint32_t)0x00FF0000)) == 0);
ASSERT_ERR((((uint32_t)rxstartdelaylong << 8) & ~((uint32_t)0x0000FF00)) == 0);
ASSERT_ERR((((uint32_t)rxstartdelayofdm << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_8_ADDR, ((uint32_t)rxstartdelaymimo << 24) | ((uint32_t)rxstartdelayshort << 16) | ((uint32_t)rxstartdelaylong << 8) | ((uint32_t)rxstartdelayofdm << 0));
}
/**
* @brief Unpacks TIMINGS_8's fields from current value of the TIMINGS_8 register.
*
* Reads the TIMINGS_8 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] rxstartdelaymimo - Will be populated with the current value of this field from the register.
* @param[out] rxstartdelayshort - Will be populated with the current value of this field from the register.
* @param[out] rxstartdelaylong - Will be populated with the current value of this field from the register.
* @param[out] rxstartdelayofdm - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_timings_8_unpack(uint8_t *rxstartdelaymimo, uint8_t *rxstartdelayshort, uint8_t *rxstartdelaylong, uint8_t *rxstartdelayofdm)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_8_ADDR);
*rxstartdelaymimo = (localVal & ((uint32_t)0xFF000000)) >> 24;
*rxstartdelayshort = (localVal & ((uint32_t)0x00FF0000)) >> 16;
*rxstartdelaylong = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*rxstartdelayofdm = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the rxStartDelayMIMO field in the TIMINGS_8 register.
*
* The TIMINGS_8 register will be read and the rxStartDelayMIMO field's value will be returned.
*
* @return The current value of the rxStartDelayMIMO field in the TIMINGS_8 register.
*/
__INLINE uint8_t nxmac_rx_start_delay_mimo_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_8_ADDR);
return ((localVal & ((uint32_t)0xFF000000)) >> 24);
}
/**
* @brief Sets the rxStartDelayMIMO field of the TIMINGS_8 register.
*
* The TIMINGS_8 register will be read, modified to contain the new field value, and written.
*
* @param[in] rxstartdelaymimo - The value to set the field to.
*/
__INLINE void nxmac_rx_start_delay_mimo_setf(uint8_t rxstartdelaymimo)
{
ASSERT_ERR((((uint32_t)rxstartdelaymimo << 24) & ~((uint32_t)0xFF000000)) == 0);
REG_PL_WR(NXMAC_TIMINGS_8_ADDR, (REG_PL_RD(NXMAC_TIMINGS_8_ADDR) & ~((uint32_t)0xFF000000)) | ((uint32_t)rxstartdelaymimo << 24));
}
/**
* @brief Returns the current value of the rxStartDelayShort field in the TIMINGS_8 register.
*
* The TIMINGS_8 register will be read and the rxStartDelayShort field's value will be returned.
*
* @return The current value of the rxStartDelayShort field in the TIMINGS_8 register.
*/
__INLINE uint8_t nxmac_rx_start_delay_short_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_8_ADDR);
return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
}
/**
* @brief Sets the rxStartDelayShort field of the TIMINGS_8 register.
*
* The TIMINGS_8 register will be read, modified to contain the new field value, and written.
*
* @param[in] rxstartdelayshort - The value to set the field to.
*/
__INLINE void nxmac_rx_start_delay_short_setf(uint8_t rxstartdelayshort)
{
ASSERT_ERR((((uint32_t)rxstartdelayshort << 16) & ~((uint32_t)0x00FF0000)) == 0);
REG_PL_WR(NXMAC_TIMINGS_8_ADDR, (REG_PL_RD(NXMAC_TIMINGS_8_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)rxstartdelayshort << 16));
}
/**
* @brief Returns the current value of the rxStartDelayLong field in the TIMINGS_8 register.
*
* The TIMINGS_8 register will be read and the rxStartDelayLong field's value will be returned.
*
* @return The current value of the rxStartDelayLong field in the TIMINGS_8 register.
*/
__INLINE uint8_t nxmac_rx_start_delay_long_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_8_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Sets the rxStartDelayLong field of the TIMINGS_8 register.
*
* The TIMINGS_8 register will be read, modified to contain the new field value, and written.
*
* @param[in] rxstartdelaylong - The value to set the field to.
*/
__INLINE void nxmac_rx_start_delay_long_setf(uint8_t rxstartdelaylong)
{
ASSERT_ERR((((uint32_t)rxstartdelaylong << 8) & ~((uint32_t)0x0000FF00)) == 0);
REG_PL_WR(NXMAC_TIMINGS_8_ADDR, (REG_PL_RD(NXMAC_TIMINGS_8_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)rxstartdelaylong << 8));
}
/**
* @brief Returns the current value of the rxStartDelayOFDM field in the TIMINGS_8 register.
*
* The TIMINGS_8 register will be read and the rxStartDelayOFDM field's value will be returned.
*
* @return The current value of the rxStartDelayOFDM field in the TIMINGS_8 register.
*/
__INLINE uint8_t nxmac_rx_start_delay_ofdm_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_8_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the rxStartDelayOFDM field of the TIMINGS_8 register.
*
* The TIMINGS_8 register will be read, modified to contain the new field value, and written.
*
* @param[in] rxstartdelayofdm - The value to set the field to.
*/
__INLINE void nxmac_rx_start_delay_ofdm_setf(uint8_t rxstartdelayofdm)
{
ASSERT_ERR((((uint32_t)rxstartdelayofdm << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_8_ADDR, (REG_PL_RD(NXMAC_TIMINGS_8_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)rxstartdelayofdm << 0));
}
/// @}
/**
* @name TIMINGS_9 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 29:20 rifsTOInMACClk 0x0
* 19:10 rifsInMACClk 0x0
* 09:00 txDMAProcDlyInMACClk 0x0
* </pre>
*
* @{
*/
/// Address of the TIMINGS_9 register
#define NXMAC_TIMINGS_9_ADDR 0xC0000104
/// Offset of the TIMINGS_9 register from the base address
#define NXMAC_TIMINGS_9_OFFSET 0x00000104
/// Index of the TIMINGS_9 register
#define NXMAC_TIMINGS_9_INDEX 0x00000041
/// Reset value of the TIMINGS_9 register
#define NXMAC_TIMINGS_9_RESET 0x00000000
/**
* @brief Returns the current value of the TIMINGS_9 register.
* The TIMINGS_9 register will be read and its value returned.
* @return The current value of the TIMINGS_9 register.
*/
__INLINE uint32_t nxmac_timings_9_get(void)
{
return REG_PL_RD(NXMAC_TIMINGS_9_ADDR);
}
/**
* @brief Sets the TIMINGS_9 register to a value.
* The TIMINGS_9 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_timings_9_set(uint32_t value)
{
REG_PL_WR(NXMAC_TIMINGS_9_ADDR, value);
}
// field definitions
/// RIFS_TO_IN_MAC_CLK field mask
#define NXMAC_RIFS_TO_IN_MAC_CLK_MASK ((uint32_t)0x3FF00000)
/// RIFS_TO_IN_MAC_CLK field LSB position
#define NXMAC_RIFS_TO_IN_MAC_CLK_LSB 20
/// RIFS_TO_IN_MAC_CLK field width
#define NXMAC_RIFS_TO_IN_MAC_CLK_WIDTH ((uint32_t)0x0000000A)
/// RIFS_IN_MAC_CLK field mask
#define NXMAC_RIFS_IN_MAC_CLK_MASK ((uint32_t)0x000FFC00)
/// RIFS_IN_MAC_CLK field LSB position
#define NXMAC_RIFS_IN_MAC_CLK_LSB 10
/// RIFS_IN_MAC_CLK field width
#define NXMAC_RIFS_IN_MAC_CLK_WIDTH ((uint32_t)0x0000000A)
/// TX_DMA_PROC_DLY_IN_MAC_CLK field mask
#define NXMAC_TX_DMA_PROC_DLY_IN_MAC_CLK_MASK ((uint32_t)0x000003FF)
/// TX_DMA_PROC_DLY_IN_MAC_CLK field LSB position
#define NXMAC_TX_DMA_PROC_DLY_IN_MAC_CLK_LSB 0
/// TX_DMA_PROC_DLY_IN_MAC_CLK field width
#define NXMAC_TX_DMA_PROC_DLY_IN_MAC_CLK_WIDTH ((uint32_t)0x0000000A)
/// RIFS_TO_IN_MAC_CLK field reset value
#define NXMAC_RIFS_TO_IN_MAC_CLK_RST 0x0
/// RIFS_IN_MAC_CLK field reset value
#define NXMAC_RIFS_IN_MAC_CLK_RST 0x0
/// TX_DMA_PROC_DLY_IN_MAC_CLK field reset value
#define NXMAC_TX_DMA_PROC_DLY_IN_MAC_CLK_RST 0x0
/**
* @brief Constructs a value for the TIMINGS_9 register given values for its fields
* and writes the value to the register.
*
* @param[in] rifstoinmacclk - The value to use for the rifsTOInMACClk field.
* @param[in] rifsinmacclk - The value to use for the rifsInMACClk field.
* @param[in] txdmaprocdlyinmacclk - The value to use for the txDMAProcDlyInMACClk field.
*/
__INLINE void nxmac_timings_9_pack(uint16_t rifstoinmacclk, uint16_t rifsinmacclk, uint16_t txdmaprocdlyinmacclk)
{
ASSERT_ERR((((uint32_t)rifstoinmacclk << 20) & ~((uint32_t)0x3FF00000)) == 0);
ASSERT_ERR((((uint32_t)rifsinmacclk << 10) & ~((uint32_t)0x000FFC00)) == 0);
ASSERT_ERR((((uint32_t)txdmaprocdlyinmacclk << 0) & ~((uint32_t)0x000003FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_9_ADDR, ((uint32_t)rifstoinmacclk << 20) | ((uint32_t)rifsinmacclk << 10) | ((uint32_t)txdmaprocdlyinmacclk << 0));
}
/**
* @brief Unpacks TIMINGS_9's fields from current value of the TIMINGS_9 register.
*
* Reads the TIMINGS_9 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] rifstoinmacclk - Will be populated with the current value of this field from the register.
* @param[out] rifsinmacclk - Will be populated with the current value of this field from the register.
* @param[out] txdmaprocdlyinmacclk - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_timings_9_unpack(uint16_t *rifstoinmacclk, uint16_t *rifsinmacclk, uint16_t *txdmaprocdlyinmacclk)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_9_ADDR);
*rifstoinmacclk = (localVal & ((uint32_t)0x3FF00000)) >> 20;
*rifsinmacclk = (localVal & ((uint32_t)0x000FFC00)) >> 10;
*txdmaprocdlyinmacclk = (localVal & ((uint32_t)0x000003FF)) >> 0;
}
/**
* @brief Returns the current value of the rifsTOInMACClk field in the TIMINGS_9 register.
*
* The TIMINGS_9 register will be read and the rifsTOInMACClk field's value will be returned.
*
* @return The current value of the rifsTOInMACClk field in the TIMINGS_9 register.
*/
__INLINE uint16_t nxmac_rifs_to_in_mac_clk_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_9_ADDR);
return ((localVal & ((uint32_t)0x3FF00000)) >> 20);
}
/**
* @brief Sets the rifsTOInMACClk field of the TIMINGS_9 register.
*
* The TIMINGS_9 register will be read, modified to contain the new field value, and written.
*
* @param[in] rifstoinmacclk - The value to set the field to.
*/
__INLINE void nxmac_rifs_to_in_mac_clk_setf(uint16_t rifstoinmacclk)
{
ASSERT_ERR((((uint32_t)rifstoinmacclk << 20) & ~((uint32_t)0x3FF00000)) == 0);
REG_PL_WR(NXMAC_TIMINGS_9_ADDR, (REG_PL_RD(NXMAC_TIMINGS_9_ADDR) & ~((uint32_t)0x3FF00000)) | ((uint32_t)rifstoinmacclk << 20));
}
/**
* @brief Returns the current value of the rifsInMACClk field in the TIMINGS_9 register.
*
* The TIMINGS_9 register will be read and the rifsInMACClk field's value will be returned.
*
* @return The current value of the rifsInMACClk field in the TIMINGS_9 register.
*/
__INLINE uint16_t nxmac_rifs_in_mac_clk_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_9_ADDR);
return ((localVal & ((uint32_t)0x000FFC00)) >> 10);
}
/**
* @brief Sets the rifsInMACClk field of the TIMINGS_9 register.
*
* The TIMINGS_9 register will be read, modified to contain the new field value, and written.
*
* @param[in] rifsinmacclk - The value to set the field to.
*/
__INLINE void nxmac_rifs_in_mac_clk_setf(uint16_t rifsinmacclk)
{
ASSERT_ERR((((uint32_t)rifsinmacclk << 10) & ~((uint32_t)0x000FFC00)) == 0);
REG_PL_WR(NXMAC_TIMINGS_9_ADDR, (REG_PL_RD(NXMAC_TIMINGS_9_ADDR) & ~((uint32_t)0x000FFC00)) | ((uint32_t)rifsinmacclk << 10));
}
/**
* @brief Returns the current value of the txDMAProcDlyInMACClk field in the TIMINGS_9 register.
*
* The TIMINGS_9 register will be read and the txDMAProcDlyInMACClk field's value will be returned.
*
* @return The current value of the txDMAProcDlyInMACClk field in the TIMINGS_9 register.
*/
__INLINE uint16_t nxmac_tx_dma_proc_dly_in_mac_clk_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TIMINGS_9_ADDR);
return ((localVal & ((uint32_t)0x000003FF)) >> 0);
}
/**
* @brief Sets the txDMAProcDlyInMACClk field of the TIMINGS_9 register.
*
* The TIMINGS_9 register will be read, modified to contain the new field value, and written.
*
* @param[in] txdmaprocdlyinmacclk - The value to set the field to.
*/
__INLINE void nxmac_tx_dma_proc_dly_in_mac_clk_setf(uint16_t txdmaprocdlyinmacclk)
{
ASSERT_ERR((((uint32_t)txdmaprocdlyinmacclk << 0) & ~((uint32_t)0x000003FF)) == 0);
REG_PL_WR(NXMAC_TIMINGS_9_ADDR, (REG_PL_RD(NXMAC_TIMINGS_9_ADDR) & ~((uint32_t)0x000003FF)) | ((uint32_t)txdmaprocdlyinmacclk << 0));
}
/// @}
/**
* @name PROT_TRIG_TIMER register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:08 hccaTriggerTimer 0x0
* 07:00 edcaTriggerTimer 0x9
* </pre>
*
* @{
*/
/// Address of the PROT_TRIG_TIMER register
#define NXMAC_PROT_TRIG_TIMER_ADDR 0xC000010C
/// Offset of the PROT_TRIG_TIMER register from the base address
#define NXMAC_PROT_TRIG_TIMER_OFFSET 0x0000010C
/// Index of the PROT_TRIG_TIMER register
#define NXMAC_PROT_TRIG_TIMER_INDEX 0x00000043
/// Reset value of the PROT_TRIG_TIMER register
#define NXMAC_PROT_TRIG_TIMER_RESET 0x00000009
/**
* @brief Returns the current value of the PROT_TRIG_TIMER register.
* The PROT_TRIG_TIMER register will be read and its value returned.
* @return The current value of the PROT_TRIG_TIMER register.
*/
__INLINE uint32_t nxmac_prot_trig_timer_get(void)
{
return REG_PL_RD(NXMAC_PROT_TRIG_TIMER_ADDR);
}
/**
* @brief Sets the PROT_TRIG_TIMER register to a value.
* The PROT_TRIG_TIMER register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_prot_trig_timer_set(uint32_t value)
{
REG_PL_WR(NXMAC_PROT_TRIG_TIMER_ADDR, value);
}
// field definitions
/// HCCA_TRIGGER_TIMER field mask
#define NXMAC_HCCA_TRIGGER_TIMER_MASK ((uint32_t)0x0000FF00)
/// HCCA_TRIGGER_TIMER field LSB position
#define NXMAC_HCCA_TRIGGER_TIMER_LSB 8
/// HCCA_TRIGGER_TIMER field width
#define NXMAC_HCCA_TRIGGER_TIMER_WIDTH ((uint32_t)0x00000008)
/// EDCA_TRIGGER_TIMER field mask
#define NXMAC_EDCA_TRIGGER_TIMER_MASK ((uint32_t)0x000000FF)
/// EDCA_TRIGGER_TIMER field LSB position
#define NXMAC_EDCA_TRIGGER_TIMER_LSB 0
/// EDCA_TRIGGER_TIMER field width
#define NXMAC_EDCA_TRIGGER_TIMER_WIDTH ((uint32_t)0x00000008)
/// HCCA_TRIGGER_TIMER field reset value
#define NXMAC_HCCA_TRIGGER_TIMER_RST 0x0
/// EDCA_TRIGGER_TIMER field reset value
#define NXMAC_EDCA_TRIGGER_TIMER_RST 0x9
/**
* @brief Unpacks PROT_TRIG_TIMER's fields from current value of the PROT_TRIG_TIMER register.
*
* Reads the PROT_TRIG_TIMER register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] hccatriggertimer - Will be populated with the current value of this field from the register.
* @param[out] edcatriggertimer - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_prot_trig_timer_unpack(uint8_t *hccatriggertimer, uint8_t *edcatriggertimer)
{
uint32_t localVal = REG_PL_RD(NXMAC_PROT_TRIG_TIMER_ADDR);
*hccatriggertimer = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*edcatriggertimer = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the hccaTriggerTimer field in the PROT_TRIG_TIMER register.
*
* The PROT_TRIG_TIMER register will be read and the hccaTriggerTimer field's value will be returned.
*
* @return The current value of the hccaTriggerTimer field in the PROT_TRIG_TIMER register.
*/
__INLINE uint8_t nxmac_hcca_trigger_timer_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_PROT_TRIG_TIMER_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Returns the current value of the edcaTriggerTimer field in the PROT_TRIG_TIMER register.
*
* The PROT_TRIG_TIMER register will be read and the edcaTriggerTimer field's value will be returned.
*
* @return The current value of the edcaTriggerTimer field in the PROT_TRIG_TIMER register.
*/
__INLINE uint8_t nxmac_edca_trigger_timer_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_PROT_TRIG_TIMER_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the edcaTriggerTimer field of the PROT_TRIG_TIMER register.
*
* The PROT_TRIG_TIMER register will be read, modified to contain the new field value, and written.
*
* @param[in] edcatriggertimer - The value to set the field to.
*/
__INLINE void nxmac_edca_trigger_timer_setf(uint8_t edcatriggertimer)
{
ASSERT_ERR((((uint32_t)edcatriggertimer << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_PROT_TRIG_TIMER_ADDR, (uint32_t)edcatriggertimer << 0);
}
/// @}
/**
* @name TX_TRIGGER_TIMER register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 15:08 txPacketTimeout 0xF
* 07:00 txAbsoluteTimeout 0x9C
* </pre>
*
* @{
*/
/// Address of the TX_TRIGGER_TIMER register
#define NXMAC_TX_TRIGGER_TIMER_ADDR 0xC0000110
/// Offset of the TX_TRIGGER_TIMER register from the base address
#define NXMAC_TX_TRIGGER_TIMER_OFFSET 0x00000110
/// Index of the TX_TRIGGER_TIMER register
#define NXMAC_TX_TRIGGER_TIMER_INDEX 0x00000044
/// Reset value of the TX_TRIGGER_TIMER register
#define NXMAC_TX_TRIGGER_TIMER_RESET 0x00000F9C
/**
* @brief Returns the current value of the TX_TRIGGER_TIMER register.
* The TX_TRIGGER_TIMER register will be read and its value returned.
* @return The current value of the TX_TRIGGER_TIMER register.
*/
__INLINE uint32_t nxmac_tx_trigger_timer_get(void)
{
return REG_PL_RD(NXMAC_TX_TRIGGER_TIMER_ADDR);
}
/**
* @brief Sets the TX_TRIGGER_TIMER register to a value.
* The TX_TRIGGER_TIMER register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_tx_trigger_timer_set(uint32_t value)
{
REG_PL_WR(NXMAC_TX_TRIGGER_TIMER_ADDR, value);
}
// field definitions
/// TX_PACKET_TIMEOUT field mask
#define NXMAC_TX_PACKET_TIMEOUT_MASK ((uint32_t)0x0000FF00)
/// TX_PACKET_TIMEOUT field LSB position
#define NXMAC_TX_PACKET_TIMEOUT_LSB 8
/// TX_PACKET_TIMEOUT field width
#define NXMAC_TX_PACKET_TIMEOUT_WIDTH ((uint32_t)0x00000008)
/// TX_ABSOLUTE_TIMEOUT field mask
#define NXMAC_TX_ABSOLUTE_TIMEOUT_MASK ((uint32_t)0x000000FF)
/// TX_ABSOLUTE_TIMEOUT field LSB position
#define NXMAC_TX_ABSOLUTE_TIMEOUT_LSB 0
/// TX_ABSOLUTE_TIMEOUT field width
#define NXMAC_TX_ABSOLUTE_TIMEOUT_WIDTH ((uint32_t)0x00000008)
/// TX_PACKET_TIMEOUT field reset value
#define NXMAC_TX_PACKET_TIMEOUT_RST 0xF
/// TX_ABSOLUTE_TIMEOUT field reset value
#define NXMAC_TX_ABSOLUTE_TIMEOUT_RST 0x9C
/**
* @brief Constructs a value for the TX_TRIGGER_TIMER register given values for its fields
* and writes the value to the register.
*
* @param[in] txpackettimeout - The value to use for the txPacketTimeout field.
* @param[in] txabsolutetimeout - The value to use for the txAbsoluteTimeout field.
*/
__INLINE void nxmac_tx_trigger_timer_pack(uint8_t txpackettimeout, uint8_t txabsolutetimeout)
{
ASSERT_ERR((((uint32_t)txpackettimeout << 8) & ~((uint32_t)0x0000FF00)) == 0);
ASSERT_ERR((((uint32_t)txabsolutetimeout << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TX_TRIGGER_TIMER_ADDR, ((uint32_t)txpackettimeout << 8) | ((uint32_t)txabsolutetimeout << 0));
}
/**
* @brief Unpacks TX_TRIGGER_TIMER's fields from current value of the TX_TRIGGER_TIMER register.
*
* Reads the TX_TRIGGER_TIMER register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] txpackettimeout - Will be populated with the current value of this field from the register.
* @param[out] txabsolutetimeout - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_tx_trigger_timer_unpack(uint8_t *txpackettimeout, uint8_t *txabsolutetimeout)
{
uint32_t localVal = REG_PL_RD(NXMAC_TX_TRIGGER_TIMER_ADDR);
*txpackettimeout = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*txabsolutetimeout = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the txPacketTimeout field in the TX_TRIGGER_TIMER register.
*
* The TX_TRIGGER_TIMER register will be read and the txPacketTimeout field's value will be returned.
*
* @return The current value of the txPacketTimeout field in the TX_TRIGGER_TIMER register.
*/
__INLINE uint8_t nxmac_tx_packet_timeout_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TX_TRIGGER_TIMER_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Sets the txPacketTimeout field of the TX_TRIGGER_TIMER register.
*
* The TX_TRIGGER_TIMER register will be read, modified to contain the new field value, and written.
*
* @param[in] txpackettimeout - The value to set the field to.
*/
__INLINE void nxmac_tx_packet_timeout_setf(uint8_t txpackettimeout)
{
ASSERT_ERR((((uint32_t)txpackettimeout << 8) & ~((uint32_t)0x0000FF00)) == 0);
REG_PL_WR(NXMAC_TX_TRIGGER_TIMER_ADDR, (REG_PL_RD(NXMAC_TX_TRIGGER_TIMER_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)txpackettimeout << 8));
}
/**
* @brief Returns the current value of the txAbsoluteTimeout field in the TX_TRIGGER_TIMER register.
*
* The TX_TRIGGER_TIMER register will be read and the txAbsoluteTimeout field's value will be returned.
*
* @return The current value of the txAbsoluteTimeout field in the TX_TRIGGER_TIMER register.
*/
__INLINE uint8_t nxmac_tx_absolute_timeout_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_TX_TRIGGER_TIMER_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the txAbsoluteTimeout field of the TX_TRIGGER_TIMER register.
*
* The TX_TRIGGER_TIMER register will be read, modified to contain the new field value, and written.
*
* @param[in] txabsolutetimeout - The value to set the field to.
*/
__INLINE void nxmac_tx_absolute_timeout_setf(uint8_t txabsolutetimeout)
{
ASSERT_ERR((((uint32_t)txabsolutetimeout << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_TX_TRIGGER_TIMER_ADDR, (REG_PL_RD(NXMAC_TX_TRIGGER_TIMER_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)txabsolutetimeout << 0));
}
/// @}
/**
* @name RX_TRIGGER_TIMER register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 23:16 rxPayloadUsedCount 0xF
* 15:08 rxPacketTimeout 0xF
* 07:00 rxAbsoluteTimeout 0x9C
* </pre>
*
* @{
*/
/// Address of the RX_TRIGGER_TIMER register
#define NXMAC_RX_TRIGGER_TIMER_ADDR 0xC0000114
/// Offset of the RX_TRIGGER_TIMER register from the base address
#define NXMAC_RX_TRIGGER_TIMER_OFFSET 0x00000114
/// Index of the RX_TRIGGER_TIMER register
#define NXMAC_RX_TRIGGER_TIMER_INDEX 0x00000045
/// Reset value of the RX_TRIGGER_TIMER register
#define NXMAC_RX_TRIGGER_TIMER_RESET 0x000F0F9C
/**
* @brief Returns the current value of the RX_TRIGGER_TIMER register.
* The RX_TRIGGER_TIMER register will be read and its value returned.
* @return The current value of the RX_TRIGGER_TIMER register.
*/
__INLINE uint32_t nxmac_rx_trigger_timer_get(void)
{
return REG_PL_RD(NXMAC_RX_TRIGGER_TIMER_ADDR);
}
/**
* @brief Sets the RX_TRIGGER_TIMER register to a value.
* The RX_TRIGGER_TIMER register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_rx_trigger_timer_set(uint32_t value)
{
REG_PL_WR(NXMAC_RX_TRIGGER_TIMER_ADDR, value);
}
// field definitions
/// RX_PAYLOAD_USED_COUNT field mask
#define NXMAC_RX_PAYLOAD_USED_COUNT_MASK ((uint32_t)0x00FF0000)
/// RX_PAYLOAD_USED_COUNT field LSB position
#define NXMAC_RX_PAYLOAD_USED_COUNT_LSB 16
/// RX_PAYLOAD_USED_COUNT field width
#define NXMAC_RX_PAYLOAD_USED_COUNT_WIDTH ((uint32_t)0x00000008)
/// RX_PACKET_TIMEOUT field mask
#define NXMAC_RX_PACKET_TIMEOUT_MASK ((uint32_t)0x0000FF00)
/// RX_PACKET_TIMEOUT field LSB position
#define NXMAC_RX_PACKET_TIMEOUT_LSB 8
/// RX_PACKET_TIMEOUT field width
#define NXMAC_RX_PACKET_TIMEOUT_WIDTH ((uint32_t)0x00000008)
/// RX_ABSOLUTE_TIMEOUT field mask
#define NXMAC_RX_ABSOLUTE_TIMEOUT_MASK ((uint32_t)0x000000FF)
/// RX_ABSOLUTE_TIMEOUT field LSB position
#define NXMAC_RX_ABSOLUTE_TIMEOUT_LSB 0
/// RX_ABSOLUTE_TIMEOUT field width
#define NXMAC_RX_ABSOLUTE_TIMEOUT_WIDTH ((uint32_t)0x00000008)
/// RX_PAYLOAD_USED_COUNT field reset value
#define NXMAC_RX_PAYLOAD_USED_COUNT_RST 0xF
/// RX_PACKET_TIMEOUT field reset value
#define NXMAC_RX_PACKET_TIMEOUT_RST 0xF
/// RX_ABSOLUTE_TIMEOUT field reset value
#define NXMAC_RX_ABSOLUTE_TIMEOUT_RST 0x9C
/**
* @brief Constructs a value for the RX_TRIGGER_TIMER register given values for its fields
* and writes the value to the register.
*
* @param[in] rxpayloadusedcount - The value to use for the rxPayloadUsedCount field.
* @param[in] rxpackettimeout - The value to use for the rxPacketTimeout field.
* @param[in] rxabsolutetimeout - The value to use for the rxAbsoluteTimeout field.
*/
__INLINE void nxmac_rx_trigger_timer_pack(uint8_t rxpayloadusedcount, uint8_t rxpackettimeout, uint8_t rxabsolutetimeout)
{
ASSERT_ERR((((uint32_t)rxpayloadusedcount << 16) & ~((uint32_t)0x00FF0000)) == 0);
ASSERT_ERR((((uint32_t)rxpackettimeout << 8) & ~((uint32_t)0x0000FF00)) == 0);
ASSERT_ERR((((uint32_t)rxabsolutetimeout << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_RX_TRIGGER_TIMER_ADDR, ((uint32_t)rxpayloadusedcount << 16) | ((uint32_t)rxpackettimeout << 8) | ((uint32_t)rxabsolutetimeout << 0));
}
/**
* @brief Unpacks RX_TRIGGER_TIMER's fields from current value of the RX_TRIGGER_TIMER register.
*
* Reads the RX_TRIGGER_TIMER register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] rxpayloadusedcount - Will be populated with the current value of this field from the register.
* @param[out] rxpackettimeout - Will be populated with the current value of this field from the register.
* @param[out] rxabsolutetimeout - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_rx_trigger_timer_unpack(uint8_t *rxpayloadusedcount, uint8_t *rxpackettimeout, uint8_t *rxabsolutetimeout)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_TRIGGER_TIMER_ADDR);
*rxpayloadusedcount = (localVal & ((uint32_t)0x00FF0000)) >> 16;
*rxpackettimeout = (localVal & ((uint32_t)0x0000FF00)) >> 8;
*rxabsolutetimeout = (localVal & ((uint32_t)0x000000FF)) >> 0;
}
/**
* @brief Returns the current value of the rxPayloadUsedCount field in the RX_TRIGGER_TIMER register.
*
* The RX_TRIGGER_TIMER register will be read and the rxPayloadUsedCount field's value will be returned.
*
* @return The current value of the rxPayloadUsedCount field in the RX_TRIGGER_TIMER register.
*/
__INLINE uint8_t nxmac_rx_payload_used_count_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_TRIGGER_TIMER_ADDR);
return ((localVal & ((uint32_t)0x00FF0000)) >> 16);
}
/**
* @brief Sets the rxPayloadUsedCount field of the RX_TRIGGER_TIMER register.
*
* The RX_TRIGGER_TIMER register will be read, modified to contain the new field value, and written.
*
* @param[in] rxpayloadusedcount - The value to set the field to.
*/
__INLINE void nxmac_rx_payload_used_count_setf(uint8_t rxpayloadusedcount)
{
ASSERT_ERR((((uint32_t)rxpayloadusedcount << 16) & ~((uint32_t)0x00FF0000)) == 0);
REG_PL_WR(NXMAC_RX_TRIGGER_TIMER_ADDR, (REG_PL_RD(NXMAC_RX_TRIGGER_TIMER_ADDR) & ~((uint32_t)0x00FF0000)) | ((uint32_t)rxpayloadusedcount << 16));
}
/**
* @brief Returns the current value of the rxPacketTimeout field in the RX_TRIGGER_TIMER register.
*
* The RX_TRIGGER_TIMER register will be read and the rxPacketTimeout field's value will be returned.
*
* @return The current value of the rxPacketTimeout field in the RX_TRIGGER_TIMER register.
*/
__INLINE uint8_t nxmac_rx_packet_timeout_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_TRIGGER_TIMER_ADDR);
return ((localVal & ((uint32_t)0x0000FF00)) >> 8);
}
/**
* @brief Sets the rxPacketTimeout field of the RX_TRIGGER_TIMER register.
*
* The RX_TRIGGER_TIMER register will be read, modified to contain the new field value, and written.
*
* @param[in] rxpackettimeout - The value to set the field to.
*/
__INLINE void nxmac_rx_packet_timeout_setf(uint8_t rxpackettimeout)
{
ASSERT_ERR((((uint32_t)rxpackettimeout << 8) & ~((uint32_t)0x0000FF00)) == 0);
REG_PL_WR(NXMAC_RX_TRIGGER_TIMER_ADDR, (REG_PL_RD(NXMAC_RX_TRIGGER_TIMER_ADDR) & ~((uint32_t)0x0000FF00)) | ((uint32_t)rxpackettimeout << 8));
}
/**
* @brief Returns the current value of the rxAbsoluteTimeout field in the RX_TRIGGER_TIMER register.
*
* The RX_TRIGGER_TIMER register will be read and the rxAbsoluteTimeout field's value will be returned.
*
* @return The current value of the rxAbsoluteTimeout field in the RX_TRIGGER_TIMER register.
*/
__INLINE uint8_t nxmac_rx_absolute_timeout_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_RX_TRIGGER_TIMER_ADDR);
return ((localVal & ((uint32_t)0x000000FF)) >> 0);
}
/**
* @brief Sets the rxAbsoluteTimeout field of the RX_TRIGGER_TIMER register.
*
* The RX_TRIGGER_TIMER register will be read, modified to contain the new field value, and written.
*
* @param[in] rxabsolutetimeout - The value to set the field to.
*/
__INLINE void nxmac_rx_absolute_timeout_setf(uint8_t rxabsolutetimeout)
{
ASSERT_ERR((((uint32_t)rxabsolutetimeout << 0) & ~((uint32_t)0x000000FF)) == 0);
REG_PL_WR(NXMAC_RX_TRIGGER_TIMER_ADDR, (REG_PL_RD(NXMAC_RX_TRIGGER_TIMER_ADDR) & ~((uint32_t)0x000000FF)) | ((uint32_t)rxabsolutetimeout << 0));
}
/// @}
/**
* @name MIB_TABLE_WRITE register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:16 mibValue 0x0
* 15 mibWrite 0
* 14 mibIncrementMode 1
* 09:00 mibTableIndex 0x0
* </pre>
*
* @{
*/
/// Address of the MIB_TABLE_WRITE register
#define NXMAC_MIB_TABLE_WRITE_ADDR 0xC0000118
/// Offset of the MIB_TABLE_WRITE register from the base address
#define NXMAC_MIB_TABLE_WRITE_OFFSET 0x00000118
/// Index of the MIB_TABLE_WRITE register
#define NXMAC_MIB_TABLE_WRITE_INDEX 0x00000046
/// Reset value of the MIB_TABLE_WRITE register
#define NXMAC_MIB_TABLE_WRITE_RESET 0x00004000
/**
* @brief Returns the current value of the MIB_TABLE_WRITE register.
* The MIB_TABLE_WRITE register will be read and its value returned.
* @return The current value of the MIB_TABLE_WRITE register.
*/
__INLINE uint32_t nxmac_mib_table_write_get(void)
{
return REG_PL_RD(NXMAC_MIB_TABLE_WRITE_ADDR);
}
/**
* @brief Sets the MIB_TABLE_WRITE register to a value.
* The MIB_TABLE_WRITE register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_mib_table_write_set(uint32_t value)
{
REG_PL_WR(NXMAC_MIB_TABLE_WRITE_ADDR, value);
}
// field definitions
/// MIB_VALUE field mask
#define NXMAC_MIB_VALUE_MASK ((uint32_t)0xFFFF0000)
/// MIB_VALUE field LSB position
#define NXMAC_MIB_VALUE_LSB 16
/// MIB_VALUE field width
#define NXMAC_MIB_VALUE_WIDTH ((uint32_t)0x00000010)
/// MIB_WRITE field bit
#define NXMAC_MIB_WRITE_BIT ((uint32_t)0x00008000)
/// MIB_WRITE field position
#define NXMAC_MIB_WRITE_POS 15
/// MIB_INCREMENT_MODE field bit
#define NXMAC_MIB_INCREMENT_MODE_BIT ((uint32_t)0x00004000)
/// MIB_INCREMENT_MODE field position
#define NXMAC_MIB_INCREMENT_MODE_POS 14
/// MIB_TABLE_INDEX field mask
#define NXMAC_MIB_TABLE_INDEX_MASK ((uint32_t)0x000003FF)
/// MIB_TABLE_INDEX field LSB position
#define NXMAC_MIB_TABLE_INDEX_LSB 0
/// MIB_TABLE_INDEX field width
#define NXMAC_MIB_TABLE_INDEX_WIDTH ((uint32_t)0x0000000A)
/// MIB_VALUE field reset value
#define NXMAC_MIB_VALUE_RST 0x0
/// MIB_WRITE field reset value
#define NXMAC_MIB_WRITE_RST 0x0
/// MIB_INCREMENT_MODE field reset value
#define NXMAC_MIB_INCREMENT_MODE_RST 0x1
/// MIB_TABLE_INDEX field reset value
#define NXMAC_MIB_TABLE_INDEX_RST 0x0
/**
* @brief Constructs a value for the MIB_TABLE_WRITE register given values for its fields
* and writes the value to the register.
*
* @param[in] mibvalue - The value to use for the mibValue field.
* @param[in] mibwrite - The value to use for the mibWrite field.
* @param[in] mibincrementmode - The value to use for the mibIncrementMode field.
* @param[in] mibtableindex - The value to use for the mibTableIndex field.
*/
__INLINE void nxmac_mib_table_write_pack(uint16_t mibvalue, uint8_t mibwrite, uint8_t mibincrementmode, uint16_t mibtableindex)
{
ASSERT_ERR((((uint32_t)mibvalue << 16) & ~((uint32_t)0xFFFF0000)) == 0);
ASSERT_ERR((((uint32_t)mibwrite << 15) & ~((uint32_t)0x00008000)) == 0);
ASSERT_ERR((((uint32_t)mibincrementmode << 14) & ~((uint32_t)0x00004000)) == 0);
ASSERT_ERR((((uint32_t)mibtableindex << 0) & ~((uint32_t)0x000003FF)) == 0);
REG_PL_WR(NXMAC_MIB_TABLE_WRITE_ADDR, ((uint32_t)mibvalue << 16) | ((uint32_t)mibwrite << 15) | ((uint32_t)mibincrementmode << 14) | ((uint32_t)mibtableindex << 0));
}
/**
* @brief Unpacks MIB_TABLE_WRITE's fields from current value of the MIB_TABLE_WRITE register.
*
* Reads the MIB_TABLE_WRITE register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] mibvalue - Will be populated with the current value of this field from the register.
* @param[out] mibwrite - Will be populated with the current value of this field from the register.
* @param[out] mibincrementmode - Will be populated with the current value of this field from the register.
* @param[out] mibtableindex - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_mib_table_write_unpack(uint16_t *mibvalue, uint8_t *mibwrite, uint8_t *mibincrementmode, uint16_t *mibtableindex)
{
uint32_t localVal = REG_PL_RD(NXMAC_MIB_TABLE_WRITE_ADDR);
*mibvalue = (localVal & ((uint32_t)0xFFFF0000)) >> 16;
*mibwrite = (localVal & ((uint32_t)0x00008000)) >> 15;
*mibincrementmode = (localVal & ((uint32_t)0x00004000)) >> 14;
*mibtableindex = (localVal & ((uint32_t)0x000003FF)) >> 0;
}
/**
* @brief Returns the current value of the mibValue field in the MIB_TABLE_WRITE register.
*
* The MIB_TABLE_WRITE register will be read and the mibValue field's value will be returned.
*
* @return The current value of the mibValue field in the MIB_TABLE_WRITE register.
*/
__INLINE uint16_t nxmac_mib_value_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MIB_TABLE_WRITE_ADDR);
return ((localVal & ((uint32_t)0xFFFF0000)) >> 16);
}
/**
* @brief Sets the mibValue field of the MIB_TABLE_WRITE register.
*
* The MIB_TABLE_WRITE register will be read, modified to contain the new field value, and written.
*
* @param[in] mibvalue - The value to set the field to.
*/
__INLINE void nxmac_mib_value_setf(uint16_t mibvalue)
{
ASSERT_ERR((((uint32_t)mibvalue << 16) & ~((uint32_t)0xFFFF0000)) == 0);
REG_PL_WR(NXMAC_MIB_TABLE_WRITE_ADDR, (REG_PL_RD(NXMAC_MIB_TABLE_WRITE_ADDR) & ~((uint32_t)0xFFFF0000)) | ((uint32_t)mibvalue << 16));
}
/**
* @brief Returns the current value of the mibWrite field in the MIB_TABLE_WRITE register.
*
* The MIB_TABLE_WRITE register will be read and the mibWrite field's value will be returned.
*
* @return The current value of the mibWrite field in the MIB_TABLE_WRITE register.
*/
__INLINE uint8_t nxmac_mib_write_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MIB_TABLE_WRITE_ADDR);
return ((localVal & ((uint32_t)0x00008000)) >> 15);
}
/**
* @brief Sets the mibWrite field of the MIB_TABLE_WRITE register.
*
* The MIB_TABLE_WRITE register will be read, modified to contain the new field value, and written.
*
* @param[in] mibwrite - The value to set the field to.
*/
__INLINE void nxmac_mib_write_setf(uint8_t mibwrite)
{
ASSERT_ERR((((uint32_t)mibwrite << 15) & ~((uint32_t)0x00008000)) == 0);
REG_PL_WR(NXMAC_MIB_TABLE_WRITE_ADDR, (REG_PL_RD(NXMAC_MIB_TABLE_WRITE_ADDR) & ~((uint32_t)0x00008000)) | ((uint32_t)mibwrite << 15));
}
/**
* @brief Returns the current value of the mibIncrementMode field in the MIB_TABLE_WRITE register.
*
* The MIB_TABLE_WRITE register will be read and the mibIncrementMode field's value will be returned.
*
* @return The current value of the mibIncrementMode field in the MIB_TABLE_WRITE register.
*/
__INLINE uint8_t nxmac_mib_increment_mode_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MIB_TABLE_WRITE_ADDR);
return ((localVal & ((uint32_t)0x00004000)) >> 14);
}
/**
* @brief Sets the mibIncrementMode field of the MIB_TABLE_WRITE register.
*
* The MIB_TABLE_WRITE register will be read, modified to contain the new field value, and written.
*
* @param[in] mibincrementmode - The value to set the field to.
*/
__INLINE void nxmac_mib_increment_mode_setf(uint8_t mibincrementmode)
{
ASSERT_ERR((((uint32_t)mibincrementmode << 14) & ~((uint32_t)0x00004000)) == 0);
REG_PL_WR(NXMAC_MIB_TABLE_WRITE_ADDR, (REG_PL_RD(NXMAC_MIB_TABLE_WRITE_ADDR) & ~((uint32_t)0x00004000)) | ((uint32_t)mibincrementmode << 14));
}
/**
* @brief Returns the current value of the mibTableIndex field in the MIB_TABLE_WRITE register.
*
* The MIB_TABLE_WRITE register will be read and the mibTableIndex field's value will be returned.
*
* @return The current value of the mibTableIndex field in the MIB_TABLE_WRITE register.
*/
__INLINE uint16_t nxmac_mib_table_index_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MIB_TABLE_WRITE_ADDR);
return ((localVal & ((uint32_t)0x000003FF)) >> 0);
}
/**
* @brief Sets the mibTableIndex field of the MIB_TABLE_WRITE register.
*
* The MIB_TABLE_WRITE register will be read, modified to contain the new field value, and written.
*
* @param[in] mibtableindex - The value to set the field to.
*/
__INLINE void nxmac_mib_table_index_setf(uint16_t mibtableindex)
{
ASSERT_ERR((((uint32_t)mibtableindex << 0) & ~((uint32_t)0x000003FF)) == 0);
REG_PL_WR(NXMAC_MIB_TABLE_WRITE_ADDR, (REG_PL_RD(NXMAC_MIB_TABLE_WRITE_ADDR) & ~((uint32_t)0x000003FF)) | ((uint32_t)mibtableindex << 0));
}
/// @}
/**
* @name MONOTONIC_COUNTER_1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 monotonicCounter1 0x0
* </pre>
*
* @{
*/
/// Address of the MONOTONIC_COUNTER_1 register
#define NXMAC_MONOTONIC_COUNTER_1_ADDR 0xC000011C
/// Offset of the MONOTONIC_COUNTER_1 register from the base address
#define NXMAC_MONOTONIC_COUNTER_1_OFFSET 0x0000011C
/// Index of the MONOTONIC_COUNTER_1 register
#define NXMAC_MONOTONIC_COUNTER_1_INDEX 0x00000047
/// Reset value of the MONOTONIC_COUNTER_1 register
#define NXMAC_MONOTONIC_COUNTER_1_RESET 0x00000000
/**
* @brief Returns the current value of the MONOTONIC_COUNTER_1 register.
* The MONOTONIC_COUNTER_1 register will be read and its value returned.
* @return The current value of the MONOTONIC_COUNTER_1 register.
*/
__INLINE uint32_t nxmac_monotonic_counter_1_get(void)
{
return REG_PL_RD(NXMAC_MONOTONIC_COUNTER_1_ADDR);
}
// field definitions
/// MONOTONIC_COUNTER_1 field mask
#define NXMAC_MONOTONIC_COUNTER_1_MASK ((uint32_t)0xFFFFFFFF)
/// MONOTONIC_COUNTER_1 field LSB position
#define NXMAC_MONOTONIC_COUNTER_1_LSB 0
/// MONOTONIC_COUNTER_1 field width
#define NXMAC_MONOTONIC_COUNTER_1_WIDTH ((uint32_t)0x00000020)
/// MONOTONIC_COUNTER_1 field reset value
#define NXMAC_MONOTONIC_COUNTER_1_RST 0x0
/**
* @brief Returns the current value of the monotonicCounter1 field in the MONOTONIC_COUNTER_1 register.
*
* The MONOTONIC_COUNTER_1 register will be read and the monotonicCounter1 field's value will be returned.
*
* @return The current value of the monotonicCounter1 field in the MONOTONIC_COUNTER_1 register.
*/
__INLINE uint32_t nxmac_monotonic_counter_1_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MONOTONIC_COUNTER_1_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/// @}
/**
* @name MONOTONIC_COUNTER_2_LO register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 monotonicCounterLow2 0x0
* </pre>
*
* @{
*/
/// Address of the MONOTONIC_COUNTER_2_LO register
#define NXMAC_MONOTONIC_COUNTER_2_LO_ADDR 0xC0000120
/// Offset of the MONOTONIC_COUNTER_2_LO register from the base address
#define NXMAC_MONOTONIC_COUNTER_2_LO_OFFSET 0x00000120
/// Index of the MONOTONIC_COUNTER_2_LO register
#define NXMAC_MONOTONIC_COUNTER_2_LO_INDEX 0x00000048
/// Reset value of the MONOTONIC_COUNTER_2_LO register
#define NXMAC_MONOTONIC_COUNTER_2_LO_RESET 0x00000000
/**
* @brief Returns the current value of the MONOTONIC_COUNTER_2_LO register.
* The MONOTONIC_COUNTER_2_LO register will be read and its value returned.
* @return The current value of the MONOTONIC_COUNTER_2_LO register.
*/
__INLINE uint32_t nxmac_monotonic_counter_2_lo_get(void)
{
return REG_PL_RD(NXMAC_MONOTONIC_COUNTER_2_LO_ADDR);
}
/**
* @brief Sets the MONOTONIC_COUNTER_2_LO register to a value.
* The MONOTONIC_COUNTER_2_LO register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_monotonic_counter_2_lo_set(uint32_t value)
{
REG_PL_WR(NXMAC_MONOTONIC_COUNTER_2_LO_ADDR, value);
}
// field definitions
/// MONOTONIC_COUNTER_LOW_2 field mask
#define NXMAC_MONOTONIC_COUNTER_LOW_2_MASK ((uint32_t)0xFFFFFFFF)
/// MONOTONIC_COUNTER_LOW_2 field LSB position
#define NXMAC_MONOTONIC_COUNTER_LOW_2_LSB 0
/// MONOTONIC_COUNTER_LOW_2 field width
#define NXMAC_MONOTONIC_COUNTER_LOW_2_WIDTH ((uint32_t)0x00000020)
/// MONOTONIC_COUNTER_LOW_2 field reset value
#define NXMAC_MONOTONIC_COUNTER_LOW_2_RST 0x0
/**
* @brief Returns the current value of the monotonicCounterLow2 field in the MONOTONIC_COUNTER_2_LO register.
*
* The MONOTONIC_COUNTER_2_LO register will be read and the monotonicCounterLow2 field's value will be returned.
*
* @return The current value of the monotonicCounterLow2 field in the MONOTONIC_COUNTER_2_LO register.
*/
__INLINE uint32_t nxmac_monotonic_counter_low_2_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MONOTONIC_COUNTER_2_LO_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the monotonicCounterLow2 field of the MONOTONIC_COUNTER_2_LO register.
*
* The MONOTONIC_COUNTER_2_LO register will be read, modified to contain the new field value, and written.
*
* @param[in] monotoniccounterlow2 - The value to set the field to.
*/
__INLINE void nxmac_monotonic_counter_low_2_setf(uint32_t monotoniccounterlow2)
{
ASSERT_ERR((((uint32_t)monotoniccounterlow2 << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_MONOTONIC_COUNTER_2_LO_ADDR, (uint32_t)monotoniccounterlow2 << 0);
}
/// @}
/**
* @name MONOTONIC_COUNTER_2_HI register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31 monotonicCounter2SWUpdate 0
* 15:00 monotonicCounterHigh2 0x0
* </pre>
*
* @{
*/
/// Address of the MONOTONIC_COUNTER_2_HI register
#define NXMAC_MONOTONIC_COUNTER_2_HI_ADDR 0xC0000124
/// Offset of the MONOTONIC_COUNTER_2_HI register from the base address
#define NXMAC_MONOTONIC_COUNTER_2_HI_OFFSET 0x00000124
/// Index of the MONOTONIC_COUNTER_2_HI register
#define NXMAC_MONOTONIC_COUNTER_2_HI_INDEX 0x00000049
/// Reset value of the MONOTONIC_COUNTER_2_HI register
#define NXMAC_MONOTONIC_COUNTER_2_HI_RESET 0x00000000
/**
* @brief Returns the current value of the MONOTONIC_COUNTER_2_HI register.
* The MONOTONIC_COUNTER_2_HI register will be read and its value returned.
* @return The current value of the MONOTONIC_COUNTER_2_HI register.
*/
__INLINE uint32_t nxmac_monotonic_counter_2_hi_get(void)
{
return REG_PL_RD(NXMAC_MONOTONIC_COUNTER_2_HI_ADDR);
}
/**
* @brief Sets the MONOTONIC_COUNTER_2_HI register to a value.
* The MONOTONIC_COUNTER_2_HI register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_monotonic_counter_2_hi_set(uint32_t value)
{
REG_PL_WR(NXMAC_MONOTONIC_COUNTER_2_HI_ADDR, value);
}
// field definitions
/// MONOTONIC_COUNTER_2SW_UPDATE field bit
#define NXMAC_MONOTONIC_COUNTER_2SW_UPDATE_BIT ((uint32_t)0x80000000)
/// MONOTONIC_COUNTER_2SW_UPDATE field position
#define NXMAC_MONOTONIC_COUNTER_2SW_UPDATE_POS 31
/// MONOTONIC_COUNTER_HIGH_2 field mask
#define NXMAC_MONOTONIC_COUNTER_HIGH_2_MASK ((uint32_t)0x0000FFFF)
/// MONOTONIC_COUNTER_HIGH_2 field LSB position
#define NXMAC_MONOTONIC_COUNTER_HIGH_2_LSB 0
/// MONOTONIC_COUNTER_HIGH_2 field width
#define NXMAC_MONOTONIC_COUNTER_HIGH_2_WIDTH ((uint32_t)0x00000010)
/// MONOTONIC_COUNTER_2SW_UPDATE field reset value
#define NXMAC_MONOTONIC_COUNTER_2SW_UPDATE_RST 0x0
/// MONOTONIC_COUNTER_HIGH_2 field reset value
#define NXMAC_MONOTONIC_COUNTER_HIGH_2_RST 0x0
/**
* @brief Constructs a value for the MONOTONIC_COUNTER_2_HI register given values for its fields
* and writes the value to the register.
*
* @param[in] monotoniccounter2swupdate - The value to use for the monotonicCounter2SWUpdate field.
* @param[in] monotoniccounterhigh2 - The value to use for the monotonicCounterHigh2 field.
*/
__INLINE void nxmac_monotonic_counter_2_hi_pack(uint8_t monotoniccounter2swupdate, uint16_t monotoniccounterhigh2)
{
ASSERT_ERR((((uint32_t)monotoniccounter2swupdate << 31) & ~((uint32_t)0x80000000)) == 0);
ASSERT_ERR((((uint32_t)monotoniccounterhigh2 << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_MONOTONIC_COUNTER_2_HI_ADDR, ((uint32_t)monotoniccounter2swupdate << 31) | ((uint32_t)monotoniccounterhigh2 << 0));
}
/**
* @brief Unpacks MONOTONIC_COUNTER_2_HI's fields from current value of the MONOTONIC_COUNTER_2_HI register.
*
* Reads the MONOTONIC_COUNTER_2_HI register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] monotoniccounter2swupdate - Will be populated with the current value of this field from the register.
* @param[out] monotoniccounterhigh2 - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_monotonic_counter_2_hi_unpack(uint8_t *monotoniccounter2swupdate, uint16_t *monotoniccounterhigh2)
{
uint32_t localVal = REG_PL_RD(NXMAC_MONOTONIC_COUNTER_2_HI_ADDR);
*monotoniccounter2swupdate = (localVal & ((uint32_t)0x80000000)) >> 31;
*monotoniccounterhigh2 = (localVal & ((uint32_t)0x0000FFFF)) >> 0;
}
/**
* @brief Returns the current value of the monotonicCounter2SWUpdate field in the MONOTONIC_COUNTER_2_HI register.
*
* The MONOTONIC_COUNTER_2_HI register will be read and the monotonicCounter2SWUpdate field's value will be returned.
*
* @return The current value of the monotonicCounter2SWUpdate field in the MONOTONIC_COUNTER_2_HI register.
*/
__INLINE uint8_t nxmac_monotonic_counter_2sw_update_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MONOTONIC_COUNTER_2_HI_ADDR);
return ((localVal & ((uint32_t)0x80000000)) >> 31);
}
/**
* @brief Sets the monotonicCounter2SWUpdate field of the MONOTONIC_COUNTER_2_HI register.
*
* The MONOTONIC_COUNTER_2_HI register will be read, modified to contain the new field value, and written.
*
* @param[in] monotoniccounter2swupdate - The value to set the field to.
*/
__INLINE void nxmac_monotonic_counter_2sw_update_setf(uint8_t monotoniccounter2swupdate)
{
ASSERT_ERR((((uint32_t)monotoniccounter2swupdate << 31) & ~((uint32_t)0x80000000)) == 0);
REG_PL_WR(NXMAC_MONOTONIC_COUNTER_2_HI_ADDR, (REG_PL_RD(NXMAC_MONOTONIC_COUNTER_2_HI_ADDR) & ~((uint32_t)0x80000000)) | ((uint32_t)monotoniccounter2swupdate << 31));
}
/**
* @brief Returns the current value of the monotonicCounterHigh2 field in the MONOTONIC_COUNTER_2_HI register.
*
* The MONOTONIC_COUNTER_2_HI register will be read and the monotonicCounterHigh2 field's value will be returned.
*
* @return The current value of the monotonicCounterHigh2 field in the MONOTONIC_COUNTER_2_HI register.
*/
__INLINE uint16_t nxmac_monotonic_counter_high_2_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MONOTONIC_COUNTER_2_HI_ADDR);
return ((localVal & ((uint32_t)0x0000FFFF)) >> 0);
}
/**
* @brief Sets the monotonicCounterHigh2 field of the MONOTONIC_COUNTER_2_HI register.
*
* The MONOTONIC_COUNTER_2_HI register will be read, modified to contain the new field value, and written.
*
* @param[in] monotoniccounterhigh2 - The value to set the field to.
*/
__INLINE void nxmac_monotonic_counter_high_2_setf(uint16_t monotoniccounterhigh2)
{
ASSERT_ERR((((uint32_t)monotoniccounterhigh2 << 0) & ~((uint32_t)0x0000FFFF)) == 0);
REG_PL_WR(NXMAC_MONOTONIC_COUNTER_2_HI_ADDR, (REG_PL_RD(NXMAC_MONOTONIC_COUNTER_2_HI_ADDR) & ~((uint32_t)0x0000FFFF)) | ((uint32_t)monotoniccounterhigh2 << 0));
}
/// @}
/**
* @name ABS_TIMER register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 absTimerValue 0x0
* </pre>
*
* @{
*/
/// Address of the ABS_TIMER register
#define NXMAC_ABS_TIMER_ADDR 0xC0000128
/// Offset of the ABS_TIMER register from the base address
#define NXMAC_ABS_TIMER_OFFSET 0x00000128
/// Index of the ABS_TIMER register
#define NXMAC_ABS_TIMER_INDEX 0x0000004A
/// Reset value of the ABS_TIMER register
#define NXMAC_ABS_TIMER_RESET 0x00000000
/// Number of elements of the ABS_TIMER register array
#define NXMAC_ABS_TIMER_COUNT 10
/**
* @brief Returns the current value of the ABS_TIMER register.
* The ABS_TIMER register will be read and its value returned.
* @param[in] reg_idx Index of the register
* @return The current value of the ABS_TIMER register.
*/
__INLINE uint32_t nxmac_abs_timer_get(int reg_idx)
{
ASSERT_ERR(reg_idx <= 9);
return REG_PL_RD(NXMAC_ABS_TIMER_ADDR + reg_idx * 4);
}
/**
* @brief Sets the ABS_TIMER register to a value.
* The ABS_TIMER register will be written.
* @param[in] reg_idx Index of the register
* @param value - The value to write.
*/
__INLINE void nxmac_abs_timer_set(int reg_idx, uint32_t value)
{
ASSERT_ERR(reg_idx <= 9);
REG_PL_WR(NXMAC_ABS_TIMER_ADDR + reg_idx * 4, value);
}
// field definitions
/// ABS_TIMER_VALUE field mask
#define NXMAC_ABS_TIMER_VALUE_MASK ((uint32_t)0xFFFFFFFF)
/// ABS_TIMER_VALUE field LSB position
#define NXMAC_ABS_TIMER_VALUE_LSB 0
/// ABS_TIMER_VALUE field width
#define NXMAC_ABS_TIMER_VALUE_WIDTH ((uint32_t)0x00000020)
/// ABS_TIMER_VALUE field reset value
#define NXMAC_ABS_TIMER_VALUE_RST 0x0
/**
* @brief Returns the current value of the absTimerValue field in the ABS_TIMER register.
*
* The ABS_TIMER register will be read and the absTimerValue field's value will be returned.
*
* @param[in] reg_idx Index of the register
* @return The current value of the absTimerValue field in the ABS_TIMER register.
*/
__INLINE uint32_t nxmac_abs_timer_value_getf(int reg_idx)
{
ASSERT_ERR(reg_idx <= 9);
uint32_t localVal = REG_PL_RD(NXMAC_ABS_TIMER_ADDR + reg_idx * 4);
ASSERT_ERR((localVal & ~((uint32_t)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the absTimerValue field of the ABS_TIMER register.
*
* The ABS_TIMER register will be read, modified to contain the new field value, and written.
*
* @param[in] reg_idx Index of the register
* @param[in] abstimervalue - The value to set the field to.
*/
__INLINE void nxmac_abs_timer_value_setf(int reg_idx, uint32_t abstimervalue)
{
ASSERT_ERR(reg_idx <= 9);
ASSERT_ERR((((uint32_t)abstimervalue << 0) & ~((uint32_t)0xFFFFFFFF)) == 0);
REG_PL_WR(NXMAC_ABS_TIMER_ADDR + reg_idx * 4, (uint32_t)abstimervalue << 0);
}
/// @}
/**
* @name MAX_RX_LENGTH register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 19:00 maxAllowedLength 0xFFFF
* </pre>
*
* @{
*/
/// Address of the MAX_RX_LENGTH register
#define NXMAC_MAX_RX_LENGTH_ADDR 0xC0000150
/// Offset of the MAX_RX_LENGTH register from the base address
#define NXMAC_MAX_RX_LENGTH_OFFSET 0x00000150
/// Index of the MAX_RX_LENGTH register
#define NXMAC_MAX_RX_LENGTH_INDEX 0x00000054
/// Reset value of the MAX_RX_LENGTH register
#define NXMAC_MAX_RX_LENGTH_RESET 0x0000FFFF
/**
* @brief Returns the current value of the MAX_RX_LENGTH register.
* The MAX_RX_LENGTH register will be read and its value returned.
* @return The current value of the MAX_RX_LENGTH register.
*/
__INLINE uint32_t nxmac_max_rx_length_get(void)
{
return REG_PL_RD(NXMAC_MAX_RX_LENGTH_ADDR);
}
/**
* @brief Sets the MAX_RX_LENGTH register to a value.
* The MAX_RX_LENGTH register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_max_rx_length_set(uint32_t value)
{
REG_PL_WR(NXMAC_MAX_RX_LENGTH_ADDR, value);
}
// field definitions
/// MAX_ALLOWED_LENGTH field mask
#define NXMAC_MAX_ALLOWED_LENGTH_MASK ((uint32_t)0x000FFFFF)
/// MAX_ALLOWED_LENGTH field LSB position
#define NXMAC_MAX_ALLOWED_LENGTH_LSB 0
/// MAX_ALLOWED_LENGTH field width
#define NXMAC_MAX_ALLOWED_LENGTH_WIDTH ((uint32_t)0x00000014)
/// MAX_ALLOWED_LENGTH field reset value
#define NXMAC_MAX_ALLOWED_LENGTH_RST 0xFFFF
/**
* @brief Returns the current value of the maxAllowedLength field in the MAX_RX_LENGTH register.
*
* The MAX_RX_LENGTH register will be read and the maxAllowedLength field's value will be returned.
*
* @return The current value of the maxAllowedLength field in the MAX_RX_LENGTH register.
*/
__INLINE uint32_t nxmac_max_allowed_length_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_MAX_RX_LENGTH_ADDR);
ASSERT_ERR((localVal & ~((uint32_t)0x000FFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief Sets the maxAllowedLength field of the MAX_RX_LENGTH register.
*
* The MAX_RX_LENGTH register will be read, modified to contain the new field value, and written.
*
* @param[in] maxallowedlength - The value to set the field to.
*/
__INLINE void nxmac_max_allowed_length_setf(uint32_t maxallowedlength)
{
ASSERT_ERR((((uint32_t)maxallowedlength << 0) & ~((uint32_t)0x000FFFFF)) == 0);
REG_PL_WR(NXMAC_MAX_RX_LENGTH_ADDR, (uint32_t)maxallowedlength << 0);
}
/// @}
/**
* @name EDCA_AC_0 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 27:12 txOpLimit0 0x0
* 11:08 cwMax0 0xA
* 07:04 cwMin0 0x4
* 03:00 aifsn0 0x7
* </pre>
*
* @{
*/
/// Address of the EDCA_AC_0 register
#define NXMAC_EDCA_AC_0_ADDR 0xC0000200
/// Offset of the EDCA_AC_0 register from the base address
#define NXMAC_EDCA_AC_0_OFFSET 0x00000200
/// Index of the EDCA_AC_0 register
#define NXMAC_EDCA_AC_0_INDEX 0x00000080
/// Reset value of the EDCA_AC_0 register
#define NXMAC_EDCA_AC_0_RESET 0x00000A47
/**
* @brief Returns the current value of the EDCA_AC_0 register.
* The EDCA_AC_0 register will be read and its value returned.
* @return The current value of the EDCA_AC_0 register.
*/
__INLINE uint32_t nxmac_edca_ac_0_get(void)
{
return REG_PL_RD(NXMAC_EDCA_AC_0_ADDR);
}
/**
* @brief Sets the EDCA_AC_0 register to a value.
* The EDCA_AC_0 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_edca_ac_0_set(uint32_t value)
{
REG_PL_WR(NXMAC_EDCA_AC_0_ADDR, value);
}
// field definitions
/// TX_OP_LIMIT_0 field mask
#define NXMAC_TX_OP_LIMIT_0_MASK ((uint32_t)0x0FFFF000)
/// TX_OP_LIMIT_0 field LSB position
#define NXMAC_TX_OP_LIMIT_0_LSB 12
/// TX_OP_LIMIT_0 field width
#define NXMAC_TX_OP_LIMIT_0_WIDTH ((uint32_t)0x00000010)
/// CW_MAX_0 field mask
#define NXMAC_CW_MAX_0_MASK ((uint32_t)0x00000F00)
/// CW_MAX_0 field LSB position
#define NXMAC_CW_MAX_0_LSB 8
/// CW_MAX_0 field width
#define NXMAC_CW_MAX_0_WIDTH ((uint32_t)0x00000004)
/// CW_MIN_0 field mask
#define NXMAC_CW_MIN_0_MASK ((uint32_t)0x000000F0)
/// CW_MIN_0 field LSB position
#define NXMAC_CW_MIN_0_LSB 4
/// CW_MIN_0 field width
#define NXMAC_CW_MIN_0_WIDTH ((uint32_t)0x00000004)
/// AIFSN_0 field mask
#define NXMAC_AIFSN_0_MASK ((uint32_t)0x0000000F)
/// AIFSN_0 field LSB position
#define NXMAC_AIFSN_0_LSB 0
/// AIFSN_0 field width
#define NXMAC_AIFSN_0_WIDTH ((uint32_t)0x00000004)
/// TX_OP_LIMIT_0 field reset value
#define NXMAC_TX_OP_LIMIT_0_RST 0x0
/// CW_MAX_0 field reset value
#define NXMAC_CW_MAX_0_RST 0xA
/// CW_MIN_0 field reset value
#define NXMAC_CW_MIN_0_RST 0x4
/// AIFSN_0 field reset value
#define NXMAC_AIFSN_0_RST 0x7
/**
* @brief Constructs a value for the EDCA_AC_0 register given values for its fields
* and writes the value to the register.
*
* @param[in] txoplimit0 - The value to use for the txOpLimit0 field.
* @param[in] cwmax0 - The value to use for the cwMax0 field.
* @param[in] cwmin0 - The value to use for the cwMin0 field.
* @param[in] aifsn0 - The value to use for the aifsn0 field.
*/
__INLINE void nxmac_edca_ac_0_pack(uint16_t txoplimit0, uint8_t cwmax0, uint8_t cwmin0, uint8_t aifsn0)
{
ASSERT_ERR((((uint32_t)txoplimit0 << 12) & ~((uint32_t)0x0FFFF000)) == 0);
ASSERT_ERR((((uint32_t)cwmax0 << 8) & ~((uint32_t)0x00000F00)) == 0);
ASSERT_ERR((((uint32_t)cwmin0 << 4) & ~((uint32_t)0x000000F0)) == 0);
ASSERT_ERR((((uint32_t)aifsn0 << 0) & ~((uint32_t)0x0000000F)) == 0);
REG_PL_WR(NXMAC_EDCA_AC_0_ADDR, ((uint32_t)txoplimit0 << 12) | ((uint32_t)cwmax0 << 8) | ((uint32_t)cwmin0 << 4) | ((uint32_t)aifsn0 << 0));
}
/**
* @brief Unpacks EDCA_AC_0's fields from current value of the EDCA_AC_0 register.
*
* Reads the EDCA_AC_0 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] txoplimit0 - Will be populated with the current value of this field from the register.
* @param[out] cwmax0 - Will be populated with the current value of this field from the register.
* @param[out] cwmin0 - Will be populated with the current value of this field from the register.
* @param[out] aifsn0 - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_edca_ac_0_unpack(uint16_t *txoplimit0, uint8_t *cwmax0, uint8_t *cwmin0, uint8_t *aifsn0)
{
uint32_t localVal = REG_PL_RD(NXMAC_EDCA_AC_0_ADDR);
*txoplimit0 = (localVal & ((uint32_t)0x0FFFF000)) >> 12;
*cwmax0 = (localVal & ((uint32_t)0x00000F00)) >> 8;
*cwmin0 = (localVal & ((uint32_t)0x000000F0)) >> 4;
*aifsn0 = (localVal & ((uint32_t)0x0000000F)) >> 0;
}
/**
* @brief Returns the current value of the txOpLimit0 field in the EDCA_AC_0 register.
*
* The EDCA_AC_0 register will be read and the txOpLimit0 field's value will be returned.
*
* @return The current value of the txOpLimit0 field in the EDCA_AC_0 register.
*/
__INLINE uint16_t nxmac_tx_op_limit_0_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_EDCA_AC_0_ADDR);
return ((localVal & ((uint32_t)0x0FFFF000)) >> 12);
}
/**
* @brief Sets the txOpLimit0 field of the EDCA_AC_0 register.
*
* The EDCA_AC_0 register will be read, modified to contain the new field value, and written.
*
* @param[in] txoplimit0 - The value to set the field to.
*/
__INLINE void nxmac_tx_op_limit_0_setf(uint16_t txoplimit0)
{
ASSERT_ERR((((uint32_t)txoplimit0 << 12) & ~((uint32_t)0x0FFFF000)) == 0);
REG_PL_WR(NXMAC_EDCA_AC_0_ADDR, (REG_PL_RD(NXMAC_EDCA_AC_0_ADDR) & ~((uint32_t)0x0FFFF000)) | ((uint32_t)txoplimit0 << 12));
}
/**
* @brief Returns the current value of the cwMax0 field in the EDCA_AC_0 register.
*
* The EDCA_AC_0 register will be read and the cwMax0 field's value will be returned.
*
* @return The current value of the cwMax0 field in the EDCA_AC_0 register.
*/
__INLINE uint8_t nxmac_cw_max_0_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_EDCA_AC_0_ADDR);
return ((localVal & ((uint32_t)0x00000F00)) >> 8);
}
/**
* @brief Sets the cwMax0 field of the EDCA_AC_0 register.
*
* The EDCA_AC_0 register will be read, modified to contain the new field value, and written.
*
* @param[in] cwmax0 - The value to set the field to.
*/
__INLINE void nxmac_cw_max_0_setf(uint8_t cwmax0)
{
ASSERT_ERR((((uint32_t)cwmax0 << 8) & ~((uint32_t)0x00000F00)) == 0);
REG_PL_WR(NXMAC_EDCA_AC_0_ADDR, (REG_PL_RD(NXMAC_EDCA_AC_0_ADDR) & ~((uint32_t)0x00000F00)) | ((uint32_t)cwmax0 << 8));
}
/**
* @brief Returns the current value of the cwMin0 field in the EDCA_AC_0 register.
*
* The EDCA_AC_0 register will be read and the cwMin0 field's value will be returned.
*
* @return The current value of the cwMin0 field in the EDCA_AC_0 register.
*/
__INLINE uint8_t nxmac_cw_min_0_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_EDCA_AC_0_ADDR);
return ((localVal & ((uint32_t)0x000000F0)) >> 4);
}
/**
* @brief Sets the cwMin0 field of the EDCA_AC_0 register.
*
* The EDCA_AC_0 register will be read, modified to contain the new field value, and written.
*
* @param[in] cwmin0 - The value to set the field to.
*/
__INLINE void nxmac_cw_min_0_setf(uint8_t cwmin0)
{
ASSERT_ERR((((uint32_t)cwmin0 << 4) & ~((uint32_t)0x000000F0)) == 0);
REG_PL_WR(NXMAC_EDCA_AC_0_ADDR, (REG_PL_RD(NXMAC_EDCA_AC_0_ADDR) & ~((uint32_t)0x000000F0)) | ((uint32_t)cwmin0 << 4));
}
/**
* @brief Returns the current value of the aifsn0 field in the EDCA_AC_0 register.
*
* The EDCA_AC_0 register will be read and the aifsn0 field's value will be returned.
*
* @return The current value of the aifsn0 field in the EDCA_AC_0 register.
*/
__INLINE uint8_t nxmac_aifsn_0_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_EDCA_AC_0_ADDR);
return ((localVal & ((uint32_t)0x0000000F)) >> 0);
}
/**
* @brief Sets the aifsn0 field of the EDCA_AC_0 register.
*
* The EDCA_AC_0 register will be read, modified to contain the new field value, and written.
*
* @param[in] aifsn0 - The value to set the field to.
*/
__INLINE void nxmac_aifsn_0_setf(uint8_t aifsn0)
{
ASSERT_ERR((((uint32_t)aifsn0 << 0) & ~((uint32_t)0x0000000F)) == 0);
REG_PL_WR(NXMAC_EDCA_AC_0_ADDR, (REG_PL_RD(NXMAC_EDCA_AC_0_ADDR) & ~((uint32_t)0x0000000F)) | ((uint32_t)aifsn0 << 0));
}
/// @}
/**
* @name EDCA_AC_1 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 27:12 txOpLimit1 0x0
* 11:08 cwMax1 0xA
* 07:04 cwMin1 0x4
* 03:00 aifsn1 0x3
* </pre>
*
* @{
*/
/// Address of the EDCA_AC_1 register
#define NXMAC_EDCA_AC_1_ADDR 0xC0000204
/// Offset of the EDCA_AC_1 register from the base address
#define NXMAC_EDCA_AC_1_OFFSET 0x00000204
/// Index of the EDCA_AC_1 register
#define NXMAC_EDCA_AC_1_INDEX 0x00000081
/// Reset value of the EDCA_AC_1 register
#define NXMAC_EDCA_AC_1_RESET 0x00000A43
/**
* @brief Returns the current value of the EDCA_AC_1 register.
* The EDCA_AC_1 register will be read and its value returned.
* @return The current value of the EDCA_AC_1 register.
*/
__INLINE uint32_t nxmac_edca_ac_1_get(void)
{
return REG_PL_RD(NXMAC_EDCA_AC_1_ADDR);
}
/**
* @brief Sets the EDCA_AC_1 register to a value.
* The EDCA_AC_1 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_edca_ac_1_set(uint32_t value)
{
REG_PL_WR(NXMAC_EDCA_AC_1_ADDR, value);
}
// field definitions
/// TX_OP_LIMIT_1 field mask
#define NXMAC_TX_OP_LIMIT_1_MASK ((uint32_t)0x0FFFF000)
/// TX_OP_LIMIT_1 field LSB position
#define NXMAC_TX_OP_LIMIT_1_LSB 12
/// TX_OP_LIMIT_1 field width
#define NXMAC_TX_OP_LIMIT_1_WIDTH ((uint32_t)0x00000010)
/// CW_MAX_1 field mask
#define NXMAC_CW_MAX_1_MASK ((uint32_t)0x00000F00)
/// CW_MAX_1 field LSB position
#define NXMAC_CW_MAX_1_LSB 8
/// CW_MAX_1 field width
#define NXMAC_CW_MAX_1_WIDTH ((uint32_t)0x00000004)
/// CW_MIN_1 field mask
#define NXMAC_CW_MIN_1_MASK ((uint32_t)0x000000F0)
/// CW_MIN_1 field LSB position
#define NXMAC_CW_MIN_1_LSB 4
/// CW_MIN_1 field width
#define NXMAC_CW_MIN_1_WIDTH ((uint32_t)0x00000004)
/// AIFSN_1 field mask
#define NXMAC_AIFSN_1_MASK ((uint32_t)0x0000000F)
/// AIFSN_1 field LSB position
#define NXMAC_AIFSN_1_LSB 0
/// AIFSN_1 field width
#define NXMAC_AIFSN_1_WIDTH ((uint32_t)0x00000004)
/// TX_OP_LIMIT_1 field reset value
#define NXMAC_TX_OP_LIMIT_1_RST 0x0
/// CW_MAX_1 field reset value
#define NXMAC_CW_MAX_1_RST 0xA
/// CW_MIN_1 field reset value
#define NXMAC_CW_MIN_1_RST 0x4
/// AIFSN_1 field reset value
#define NXMAC_AIFSN_1_RST 0x3
/**
* @brief Constructs a value for the EDCA_AC_1 register given values for its fields
* and writes the value to the register.
*
* @param[in] txoplimit1 - The value to use for the txOpLimit1 field.
* @param[in] cwmax1 - The value to use for the cwMax1 field.
* @param[in] cwmin1 - The value to use for the cwMin1 field.
* @param[in] aifsn1 - The value to use for the aifsn1 field.
*/
__INLINE void nxmac_edca_ac_1_pack(uint16_t txoplimit1, uint8_t cwmax1, uint8_t cwmin1, uint8_t aifsn1)
{
ASSERT_ERR((((uint32_t)txoplimit1 << 12) & ~((uint32_t)0x0FFFF000)) == 0);
ASSERT_ERR((((uint32_t)cwmax1 << 8) & ~((uint32_t)0x00000F00)) == 0);
ASSERT_ERR((((uint32_t)cwmin1 << 4) & ~((uint32_t)0x000000F0)) == 0);
ASSERT_ERR((((uint32_t)aifsn1 << 0) & ~((uint32_t)0x0000000F)) == 0);
REG_PL_WR(NXMAC_EDCA_AC_1_ADDR, ((uint32_t)txoplimit1 << 12) | ((uint32_t)cwmax1 << 8) | ((uint32_t)cwmin1 << 4) | ((uint32_t)aifsn1 << 0));
}
/**
* @brief Unpacks EDCA_AC_1's fields from current value of the EDCA_AC_1 register.
*
* Reads the EDCA_AC_1 register and populates all the _field variables with the corresponding
* values from the register.
*
* @param[out] txoplimit1 - Will be populated with the current value of this field from the register.
* @param[out] cwmax1 - Will be populated with the current value of this field from the register.
* @param[out] cwmin1 - Will be populated with the current value of this field from the register.
* @param[out] aifsn1 - Will be populated with the current value of this field from the register.
*/
__INLINE void nxmac_edca_ac_1_unpack(uint16_t *txoplimit1, uint8_t *cwmax1, uint8_t *cwmin1, uint8_t *aifsn1)
{
uint32_t localVal = REG_PL_RD(NXMAC_EDCA_AC_1_ADDR);
*txoplimit1 = (localVal & ((uint32_t)0x0FFFF000)) >> 12;
*cwmax1 = (localVal & ((uint32_t)0x00000F00)) >> 8;
*cwmin1 = (localVal & ((uint32_t)0x000000F0)) >> 4;
*aifsn1 = (localVal & ((uint32_t)0x0000000F)) >> 0;
}
/**
* @brief Returns the current value of the txOpLimit1 field in the EDCA_AC_1 register.
*
* The EDCA_AC_1 register will be read and the txOpLimit1 field's value will be returned.
*
* @return The current value of the txOpLimit1 field in the EDCA_AC_1 register.
*/
__INLINE uint16_t nxmac_tx_op_limit_1_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_EDCA_AC_1_ADDR);
return ((localVal & ((uint32_t)0x0FFFF000)) >> 12);
}
/**
* @brief Sets the txOpLimit1 field of the EDCA_AC_1 register.
*
* The EDCA_AC_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] txoplimit1 - The value to set the field to.
*/
__INLINE void nxmac_tx_op_limit_1_setf(uint16_t txoplimit1)
{
ASSERT_ERR((((uint32_t)txoplimit1 << 12) & ~((uint32_t)0x0FFFF000)) == 0);
REG_PL_WR(NXMAC_EDCA_AC_1_ADDR, (REG_PL_RD(NXMAC_EDCA_AC_1_ADDR) & ~((uint32_t)0x0FFFF000)) | ((uint32_t)txoplimit1 << 12));
}
/**
* @brief Returns the current value of the cwMax1 field in the EDCA_AC_1 register.
*
* The EDCA_AC_1 register will be read and the cwMax1 field's value will be returned.
*
* @return The current value of the cwMax1 field in the EDCA_AC_1 register.
*/
__INLINE uint8_t nxmac_cw_max_1_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_EDCA_AC_1_ADDR);
return ((localVal & ((uint32_t)0x00000F00)) >> 8);
}
/**
* @brief Sets the cwMax1 field of the EDCA_AC_1 register.
*
* The EDCA_AC_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] cwmax1 - The value to set the field to.
*/
__INLINE void nxmac_cw_max_1_setf(uint8_t cwmax1)
{
ASSERT_ERR((((uint32_t)cwmax1 << 8) & ~((uint32_t)0x00000F00)) == 0);
REG_PL_WR(NXMAC_EDCA_AC_1_ADDR, (REG_PL_RD(NXMAC_EDCA_AC_1_ADDR) & ~((uint32_t)0x00000F00)) | ((uint32_t)cwmax1 << 8));
}
/**
* @brief Returns the current value of the cwMin1 field in the EDCA_AC_1 register.
*
* The EDCA_AC_1 register will be read and the cwMin1 field's value will be returned.
*
* @return The current value of the cwMin1 field in the EDCA_AC_1 register.
*/
__INLINE uint8_t nxmac_cw_min_1_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_EDCA_AC_1_ADDR);
return ((localVal & ((uint32_t)0x000000F0)) >> 4);
}
/**
* @brief Sets the cwMin1 field of the EDCA_AC_1 register.
*
* The EDCA_AC_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] cwmin1 - The value to set the field to.
*/
__INLINE void nxmac_cw_min_1_setf(uint8_t cwmin1)
{
ASSERT_ERR((((uint32_t)cwmin1 << 4) & ~((uint32_t)0x000000F0)) == 0);
REG_PL_WR(NXMAC_EDCA_AC_1_ADDR, (REG_PL_RD(NXMAC_EDCA_AC_1_ADDR) & ~((uint32_t)0x000000F0)) | ((uint32_t)cwmin1 << 4));
}
/**
* @brief Returns the current value of the aifsn1 field in the EDCA_AC_1 register.
*
* The EDCA_AC_1 register will be read and the aifsn1 field's value will be returned.
*
* @return The current value of the aifsn1 field in the EDCA_AC_1 register.
*/
__INLINE uint8_t nxmac_aifsn_1_getf(void)
{
uint32_t localVal = REG_PL_RD(NXMAC_EDCA_AC_1_ADDR);
return ((localVal & ((uint32_t)0x0000000F)) >> 0);
}
/**
* @brief Sets the aifsn1 field of the EDCA_AC_1 register.
*
* The EDCA_AC_1 register will be read, modified to contain the new field value, and written.
*
* @param[in] aifsn1 - The value to set the field to.
*/
__INLINE void nxmac_aifsn_1_setf(uint8_t aifsn1)
{
ASSERT_ERR((((uint32_t)aifsn1 << 0) & ~((uint32_t)0x0000000F)) == 0);
REG_PL_WR(NXMAC_EDCA_AC_1_ADDR, (REG_PL_RD(NXMAC_EDCA_AC_1_ADDR) & ~((uint32_t)0x0000000F)) | ((uint32_t)aifsn1 << 0));
}
/// @}
/**
* @name EDCA_AC_2 register definitions
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 27:12 txOpLimit2 0x5E
* 11:08 cwMax2 0x4
* 07:04 cwMin2 0x3
* 03:00 aifsn2 0x2
* </pre>
*
* @{
*/
/// Address of the EDCA_AC_2 register
#define NXMAC_EDCA_AC_2_ADDR 0xC0000208
/// Offset of the EDCA_AC_2 register from the base address
#define NXMAC_EDCA_AC_2_OFFSET 0x00000208
/// Index of the EDCA_AC_2 register
#define NXMAC_EDCA_AC_2_INDEX 0x00000082
/// Reset value of the EDCA_AC_2 register
#define NXMAC_EDCA_AC_2_RESET 0x0005E432
/**
* @brief Returns the current value of the EDCA_AC_2 register.
* The EDCA_AC_2 register will be read and its value returned.
* @return The current value of the EDCA_AC_2 register.
*/
__INLINE uint32_t nxmac_edca_ac_2_get(void)
{
return REG_PL_RD(NXMAC_EDCA_AC_2_ADDR);
}
/**
* @brief Sets the EDCA_AC_2 register to a value.
* The EDCA_AC_2 register will be written.
* @param value - The value to write.
*/
__INLINE void nxmac_edca_ac_2_set(uint32_t value)
{
REG_PL_WR(NXMAC_EDCA_AC_2_ADDR, value);
}
/
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