Other way for a CPU inspired on the TR3200

Changes on TR3200 branch and flags mode.md

%flags now not are a GPR. Now is a internal hidden register. Status stuff like interrupts are now there accessed by special instructions for it. JMP.cc and IF.cc can read arithmetic flags on it. Chaining IFs disappears.

New &renamed instructions :

GET/SET_INT Rn : Get/Set Interrupt flag (to Enable/Disable interrupts)

GET/SET_SS Rn : Get/Set Single Step mode (to Enable/Disable single step mode)

GET/CLR_DIVERR Rn : Get/Clear Division Error flag.

CMP Rd, Rn : Do comparison, ie SUB Rd, Rn but not sets Rd with the result of subtraction. Only sets %flags

IFXX by IF.cc : Acts like a prefix instead as proper instructions. Now, not accepts any parameter as CMP sets the flags. Adds one extra cycle to the next instruction. Assemblers should have an alias for instructions like ADD.cc Rd, Rs, Rn = IF.cc ADD Rd, Rs, Rn , or JMP.cc = IF.cc ADD Rd, Rs, Rn . Also, IF.cc prefix should have a copy of M and L bits of the prefixed instruction, to allow to be only 2 cycles if it fails.

Example of usage :

Cycle count assuming %r0 = ';' and %r8 being = EXAM_MODE

Old code with the old datapath ,12 instructions -> 4+1+4+1+4+1+3+3+3 = 24 cycles :

    IFEQ %r0, ' '
      IFEQ %r8, MODE_EXAM
        JMP MONITOR_NEW_LADDR

    IFEQ %r0, ' '
      IFEQ %r8, MODE_STORE
        JMP MONITOR_WRITEVAL

    IFEQ %r0, '.'
      IFEQ %r8, MODE_EXAM        ; Only if is in Examination mode
        JMP MONITOR_CHMODE_BEXAM  ; Changes to block examine mode

    IFEQ %r0, ':'
      IFEQ %r8, MODE_EXAM        ; Only if is in Examination mode
        JMP MONITOR_CHMODE_STORE  ; Changes to store mode

New code with the new datapath ,12 instructions, -> 3+3+3+2+3+2+3+3 = 22 cycles :

    CMP %r0, ' '
    JMP.NEQ MONITOR_CHECK_IF_EXAM_MODE
    
    CMP %r8, MODE_EXAM
    JMP.EQ MONITOR_NEW_LADDR
    
    CMP %r8, MODE_STORE
    JMP.EQ MONITOR_WRITEVAL
    
    MONITOR_CHECK_IF_EXAM_MODE:
    CMP %r8, MODE_EXAM
    JMP.NEQ MONITOR_END_STUFF
    
    CMP %r0, '.'                      ; Block Examination command
    JMP.EQ MONITOR_CHMODE_BEXAM       ; Change to block examine mode 
    
    CMP %r0, ';'                      ; Write data command
    JMP.EQ MONITOR_CHMODE_STORE       ; hanges to write data mode 

    MONITOR_END_STUFF:

CPU datapath.md

We could take a simple stage model like ARM Cortex-M3 , ie 3 stages model : Fetch, Decode and Execute.

Fetch only reads 4 bytes from RAM, to take the instruction and increases PC.

Decode, decodes an instruction and :

• Fetch next 4 bytes without increasing the PC
• If is prefix IF.cc, checks the condition and increases PC by 4.
  • If the condition is true, calls again the Decode stage using the fetch on Decode as instruction to be processed.
  • If the condition is false, don't call the Execute stage.
• Sets input/output registers

Execute stage, well... executes it and writes to the output. If is a JMP or CALL instruction, obviously would overwrite PC register value.

Interrupt checking is doing on Fetch stage, before anything.