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/////////////////////////////////////////////////////////////////////////////// | |
// | |
// Filename: cputest.c | |
// | |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core | |
// | |
// Purpose: To test the CPU, it's instructions, cache, and pipeline, to make | |
// certain that it works. This includes testing that each of the | |
// instructions works, as well as any strange instruction combinations. | |
// |
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asm("\t.section\t.start\n" | |
"\t.global\t_start\n" | |
"\t.type\t_start,@function\n" | |
"_start:\n" | |
"\tLDI\t_top_of_stack,SP\n" | |
"\tBRA\tentry\n" | |
"\t.section\t.text"); | |
#define INT_RTC 0x002 | |
#define INT_FLASH 0x004 |
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/******************************************************************************* | |
* | |
* Filename: xula.ld | |
* | |
* Project: XuLA2-LX25 SoC | |
* | |
* Purpose: This script provides a description of the XuLA2-LX25 SoC, | |
* and specifically the memory bus that the Zip CPU would see, | |
* for the purposes of where to place memory when linking. | |
* |
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/////////////////////////////////////////////////////////////////////////////// | |
// | |
// Filename: cputest.c | |
// | |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core | |
// | |
// Purpose: To test the CPU, it's instructions, cache, and pipeline, to make | |
// certain that it works. This includes testing that each of the | |
// instructions works, as well as any strange instruction combinations. | |
// |
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<student> Yes I am | |
<ZipCPU> You asked a question on ##verilog some time ago, and then left before I noticed and answered the question. | |
<ZipCPU> I wanted to make certain you were on line before I commented on any of your issues. | |
<ZipCPU> Further, because the ##fpga discussion is struggling to handle about 3 topics at once, I thought it might be simpler to leave the discussion channel. | |
<student> Yea that's right, I left before receiving any answers, I waited a lot but none answered. | |
<ZipCPU> You were asking some fascinating questions on ##fpga. | |
<ZipCPU> May I try my hand at answering any of them? | |
<student> Yea sure, I would be too thankful for that as I'm starting my way in digital design and I have multiple issues that I didn't find answer on edaboard forums, and IRC as well! | |
<ZipCPU> So ... I started digital design in earnest almost two years ago. In many ways, I'm a newbie. On the other hand, I do have a graduate degree in computer engineering, so ... I might know a thing or two ... | |
<ZipCPU> At one time, |
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//////////////////////////////////////////////////////////////////////////////// | |
// | |
// Filename: testb.h | |
// | |
// Project: Zip CPU -- a small, lightweight, RISC CPU core | |
// | |
// Purpose: A wrapper for a common interface to a clocked FPGA core | |
// begin exercised in Verilator. | |
// | |
// Creator: Dan Gisselquist, Ph.D. |
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///////////////////////////////////////////////////////////////////////////// | |
// | |
// Filename: mpygen.cpp | |
// | |
// Project: A simple, better, multiply generator | |
// | |
// Purpose: This is the product of studying the signed, two's complement, | |
// multiply operation presented on wikipedia, | |
// | |
// http://en.wikipedia.org/wiki/Binary_multiplier |
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//////////////////////////////////////////////////////////////////// | |
// | |
// Filename: string.c | |
// | |
// Project: CMod S6 System on a Chip, ZipCPU demonstration project | |
// | |
// Purpose: To provide *some* of the C-library's capabilities, without | |
// using perfectly optimal functions--but rather simple things that | |
// can be easily tested and debugged. | |
// |
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//////////////////////////////////////////////////////////////////////////////// | |
// | |
// Filename: div.v | |
// | |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core | |
// | |
// Purpose: Provide an Integer divide capability to the Zip CPU. Provides | |
// for both signed and unsigned divide. | |
// | |
// Steps: |
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/////////////////////////////////////////////////////////////////////////// | |
// | |
// Filename: sgnmpy_16x16.v | |
// | |
// Project: A simple, better, multiply generator | |
// | |
// Purpose: This verilog file multiplies two numbers together, without | |
// using any hardware acceleration. The file itself is | |
// computer generated, so please (for your sake) don't | |
// make any edits to the file lest you regenerate it and |
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