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Dan Gisselquist ZipCPU

  • Gisselquist Technology, LLC
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View CPU Test
Running CPU self-test
SIM Instructions Is this a simulator?
CIS Instructions Supported
Break test #1 Pass
Break test #2 Pass
Break test #3 Pass
Early Branch test Pass
Trap test/AND Pass
Trap test/CLR Pass
View blk0wrapper.sby
prf: mode prove
cvr: mode cover
prf: depth 40
cvr: depth 40
View tb.v
`timescale 1ns / 1ns
// Company:
// Engineer:
// Create Date: 16.04.2021 13:39:07
// Design Name:
// Module Name: sim
// Project Name:
// Target Devices:
View equiripple_mband.cpp
// ntaps: the number of filter coefficients
// M: Every Mth coefficient will be zero, this is the "M"
// in M-band
// fp: Filter's passband cutoff. Can be zero.
LPFIRLITE equiripple_halfband_fl(int ntaps, const int M,
const double fp) {
// Assume that our filters will always have odd length
ntaps = (ntaps & 1) ? ntaps : ntaps-1;
int L;
View mybits.sby
mode prove
depth 2
ZipCPU / axi_regs_top.sby
Created October 16, 2020 22:37
Verified AXI-lite slave design
View axi_regs_top.sby
## Here's the SymbiYosys script we used for this task
prf: mode prove
prf: depth 4
cvr: mode cover
View cicfil.v
// Filename: cicfil.v
// Project: SDR, a basic Soft(Gate)ware Defined Radio architecture
// Purpose: Perform some number of CIC integrate and dump stages, followed
// by a downsample by half the number of averages given. Hence,
// if we integrate 4 samples and output, we'll downsample by two (4 / 2).
View wbmotor.v
initial counts = 0;
always @(posedge i_clk)
if (i_reset)
// Tare the counter by setting it to zero on any reset
counts <= 0;
else begin
case({lst_a, lst_b, ck_a, ck_b})
4'h1: counts <= counts + 1'b1;
4'h7: counts <= counts + 1'b1;
4'he: counts <= counts + 1'b1;
View walker.sby
cvr: mode cover
multiclock on
depth 360
View pp2stb.v
module pps2tb;
reg [3:0] counter;
reg clk;
reg o_led;
initial clk = 0;
always @(*)
clk <= #5 !clk;
initial counter = 0;