ZipCPU

module vtb;
	reg	clk, d, q;

	initial	clk = 0;
	always @(*)
		clk <= #5 !clk;

	always @(posedge clk)
		q <= d;

ZipCPU

// This is the core as it was originally given to me, and without any modifications
//
//
module wb2axi
  (
   input wire 	      i_clk,
   input wire 	      i_rst,
   input wire [31:0]  i_wb_adr,
   input wire [31:0]  i_wb_dat,
   input wire [3:0]   i_wb_sel,

ZipCPU

[tasks]
prf
cvr

[options]
prf: mode prove
prf: depth 17
cvr: mode cover
cvr: depth 60
multiclock on

ZipCPU

////////////////////////////////////////////////////////////////////////////////
//
// Filename:	fwb_slave.v
//
// Project:	Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:	This file describes the rules of a wishbone interaction from the
//		perspective of a wishbone slave.  These formal rules may be used
//	with yosys-smtbmc to *prove* that the slave properly handles outgoing
//	responses to (assumed correct) incoming requests.

ZipCPU

// Here's the goal: imagine you have a return from a set of values.
// One of those data returns will set the i_valid line high.  In that
// case, we want to return the corresponding bit.  Hence, if i_valid[N],
// for any N, then the output should always be i_data[N] and the output
// valid signal should also be high.
//
// The goal:
//	1. How low can you get the logic for such a design.
//	2. Can you make the code to do that generic
//

ZipCPU

//
// This example was provided by Clifford Wolf
//
module foo;
        parameter X = 9;
        initial begin
                if (X % 3 != 0) begin
                        $display("Parameter X in %m must be divisible by 3! Value %d is not.", X);
                        $stop;
                end

ZipCPU

module miter (
	input        i_clk,
	input        i_reset,
	input        i_tap_wr,
	input [11:0] i_tap,
	input        i_ce,
	input [11:0] i_sample
);
	wire [30:0] ref_result;
	wire [30:0] uut_result;

ZipCPU

////////////////////////////////////////////////////////////////////////////////
//
// Filename: 	wbxbar.v
//
// Project:	AutoFPGA, a utility for composing FPGA designs from peripherals
//
// Purpose:	A configurable wishbone cross-bar
//
// Creator:	Dan Gisselquist, Ph.D.
//		Gisselquist Technology, LLC

ZipCPU

always @(posedge i_clk)
begin
tb_0_0_0 <= i_a[0]&i_b[0];
tb_0_1_1 <= i_a[0]&i_b[1];
tb_0_2_2 <= i_a[0]&i_b[2];
tb_0_3_3 <= i_a[0]&i_b[3];
tb_0_4_4 <= i_a[0]&i_b[4];
tb_0_5_5 <= i_a[0]&i_b[5];
tb_0_6_6 <= i_a[0]&i_b[6];
tb_0_7_7 <= i_a[0]&i_b[7];

ZipCPU

`timescale 1ns / 1ps
`default_nettype	none
// Module which sends the total calculated output signal to the PmodI2S
// stereo audio output device
module pmod_out(sig, i_clk, o_i2s_mclk, o_i2s_lrclk, o_i2s_sclk, o_i2s_sdin);
    input [15:0] sig;
    input wire	i_clk;      // 500MHz clock
    output reg	o_i2s_mclk;    // Master clock to send to PmodI2S to maintain
                    // synchronization
    output reg	o_i2s_lrclk;   // Left-right clock stereo audio output