Stopping on bad parameters

//
// This example was provided by Clifford Wolf
//
module foo;
        parameter X = 9;
        initial begin
                if (X % 3 != 0) begin
                        $display("Parameter X in %m must be divisible by 3! Value %d is not.", X);
                        $stop;
                end
        end
endmodule

module top;
        foo #(.X(7)) bar ();
endmodule

This doesn't seem to error?

-- Parsing `temp.v' using frontend `verilog' --

1. Executing Verilog-2005 frontend.
Parsing Verilog input from `temp.v' to AST representation.
Generating RTLIL representation for module `\foo'.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

End of script. Logfile hash: 453372dc88
CPU: user 0.00s system 0.01s, MEM: 23.12 MB total, 7.41 MB resident
Time spent: 100% 1x read_verilog (0 sec)

The error is created when the code is elaborated. Go ahead and run hierarchy and it will die. hierarchy is the first command within prep, proc, synth, synth_xilinx, synth_ice40, synth_ecp5, etc.