vtb.v

module vtb;
	reg	clk, d, q;

	initial	clk = 0;
	always @(*)
		clk <= #5 !clk;

	always @(posedge clk)
		q <= d;

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(0,vtb);

		d = 0;
		@(posedge clk);
		d = 1;
		@(posedge clk);
		d = 0;
		@(posedge clk);
		d = 1;
		@(posedge clk);
		d = 0;
		@(posedge clk);
		d = 1;
		@(posedge clk);
		d = 0;
		@(posedge clk);
		d = 1;
	end

	reg	[4:0]	counter = 0;
	always @(posedge clk)
	begin
		counter <= counter + 1;
		if (counter > 20)
		begin
			$display("All done\n");
			$finish;
		end
	end

endmodule