tb.v

`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16.04.2021 13:39:07
// Design Name:
// Module Name: sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//
//
//
// FFT Generated via:
//
//  fftgen -f 16 -n 5 -m 5
//
module test(

);

reg [4:0] Arr [15:0];

initial	begin
	Arr[ 0] = 5'b00000;
	Arr[ 1] = 5'b00011;
	Arr[ 2] = 5'b00100;
	Arr[ 3] = 5'b00011; 
	Arr[ 4] = 5'b00000;
	Arr[ 5] = 5'b11101;
	Arr[ 6] = 5'b11100;
	Arr[ 7] = 5'b11101;
	Arr[ 8] = 5'b00000;
	Arr[ 9] = 5'b00011;
	Arr[10] = 5'b00100;
	Arr[11] = 5'b00011; 
	Arr[12] = 5'b00000;
	Arr[13] = 5'b11101;
	Arr[14] = 5'b11100;
	Arr[15] = 5'b11101;
end

	//Inputs

	reg clk = 0;
	reg rst = 0;
	reg i_ce = 0;
	wire [9:0] i_sample;
	//Outputs
	wire [9:0] o_result;
	wire o_sync;

	//Test

	fftmain uut (
		.i_clk(clk),
		.i_reset(rst),
		.i_ce(i_ce),
		.i_sample(i_sample),
		//Outputs
		.o_result(o_result),
		.o_sync(o_sync)
	);

	reg [4:0] adc_reg;
	reg [3:0] i = 0;

	always @(posedge clk)
	if (rst)
	begin
		adc_reg <= 5'b0;
		i <= 0;
	end else begin
		adc_reg <= Arr[i];
		i <= i+1;
	end

	assign i_sample = {adc_reg,5'b00000};

	initial begin
		$dumpfile("dump.vcd");
		$dumpvars(0,test);

		clk  = 0;
		rst  = 1;
		i_ce = 0;
		@(posedge clk);
		rst <= 0;
		@(posedge clk);
		i_ce <= 1;
		@(posedge clk);
	end

	always #1 clk = ~clk;

endmodule