ZipCPU

///////////////////////////////////////////////////////////////////////////////
//
// Filename:	cputest.c
//
// Project:	Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:	To test the CPU, it's instructions, cache, and pipeline, to make
//		certain that it works.  This includes testing that each of the
//	instructions works, as well as any strange instruction combinations.
//

ZipCPU

asm("\t.section\t.start\n"
	"\t.global\t_start\n"
	"\t.type\t_start,@function\n"
	"_start:\n"
	"\tLDI\t_top_of_stack,SP\n"
	"\tBRA\tentry\n"
	"\t.section\t.text");

#define	INT_RTC		0x002
#define	INT_FLASH	0x004

ZipCPU

/*******************************************************************************
*
* Filename:	xula.ld
*
* Project:	XuLA2-LX25 SoC
*
* Purpose:	This script provides a description of the XuLA2-LX25 SoC,
* 		and specifically the memory bus that the Zip CPU would see,
*		for the purposes of where to place memory when linking.
*

ZipCPU

///////////////////////////////////////////////////////////////////////////////
//
// Filename:	cputest.c
//
// Project:	Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:	To test the CPU, it's instructions, cache, and pipeline, to make
//		certain that it works.  This includes testing that each of the
//	instructions works, as well as any strange instruction combinations.
//

ZipCPU

////////////////////////////////////////////////////////////////////////////////
//
// Filename: 	testb.h
//
// Project:	Zip CPU -- a small, lightweight, RISC CPU core
//
// Purpose:	A wrapper for a common interface to a clocked FPGA core
//		begin exercised in Verilator.
//
// Creator:	Dan Gisselquist, Ph.D.

ZipCPU

/////////////////////////////////////////////////////////////////////////////
//
// Filename: 	mpygen.cpp
//
// Project:	A simple, better, multiply generator
//
// Purpose:	This is the product of studying the signed, two's complement, 
//		multiply operation presented on wikipedia,
//
//		http://en.wikipedia.org/wiki/Binary_multiplier

ZipCPU

////////////////////////////////////////////////////////////////////
//
// Filename: 	string.c
//
// Project:	CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose:	To provide *some* of the C-library's capabilities, without
//		using perfectly optimal functions--but rather simple things that
//	can be easily tested and debugged.
//

ZipCPU

////////////////////////////////////////////////////////////////////////////////
//
// Filename:	div.v
//
// Project:	Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:	Provide an Integer divide capability to the Zip CPU.  Provides
//		for both signed and unsigned divide.
//
// Steps:

ZipCPU

///////////////////////////////////////////////////////////////////////////
//
// Filename: 	sgnmpy_16x16.v
//		
// Project:	A simple, better, multiply generator
//
// Purpose:	This verilog file multiplies two numbers together, without
// 		using any hardware acceleration.  The file itself is
// 		computer generated, so please (for your sake) don't
// 		make any edits to the file lest you regenerate it and

ZipCPU

////////////////////////////////////////////////////////////////////////////////
//
// Filename: 	bimpy
//
// Project:	A simple, better, multiply generator
//
// Purpose:	A simply 2-bit multiply based upon the fact that LUT's allow
//		6-bits of input, but a 2x2 bit multiply will never carry more
//		than one bit.  While this multiply is hardware independent,
//		it is really motivated by trying to optimize for a specific