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gistfile1.txt
================ Logging to /home/alahay01/dotnet/runtime_sve_api/artifacts/spmi/superpmi.10.log
Using JIT/EE Version from jiteeversionguid.h: b75a5475-ff22-4078-9551-2024ce03d383
SuperPMI replay
------------------------------------------------------------
Start time: 12:41:49
JIT Path: /home/alahay01/dotnet/runtime_sve_api/artifacts/spmi/basejit/f1bcbeb5fa2fe84698b62d88dd35199f0d7fbedb.linux.arm64.Checked/libclrjit.so
Using MCH files:
/home/alahay01/dotnet/runtime_sve_api/artifacts/spmi/mch/b75a5475-ff22-4078-9551-2024ce03d383.linux.arm64/benchmarks.run.linux.arm64.checked.mch
Using superpmi from Core_Root: /home/alahay01/dotnet/runtime_sve_api/artifacts/tests/coreclr/linux.arm64.Checked/Tests/Core_Root/superpmi
Temp Location: /tmp/tmpnugpojop
Running SuperPMI replay of /home/alahay01/dotnet/runtime_sve_api/artifacts/spmi/mch/b75a5475-ff22-4078-9551-2024ce03d383.linux.arm64/benchmarks.run.linux.arm64.checked.mch
Invoking: /home/alahay01/dotnet/runtime_sve_api/artifacts/tests/coreclr/linux.arm64.Checked/Tests/Core_Root/superpmi -v ewi -c 11416 -f /tmp/tmpnugpojop/benchmarks.run.linux.arm64.checked.mch_fail.mcl -details /tmp/tmpnugpojop/benchmarks.run.linux.arm64.checked.mch_details.csv /home/alahay01/dotnet/runtime_sve_api/artifacts/spmi/basejit/f1bcbeb5fa2fe84698b62d88dd35199f0d7fbedb.linux.arm64.Checked/libclrjit.so /home/alahay01/dotnet/runtime_sve_api/artifacts/spmi/mch/b75a5475-ff22-4078-9551-2024ce03d383.linux.arm64/benchmarks.run.linux.arm64.checked.mch
****** START compiling System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this (MethodHash=aff7d2df)
Generating code for Unix arm64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: optimizer should use profile data
IL to import:
IL_0000 7e 55 05 00 0a ldsfld 0xA000555
IL_0005 7e 56 05 00 0a ldsfld 0xA000556
IL_000a 28 68 01 00 2b call 0x2B000168
IL_000f 2a ret
Notify VM instruction set (AdvSimd) must be supported.
Found Vector128<ulong>
lvaSetClass: setting class for V00 to (0xffff41308cd8) System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
'this' passed in register x0
Parameter V00 ABI info: [00..08) reg x0
lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
Local V01 should not be enregistered because: it is address exposed
; Initial local variable assignments
;
; V00 this ref this class-hnd <System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]>
; V01 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 1
VarNum LVNum Name Beg End
0: 00h 00h V00 this 000h 010h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this
Jump targets:
none
New Basic Block BB01 [0000] created.
BB01 [0000] [000..010)
IL Code Size,Instr 16, 4, Basic Block count 1, Local Variable Num,Ref count 2, 0 for method System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this
OPTIONS: opts.MinOpts() == false
Basic block list for 'System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this'
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
Trees after Pre-import
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)
*************** Finishing PHASE Profile incorporation [no changes]
*************** Starting PHASE Importation
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this'
[ 0] 0 (0x000) ldsfld 0A000555
Checking if we can import 'static readonly' as a jit-time constant... checking if we can do anything for a large struct ...getStaticFieldContent returned false - bail out. Found Vector128<ulong>
[ 1] 5 (0x005) ldsfld 0A000556
Checking if we can import 'static readonly' as a jit-time constant... checking if we can do anything for a large struct ...getStaticFieldContent returned false - bail out.
[ 2] 10 (0x00a) call 2B000168
(Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT)
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128.Multiply: Notify VM instruction set (Vector128) must be supported.
Recognized
Calling impNormStructVal on:
[000011] --CXG------ * COMMA simd16
[000010] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000007] I---G------ \--* IND simd16
[000006] H---------- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
resulting tree:
[000011] --CXG------ * COMMA simd16
[000010] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000007] I---G------ \--* IND simd16
[000006] H---------- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
Calling impNormStructVal on:
[000005] --CXG------ * COMMA simd16
[000004] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000001] I---G------ \--* IND simd16
[000000] H---------- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
resulting tree:
[000005] --CXG------ * COMMA simd16
[000004] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000001] I---G------ \--* IND simd16
[000000] H---------- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
GTF_CALL_M_IMPLICIT_TAILCALL set for call [000012]
CheckCanInline: fetching method info for inline candidate Multiply -- context 0xffff41cd6308
Method context: System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong]
INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this' calling 'System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong]'
INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success'
Found Vector128<ulong>
changing the type of a call [000012] from struct to simd16
STMT00000 ( 0x000[E-] ... ??? )
[000012] I-CXG------ * CALL simd16 System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong] (exactContextHnd=0x0xffff41cd6308)
[000005] --CXG------ arg0 +--* COMMA simd16
[000004] H-CXG------ | +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H---------- arg0 | | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000001] I---G------ | \--* IND simd16
[000000] H---------- | \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
[000011] --CXG------ arg1 \--* COMMA simd16
[000010] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000007] I---G------ \--* IND simd16
[000006] H---------- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
[ 1] 15 (0x00f) ret
impFixupStructReturnType: retyping
[000013] --C-------- * RET_EXPR simd16(for [000012])
STMT00001 ( 0x000[E-] ... ??? )
[000014] --C-------- * RETURN simd16
[000013] --C-------- \--* RET_EXPR simd16(for [000012])
*************** Finishing PHASE Importation
Trees after Importation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x00F )
[000012] I-CXG------ * CALL simd16 System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong] (exactContextHnd=0x0xffff41cd6308)
[000005] --CXG------ arg0 +--* COMMA simd16
[000004] H-CXG------ | +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H---------- arg0 | | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000001] I---G------ | \--* IND simd16
[000000] H---------- | \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
[000011] --CXG------ arg1 \--* COMMA simd16
[000010] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000007] I---G------ \--* IND simd16
[000006] H---------- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
[000014] --C-------- * RETURN simd16
[000013] --C-------- \--* RET_EXPR simd16(for [000012])
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Indirect call transform
-- no candidates to transform
*************** Finishing PHASE Indirect call transform [no changes]
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import [no changes]
*************** Starting PHASE Morph - Init
New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** Finishing PHASE Morph - Init [no changes]
*************** Starting PHASE Morph - Inlining
INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper' for 'System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this' calling 'n/a'
INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper'
INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper' for 'System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this' calling 'n/a'
INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper'
Expanding INLINE_CANDIDATE in statement STMT00000 in BB01:
STMT00000 ( 0x000[E-] ... 0x00F )
[000012] I-CXG------ * CALL simd16 System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong] (exactContextHnd=0x0xffff41cd6308)
[000005] --CXG------ arg0 +--* COMMA simd16
[000004] H-CXG------ | +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H---------- arg0 | | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000001] I---G------ | \--* IND simd16
[000000] H---------- | \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
[000011] --CXG------ arg1 \--* COMMA simd16
[000010] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000007] I---G------ \--* IND simd16
[000006] H---------- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
Note: candidate is implicit tail call
Argument #0: has global refs has side effects
[000005] --CXG------ * COMMA simd16
[000004] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000001] I---G------ \--* IND simd16
[000000] H---------- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
Argument #1: has global refs has side effects
[000011] --CXG------ * COMMA simd16
[000010] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000007] I---G------ \--* IND simd16
[000006] H---------- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
INLINER: inlineInfo.tokenLookupContextHandle for System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong] set to 0x0xffff41cd6308:
Invoking compiler for the inlinee method System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong] :
IL to import:
IL_0000 02 ldarg.0
IL_0001 03 ldarg.1
IL_0002 28 d2 14 00 0a call 0xA0014D2
IL_0007 2a ret
INLINER impTokenLookupContextHandle for System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong] is 0x0xffff41cd6308.
Notify VM instruction set (AdvSimd) must be supported.
Found Vector128<ulong>
*************** In compInitDebuggingInfo() for System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong]
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong]
Named Intrinsic System.Runtime.Intrinsics.Vector128`1.op_Multiply: Notify VM instruction set (Vector128) must be supported.
Recognized
Jump targets:
none
New Basic Block BB01 [0001] created.
BB01 [0001] [000..008)
Basic block list for 'System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong]'
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001] 1 1 [000..008) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Inline @[000012] Starting PHASE Pre-import
*************** Inline @[000012] Finishing PHASE Pre-import
Trees after Pre-import
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001] 1 1 [000..008) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0001] [000..008) (return), preds={} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Inline @[000012] Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)
Computing inlinee profile scale:
... no callee profile data, will use non-pgo weight to scale
... call site not profiled, will use non-pgo weight to scale
call site count 100 callee entry count 100 scale 1
Scaling inlinee blocks
*************** Inline @[000012] Finishing PHASE Profile incorporation
Trees after Profile incorporation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001] 1 1 [000..008) (return)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0001] [000..008) (return), preds={} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Inline @[000012] Starting PHASE Importation
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong]'
[ 0] 0 (0x000) ldarg.0
lvaGrabTemp returning 2 (V02 tmp1) called for Inlining Arg.
Marked V02 as a single def temp
[ 1] 1 (0x001) ldarg.1
lvaGrabTemp returning 3 (V03 tmp2) called for Inlining Arg.
Marked V03 as a single def temp
[ 2] 2 (0x002) call 0A0014D2
(Inline Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT)
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Vector128`1.op_Multiply: Recognized
Found Vector128<ulong>
Found Vector128<ulong>
Found Vector128<ulong>
[ 1] 7 (0x007) ret
Inlinee Return expression (before normalization) =>
[000029] ----------- * HWINTRINSIC simd16 ulong Insert
[000020] ----------- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] ----------- | \--* MUL long
[000017] ----------- | +--* HWINTRINSIC long ulong ToScalar
[000015] ----------- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] ----------- | \--* HWINTRINSIC long ulong ToScalar
[000016] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] ----------- +--* CNS_INT int 1
[000027] ----------- \--* MUL long
[000024] ----------- +--* HWINTRINSIC long ulong GetElement
[000021] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000023] ----------- | \--* CNS_INT int 1
[000026] ----------- \--* HWINTRINSIC long ulong GetElement
[000022] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000025] ----------- \--* CNS_INT int 1
Found Vector128<ulong>
impFixupStructReturnType: retyping
[000029] ----------- * HWINTRINSIC simd16 ulong Insert
[000020] ----------- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] ----------- | \--* MUL long
[000017] ----------- | +--* HWINTRINSIC long ulong ToScalar
[000015] ----------- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] ----------- | \--* HWINTRINSIC long ulong ToScalar
[000016] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] ----------- +--* CNS_INT int 1
[000027] ----------- \--* MUL long
[000024] ----------- +--* HWINTRINSIC long ulong GetElement
[000021] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000023] ----------- | \--* CNS_INT int 1
[000026] ----------- \--* HWINTRINSIC long ulong GetElement
[000022] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000025] ----------- \--* CNS_INT int 1
Inlinee Return expression (after normalization) =>
[000029] ----------- * HWINTRINSIC simd16 ulong Insert
[000020] ----------- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] ----------- | \--* MUL long
[000017] ----------- | +--* HWINTRINSIC long ulong ToScalar
[000015] ----------- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] ----------- | \--* HWINTRINSIC long ulong ToScalar
[000016] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] ----------- +--* CNS_INT int 1
[000027] ----------- \--* MUL long
[000024] ----------- +--* HWINTRINSIC long ulong GetElement
[000021] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000023] ----------- | \--* CNS_INT int 1
[000026] ----------- \--* HWINTRINSIC long ulong GetElement
[000022] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000025] ----------- \--* CNS_INT int 1
** Note: inlinee IL was partially imported -- imported 0 of 8 bytes of method IL
*************** Inline @[000012] Finishing PHASE Importation
Trees after Importation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0001] 1 1 [000..008) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0001] [000..008) (return), preds={} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Inline @[000012] Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Inline @[000012] Finishing PHASE Expand patchpoints [no changes]
*************** Inline @[000012] Starting PHASE Indirect call transform
-- no candidates to transform
*************** Inline @[000012] Finishing PHASE Indirect call transform [no changes]
*************** Inline @[000012] Starting PHASE Post-import
*************** Inline @[000012] Finishing PHASE Post-import [no changes]
----------- Statements (and blocks) added due to the inlining of call [000012] -----------
Arguments setup:
STMT00002 ( 0x000[E-] ... ??? )
[000005] -ACXG------ * COMMA simd16
[000004] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000030] DA--G------ \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G------ \--* IND simd16
[000000] H---------- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
STMT00003 ( 0x000[E-] ... ??? )
[000011] -ACXG------ * COMMA simd16
[000010] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000031] DA--G------ \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G------ \--* IND simd16
[000006] H---------- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
Inlinee method body:fgInlineAppendStatements: no gc ref inline locals.
Successfully inlined System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong] (8 IL bytes) (depth 1) [below ALWAYS_INLINE size]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this' calling 'System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong]'
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size'
INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper' for 'System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this' calling 'n/a'
INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper'
INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper' for 'System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this' calling 'n/a'
INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper'
Replacing the return expression placeholder [000013] with [000029]
[000013] --C-------- * RET_EXPR simd16(for [000012]) -> [000029]
Inserting the inline return expression
[000029] ----------- * HWINTRINSIC simd16 ulong Insert
[000020] ----------- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] ----------- | \--* MUL long
[000017] ----------- | +--* HWINTRINSIC long ulong ToScalar
[000015] ----------- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] ----------- | \--* HWINTRINSIC long ulong ToScalar
[000016] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] ----------- +--* CNS_INT int 1
[000027] ----------- \--* MUL long
[000024] ----------- +--* HWINTRINSIC long ulong GetElement
[000021] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000023] ----------- | \--* CNS_INT int 1
[000026] ----------- \--* HWINTRINSIC long ulong GetElement
[000022] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000025] ----------- \--* CNS_INT int 1
**************** Inline Tree
Inlines into 06000000 [via ExtendedDefaultPolicy] System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this:
[INL01 IL=0010 TR=000012 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Runtime.Intrinsics.Vector128:Multiply[ulong](System.Runtime.Intrinsics.Vector128`1[ulong],System.Runtime.Intrinsics.Vector128`1[ulong]):System.Runtime.Intrinsics.Vector128`1[ulong]
Budget: initialTime=108, finalTime=94, initialBudget=1080, currentBudget=1080
Budget: initialSize=496, finalSize=496
*************** Before renumbering the basic blocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
=============== No blocks renumbered!
*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
[000005] -ACXG------ * COMMA simd16
[000004] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000030] DA--G------ \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G------ \--* IND simd16
[000000] H---------- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
[000011] -ACXG------ * COMMA simd16
[000010] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000031] DA--G------ \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G------ \--* IND simd16
[000006] H---------- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
[000014] --C-------- * RETURN simd16
[000029] ----------- \--* HWINTRINSIC simd16 ulong Insert
[000020] ----------- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] ----------- | \--* MUL long
[000017] ----------- | +--* HWINTRINSIC long ulong ToScalar
[000015] ----------- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] ----------- | \--* HWINTRINSIC long ulong ToScalar
[000016] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] ----------- +--* CNS_INT int 1
[000027] ----------- \--* MUL long
[000024] ----------- +--* HWINTRINSIC long ulong GetElement
[000021] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000023] ----------- | \--* CNS_INT int 1
[000026] ----------- \--* HWINTRINSIC long ulong GetElement
[000022] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000025] ----------- \--* CNS_INT int 1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Allocate Objects
no newobjs in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks [no changes]
*************** Starting PHASE Add Swift error returns
*************** Finishing PHASE Add Swift error returns [no changes]
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally [no changes]
*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Head and tail merge
*************** Finishing PHASE Head and tail merge
Trees after Head and tail merge
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
[000005] -ACXG------ * COMMA simd16
[000004] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000030] DA--G------ \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G------ \--* IND simd16
[000000] H---------- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
[000011] -ACXG------ * COMMA simd16
[000010] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000031] DA--G------ \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G------ \--* IND simd16
[000006] H---------- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
[000014] --C-------- * RETURN simd16
[000029] ----------- \--* HWINTRINSIC simd16 ulong Insert
[000020] ----------- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] ----------- | \--* MUL long
[000017] ----------- | +--* HWINTRINSIC long ulong ToScalar
[000015] ----------- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] ----------- | \--* HWINTRINSIC long ulong ToScalar
[000016] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] ----------- +--* CNS_INT int 1
[000027] ----------- \--* MUL long
[000024] ----------- +--* HWINTRINSIC long ulong GetElement
[000021] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000023] ----------- | \--* CNS_INT int 1
[000026] ----------- \--* HWINTRINSIC long ulong GetElement
[000022] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000025] ----------- \--* CNS_INT int 1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Merge throw blocks
*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.
*************** Finishing PHASE Merge throw blocks [no changes]
*************** Starting PHASE Update flow graph early pass
*************** Finishing PHASE Update flow graph early pass [no changes]
*************** Starting PHASE Morph - Promote Structs
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 this ref this class-hnd <System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]>
; V01 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
; V02 tmp1 simd16 HFA(simd16) "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ulong]>
; V03 tmp2 simd16 HFA(simd16) "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ulong]>
struct promotion of V01 is disabled because it has already been marked DNER
*************** Finishing PHASE Morph - Promote Structs [no changes]
*************** Starting PHASE Canonicalize entry
*************** Finishing PHASE Canonicalize entry [no changes]
*************** Starting PHASE DFS blocks and remove dead code
*************** Finishing PHASE DFS blocks and remove dead code [no changes]
*************** Starting PHASE Morph - Structs/AddrExp
LocalAddressVisitor visiting statement:
STMT00002 ( 0x000[E-] ... ??? )
[000005] -ACXG------ * COMMA simd16
[000004] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000030] DA--G------ \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G------ \--* IND simd16
[000000] H---------- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
LocalAddressVisitor visiting statement:
STMT00003 ( 0x000[E-] ... ??? )
[000011] -ACXG------ * COMMA simd16
[000010] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000031] DA--G------ \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G------ \--* IND simd16
[000006] H---------- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
LocalAddressVisitor visiting statement:
STMT00001 ( 0x000[E-] ... ??? )
[000014] --C-------- * RETURN simd16
[000029] ----------- \--* HWINTRINSIC simd16 ulong Insert
[000020] ----------- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] ----------- | \--* MUL long
[000017] ----------- | +--* HWINTRINSIC long ulong ToScalar
[000015] ----------- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] ----------- | \--* HWINTRINSIC long ulong ToScalar
[000016] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] ----------- +--* CNS_INT int 1
[000027] ----------- \--* MUL long
[000024] ----------- +--* HWINTRINSIC long ulong GetElement
[000021] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000023] ----------- | \--* CNS_INT int 1
[000026] ----------- \--* HWINTRINSIC long ulong GetElement
[000022] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000025] ----------- \--* CNS_INT int 1
*************** Finishing PHASE Morph - Structs/AddrExp [no changes]
*************** Starting PHASE Early liveness
Local V01 should not be enregistered because: struct size does not match reg size
Tracked variable (2 out of 4) table:
V02 tmp1 [simd16]: refCnt = 3, refCntWtd = 0
V03 tmp2 [simd16]: refCnt = 3, refCntWtd = 0
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={ }
DEF(2)={V02 V03}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (0)={}
OUT(0)={}
*************** Finishing PHASE Early liveness
Trees after Early liveness
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
[000005] -ACXG------ * COMMA simd16
[000004] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000030] DA--G------ \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G------ \--* IND simd16
[000000] H---------- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
[000011] -ACXG------ * COMMA simd16
[000010] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000031] DA--G------ \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G------ \--* IND simd16
[000006] H---------- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
[000014] --C-------- * RETURN simd16
[000029] ----------- \--* HWINTRINSIC simd16 ulong Insert
[000020] ----------- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] ----------- | \--* MUL long
[000017] ----------- | +--* HWINTRINSIC long ulong ToScalar
[000015] ----------- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] ----------- | \--* HWINTRINSIC long ulong ToScalar
[000016] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] ----------- +--* CNS_INT int 1
[000027] ----------- \--* MUL long
[000024] ----------- +--* HWINTRINSIC long ulong GetElement
[000021] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 (last use)
[000023] ----------- | \--* CNS_INT int 1
[000026] ----------- \--* HWINTRINSIC long ulong GetElement
[000022] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 (last use)
[000025] ----------- \--* CNS_INT int 1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Forward Substitution
===> BB01
*************** Finishing PHASE Forward Substitution [no changes]
*************** Starting PHASE Physical promotion
*************** Finishing PHASE Physical promotion [no changes]
*************** Starting PHASE Identify candidates for implicit byref copy omission
*************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes]
*************** Starting PHASE Morph - ByRefs
*************** Finishing PHASE Morph - ByRefs [no changes]
*************** Starting PHASE Morph - Global
Morphing BB01
Assertions in: #NA
fgMorphTree BB01, STMT00002 (before)
[000005] -ACXG------ * COMMA simd16
[000004] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000030] DA--G------ \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G------ \--* IND simd16
[000000] H---------- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
Initializing arg info for 4.CALL:
Argument 0 ABI info: [00..08) reg x0
Args for call [000004] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000003].CNS_INT long (By value), 1 reg: x0]
Morphing args for 4.CALL:
Sorting the arguments:
Deferred argument ('x0'):
[000003] H----+----- * CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
Moved to late list
Register placement order: x0
Args for [000004].CALL after fgMorphArgs:
CallArg[[000003].CNS_INT long (By value), 1 reg: x0, isLate, processed]
OutgoingArgsStackSize is 0
MorphCopyBlock:
PrepareDst for [000030] have found a local var V02.
block store to morph:
[000030] DA--G------ * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G+----- \--* IND simd16
[000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
this requires a CopyBlock.
MorphCopyBlock (after):
[000030] DA--G------ * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G+----- \--* IND simd16
[000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
fgMorphTree BB01, STMT00003 (before)
[000011] -ACXG------ * COMMA simd16
[000010] H-CXG------ +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H---------- arg0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000031] DA--G------ \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G------ \--* IND simd16
[000006] H---------- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
Initializing arg info for 10.CALL:
Argument 0 ABI info: [00..08) reg x0
Args for call [000010] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000009].CNS_INT long (By value), 1 reg: x0]
Morphing args for 10.CALL:
Sorting the arguments:
Deferred argument ('x0'):
[000009] H----+----- * CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
Moved to late list
Register placement order: x0
Args for [000010].CALL after fgMorphArgs:
CallArg[[000009].CNS_INT long (By value), 1 reg: x0, isLate, processed]
OutgoingArgsStackSize is 0
MorphCopyBlock:
PrepareDst for [000031] have found a local var V03.
block store to morph:
[000031] DA--G------ * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G+----- \--* IND simd16
[000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
this requires a CopyBlock.
MorphCopyBlock (after):
[000031] DA--G------ * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G+----- \--* IND simd16
[000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
fgMorphTree BB01, STMT00001 (before)
[000014] --C-------- * RETURN simd16
[000029] ----------- \--* HWINTRINSIC simd16 ulong Insert
[000020] ----------- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] ----------- | \--* MUL long
[000017] ----------- | +--* HWINTRINSIC long ulong ToScalar
[000015] ----------- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] ----------- | \--* HWINTRINSIC long ulong ToScalar
[000016] ----------- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] ----------- +--* CNS_INT int 1
[000027] ----------- \--* MUL long
[000024] ----------- +--* HWINTRINSIC long ulong GetElement
[000021] ----------- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 (last use)
[000023] ----------- | \--* CNS_INT int 1
[000026] ----------- \--* HWINTRINSIC long ulong GetElement
[000022] ----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 (last use)
[000025] ----------- \--* CNS_INT int 1
morph assertion stats: 64 table size, 0 assertions, 0 dropped
*************** Finishing PHASE Morph - Global
Trees after Morph - Global
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
[000005] -ACXG+----- * COMMA void
[000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G+----- \--* IND simd16
[000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
[000011] -ACXG+----- * COMMA void
[000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G+----- \--* IND simd16
[000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
[000014] -----+----- * RETURN simd16
[000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert
[000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] -----+----- | \--* MUL long
[000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar
[000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar
[000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] -----+-N--- +--* CNS_INT int 1
[000027] -----+----- \--* MUL long
[000024] -----+----- +--* HWINTRINSIC long ulong GetElement
[000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 (last use)
[000023] -----+----- | \--* CNS_INT int 1
[000026] -----+----- \--* HWINTRINSIC long ulong GetElement
[000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 (last use)
[000025] -----+----- \--* CNS_INT int 1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Post-Morph
*************** In fgMarkDemotedImplicitByRefArgs()
*************** Finishing PHASE Post-Morph
Trees after Post-Morph
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
[000005] -ACXG+----- * COMMA void
[000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G+----- \--* IND simd16
[000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
[000011] -ACXG+----- * COMMA void
[000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G+----- \--* IND simd16
[000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
[000014] -----+----- * RETURN simd16
[000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert
[000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] -----+----- | \--* MUL long
[000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar
[000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar
[000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] -----+-N--- +--* CNS_INT int 1
[000027] -----+----- \--* MUL long
[000024] -----+----- +--* HWINTRINSIC long ulong GetElement
[000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000023] -----+----- | \--* CNS_INT int 1
[000026] -----+----- \--* HWINTRINSIC long ulong GetElement
[000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000025] -----+----- \--* CNS_INT int 1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie [no changes]
*************** Starting PHASE Compute block weights
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
*************** Finishing PHASE Compute block weights [no changes]
*************** Starting PHASE Create EH funclets
*************** Finishing PHASE Create EH funclets [no changes]
*************** Starting PHASE Invert loops
*************** Before renumbering the basic blocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
=============== No blocks renumbered!
*************** Finishing PHASE Invert loops [no changes]
*************** Starting PHASE Optimize control flow
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize control flow
Trees after Optimize control flow
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
[000005] -ACXG+----- * COMMA void
[000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G+----- \--* IND simd16
[000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
[000011] -ACXG+----- * COMMA void
[000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G+----- \--* IND simd16
[000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
[000014] -----+----- * RETURN simd16
[000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert
[000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] -----+----- | \--* MUL long
[000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar
[000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar
[000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] -----+-N--- +--* CNS_INT int 1
[000027] -----+----- \--* MUL long
[000024] -----+----- +--* HWINTRINSIC long ulong GetElement
[000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000023] -----+----- | \--* CNS_INT int 1
[000026] -----+----- \--* HWINTRINSIC long ulong GetElement
[000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000025] -----+----- \--* CNS_INT int 1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Post-morph head and tail merge
*************** Finishing PHASE Post-morph head and tail merge
Trees after Post-morph head and tail merge
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
[000005] -ACXG+----- * COMMA void
[000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G+----- \--* IND simd16
[000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
[000011] -ACXG+----- * COMMA void
[000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G+----- \--* IND simd16
[000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
[000014] -----+----- * RETURN simd16
[000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert
[000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] -----+----- | \--* MUL long
[000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar
[000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar
[000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] -----+-N--- +--* CNS_INT int 1
[000027] -----+----- \--* MUL long
[000024] -----+----- +--* HWINTRINSIC long ulong GetElement
[000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000023] -----+----- | \--* CNS_INT int 1
[000026] -----+----- \--* HWINTRINSIC long ulong GetElement
[000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000025] -----+----- \--* CNS_INT int 1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Canonicalize entry
*************** Finishing PHASE Canonicalize entry [no changes]
*************** Starting PHASE DFS blocks and remove dead code 2
*************** Finishing PHASE DFS blocks and remove dead code 2 [no changes]
*************** Starting PHASE Find loops
*************** In optFindLoopsPhase()
*************** Before renumbering the basic blocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
=============== No blocks renumbered!
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 0]
Flow graph has no cycles; skipping identification of natural loops
*************** Before renumbering the basic blocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
=============== No blocks renumbered!
*************** Finishing PHASE Find loops
Trees after Find loops
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
[000005] -ACXG+----- * COMMA void
[000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G+----- \--* IND simd16
[000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
[000011] -ACXG+----- * COMMA void
[000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G+----- \--* IND simd16
[000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
[000014] -----+----- * RETURN simd16
[000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert
[000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] -----+----- | \--* MUL long
[000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar
[000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar
[000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] -----+-N--- +--* CNS_INT int 1
[000027] -----+----- \--* MUL long
[000024] -----+----- +--* HWINTRINSIC long ulong GetElement
[000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000023] -----+----- | \--* CNS_INT int 1
[000026] -----+----- \--* HWINTRINSIC long ulong GetElement
[000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000025] -----+----- \--* CNS_INT int 1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Set block weights
After computing the dominance tree:
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
Return blocks: BB01
*************** Finishing PHASE Set block weights [no changes]
*************** Starting PHASE Clone loops
*************** In optCloneLoops()
No loops to clone
*************** Finishing PHASE Clone loops [no changes]
*************** Starting PHASE Unroll loops
*************** Finishing PHASE Unroll loops [no changes]
*************** Starting PHASE Compute dominators
*************** Finishing PHASE Compute dominators [no changes]
*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function
*************** Finishing PHASE Morph array ops [no changes]
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
*** marking local variables in block BB01 (weight=1)
STMT00002 ( 0x000[E-] ... ??? )
[000005] -ACXG+----- * COMMA void
[000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000001] I---G+----- \--* IND simd16
[000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
New refCnts for V02: refCnt = 1, refCntWtd = 2
V02 needs explicit zero init. Disqualified as a single-def register candidate.
STMT00003 ( 0x000[E-] ... ??? )
[000011] -ACXG+----- * COMMA void
[000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
[000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
[000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000007] I---G+----- \--* IND simd16
[000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
New refCnts for V03: refCnt = 1, refCntWtd = 2
V03 needs explicit zero init. Disqualified as a single-def register candidate.
STMT00001 ( 0x000[E-] ... ??? )
[000014] -----+----- * RETURN simd16
[000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert
[000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
[000019] -----+----- | \--* MUL long
[000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar
[000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar
[000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000028] -----+-N--- +--* CNS_INT int 1
[000027] -----+----- \--* MUL long
[000024] -----+----- +--* HWINTRINSIC long ulong GetElement
[000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
[000023] -----+----- | \--* CNS_INT int 1
[000026] -----+----- \--* HWINTRINSIC long ulong GetElement
[000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
[000025] -----+----- \--* CNS_INT int 1
New refCnts for V02: refCnt = 2, refCntWtd = 4
New refCnts for V03: refCnt = 2, refCntWtd = 4
New refCnts for V02: refCnt = 3, refCntWtd = 6
New refCnts for V03: refCnt = 3, refCntWtd = 6
*** lvaComputeRefCounts -- implicit counts ***
*************** Finishing PHASE Mark local vars [no changes]
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
Trees after Find oper order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
( 23, 29) [000005] -ACXG+----- * COMMA void
( 17, 15) [000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
( 3, 12) [000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
( 6, 14) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
( 6, 14) [000001] I---G+----- \--* IND simd16
( 3, 12) [000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
( 23, 29) [000011] -ACXG+----- * COMMA void
( 17, 15) [000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
( 3, 12) [000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
( 6, 14) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
( 6, 14) [000007] I---G+----- \--* IND simd16
( 3, 12) [000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
( 22, 23) [000014] -----+----- * RETURN simd16
( 21, 22) [000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert
( 9, 8) [000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
( 8, 7) [000019] -----+----- | \--* MUL long
( 2, 2) [000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar
( 1, 1) [000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
( 2, 2) [000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar
( 1, 1) [000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
( 1, 2) [000028] -----+-N--- +--* CNS_INT int 1
( 10, 11) [000027] -----+----- \--* MUL long
( 3, 4) [000024] -----+----- +--* HWINTRINSIC long ulong GetElement
( 1, 1) [000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
( 1, 2) [000023] -----+----- | \--* CNS_INT int 1
( 3, 4) [000026] -----+----- \--* HWINTRINSIC long ulong GetElement
( 1, 1) [000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
( 1, 2) [000025] -----+----- \--* CNS_INT int 1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 16 tree nodes
*************** Finishing PHASE Set block order
Trees after Set block order
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
N006 ( 23, 29) [000005] -ACXG+----- * COMMA void
N002 ( 17, 15) [000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
N001 ( 3, 12) [000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
N005 ( 6, 14) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
N004 ( 6, 14) [000001] I---G+----- \--* IND simd16
N003 ( 3, 12) [000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
N006 ( 23, 29) [000011] -ACXG+----- * COMMA void
N002 ( 17, 15) [000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
N001 ( 3, 12) [000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
N005 ( 6, 14) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
N004 ( 6, 14) [000007] I---G+----- \--* IND simd16
N003 ( 3, 12) [000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
N016 ( 22, 23) [000014] -----+----- * RETURN simd16
N015 ( 21, 22) [000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert
N006 ( 9, 8) [000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
N005 ( 8, 7) [000019] -----+----- | \--* MUL long
N002 ( 2, 2) [000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar
N001 ( 1, 1) [000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
N004 ( 2, 2) [000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar
N003 ( 1, 1) [000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
N007 ( 1, 2) [000028] -----+-N--- +--* CNS_INT int 1
N014 ( 10, 11) [000027] -----+----- \--* MUL long
N010 ( 3, 4) [000024] -----+----- +--* HWINTRINSIC long ulong GetElement
N008 ( 1, 1) [000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1
N009 ( 1, 2) [000023] -----+----- | \--* CNS_INT int 1
N013 ( 3, 4) [000026] -----+----- \--* HWINTRINSIC long ulong GetElement
N011 ( 1, 1) [000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2
N012 ( 1, 2) [000025] -----+----- \--* CNS_INT int 1
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Local V01 should not be enregistered because: struct size does not match reg size
Tracked variable (2 out of 4) table:
V02 tmp1 [simd16]: refCnt = 3, refCntWtd = 6
V03 tmp2 [simd16]: refCnt = 3, refCntWtd = 6
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={ } + ByrefExposed + GcHeap
DEF(2)={V02 V03} + ByrefExposed* + GcHeap*
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={}
*************** In optRemoveRedundantZeroInits()
Analyzing BB01
Marking V02 as having an explicit init
Marking V03 as having an explicit init
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
V02.1: defined in BB01 2 uses (local)
V03.1: defined in BB01 2 uses (local)
*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
N006 ( 23, 29) [000005] -ACXG+----- * COMMA void
N002 ( 17, 15) [000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
N001 ( 3, 12) [000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
N005 ( 6, 14) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1
N004 ( 6, 14) [000001] I---G+----- \--* IND simd16
N003 ( 3, 12) [000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
N006 ( 23, 29) [000011] -ACXG+----- * COMMA void
N002 ( 17, 15) [000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
N001 ( 3, 12) [000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
N005 ( 6, 14) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1
N004 ( 6, 14) [000007] I---G+----- \--* IND simd16
N003 ( 3, 12) [000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
N016 ( 22, 23) [000014] -----+----- * RETURN simd16
N015 ( 21, 22) [000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert
N006 ( 9, 8) [000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
N005 ( 8, 7) [000019] -----+----- | \--* MUL long
N002 ( 2, 2) [000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar
N001 ( 1, 1) [000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1
N004 ( 2, 2) [000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar
N003 ( 1, 1) [000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1
N007 ( 1, 2) [000028] -----+-N--- +--* CNS_INT int 1
N014 ( 10, 11) [000027] -----+----- \--* MUL long
N010 ( 3, 4) [000024] -----+----- +--* HWINTRINSIC long ulong GetElement
N008 ( 1, 1) [000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 (last use)
N009 ( 1, 2) [000023] -----+----- | \--* CNS_INT int 1
N013 ( 3, 4) [000026] -----+----- \--* HWINTRINSIC long ulong GetElement
N011 ( 1, 1) [000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 (last use)
N012 ( 1, 2) [000025] -----+----- \--* CNS_INT int 1
SSA MEM: ByrefExposed, GcHeap = m:2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
SSA checks completed successfully
*************** Starting PHASE Early Value Propagation
no arrays or null checks in the method
*************** Finishing PHASE Early Value Propagation [no changes]
*************** Starting PHASE Do value numbering
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $80
Visiting BB01
The SSA definition for ByrefExposed (#1) at start of BB01 is $80 {InitVal($40)}
The SSA definition for GcHeap (#1) at start of BB01 is $80 {InitVal($40)}
***** BB01, STMT00002(before)
N006 ( 23, 29) [000005] -ACXG+----- * COMMA void
N002 ( 17, 15) [000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
N001 ( 3, 12) [000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
N005 ( 6, 14) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1
N004 ( 6, 14) [000001] I---G+----- \--* IND simd16
N003 ( 3, 12) [000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>]
N001 [000003] CNS_INT(h) 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] => $c0 {Hnd const: 0x0xffff41308cd8 GTF_ICON_CLASS_HDL System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]}
N002 [000004] CALL help => $1c0 {norm=$180 {GetGcstaticBase($c0)}, exc=$140 {ClassInitGenericExc($c0)}}
N003 [000000] CNS_INT(h) 0xffbe99a53888 static Fseq[<unknown field>] => $c1 {Hnd const: 0x0xffbe99a53888 GTF_ICON_STATIC_HDL}
Found Vector128<ulong>
VNForHandle(<unknown field>) is $c2, fieldType is simd16, size = 16
VNForMapSelect($80, $c2):simd16 returns $200 {$80[$c2]}
N004 [000001] IND => <l:$200 {$80[$c2]}, c:$240 {MemOpaque:NotInLoop}>
Tree [000030] assigned VN to local var V02/1: <l:$200 {$80[$c2]}, c:$240 {MemOpaque:NotInLoop}>
N005 [000030] STORE_LCL_VAR V02 tmp1 d:1 => $VN.Void
N006 [000005] COMMA => $141 {norm=$VN.Void, exc=$140 {ClassInitGenericExc($c0)}}
***** BB01, STMT00002(after)
N006 ( 23, 29) [000005] -ACXG+----- * COMMA void $141
N002 ( 17, 15) [000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) [000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
N005 ( 6, 14) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
N004 ( 6, 14) [000001] I---G+----- \--* IND simd16 <l:$200, c:$240>
N003 ( 3, 12) [000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
---------
***** BB01, STMT00003(before)
N006 ( 23, 29) [000011] -ACXG+----- * COMMA void
N002 ( 17, 15) [000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE
N001 ( 3, 12) [000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
N005 ( 6, 14) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1
N004 ( 6, 14) [000007] I---G+----- \--* IND simd16
N003 ( 3, 12) [000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>]
N001 [000009] CNS_INT(h) 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] => $c0 {Hnd const: 0x0xffff41308cd8 GTF_ICON_CLASS_HDL System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]}
N002 [000010] CALL help => $1c0 {norm=$180 {GetGcstaticBase($c0)}, exc=$140 {ClassInitGenericExc($c0)}}
N003 [000006] CNS_INT(h) 0xffbe99a538a8 static Fseq[<unknown field>] => $c3 {Hnd const: 0x0xffbe99a538a8 GTF_ICON_STATIC_HDL}
Found Vector128<ulong>
VNForHandle(<unknown field>) is $c4, fieldType is simd16, size = 16
VNForMapSelect($80, $c4):simd16 returns $201 {$80[$c4]}
N004 [000007] IND => <l:$201 {$80[$c4]}, c:$241 {MemOpaque:NotInLoop}>
Tree [000031] assigned VN to local var V03/1: <l:$201 {$80[$c4]}, c:$241 {MemOpaque:NotInLoop}>
N005 [000031] STORE_LCL_VAR V03 tmp2 d:1 => $VN.Void
N006 [000011] COMMA => $141 {norm=$VN.Void, exc=$140 {ClassInitGenericExc($c0)}}
***** BB01, STMT00003(after)
N006 ( 23, 29) [000011] -ACXG+----- * COMMA void $141
N002 ( 17, 15) [000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) [000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
N005 ( 6, 14) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
N004 ( 6, 14) [000007] I---G+----- \--* IND simd16 <l:$201, c:$241>
N003 ( 3, 12) [000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>] $c3
---------
***** BB01, STMT00001(before)
N016 ( 22, 23) [000014] -----+----- * RETURN simd16
N015 ( 21, 22) [000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert
N006 ( 9, 8) [000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe
N005 ( 8, 7) [000019] -----+----- | \--* MUL long
N002 ( 2, 2) [000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar
N001 ( 1, 1) [000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1
N004 ( 2, 2) [000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar
N003 ( 1, 1) [000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1
N007 ( 1, 2) [000028] -----+-N--- +--* CNS_INT int 1
N014 ( 10, 11) [000027] -----+----- \--* MUL long
N010 ( 3, 4) [000024] -----+----- +--* HWINTRINSIC long ulong GetElement
N008 ( 1, 1) [000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 (last use)
N009 ( 1, 2) [000023] -----+----- | \--* CNS_INT int 1
N013 ( 3, 4) [000026] -----+----- \--* HWINTRINSIC long ulong GetElement
N011 ( 1, 1) [000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 (last use)
N012 ( 1, 2) [000025] -----+----- \--* CNS_INT int 1
N001 [000015] LCL_VAR V02 tmp1 u:1 => <l:$200 {$80[$c2]}, c:$240 {MemOpaque:NotInLoop}>
simdTypeVN is $142 {SimdType(simd16, ulong)}
N002 [000017] HWINTRINSIC => <l:$280 {HWI_Vector128_ToScalar($200, $142)}, c:$281 {HWI_Vector128_ToScalar($240, $142)}>
N003 [000016] LCL_VAR V03 tmp2 u:1 => <l:$201 {$80[$c4]}, c:$241 {MemOpaque:NotInLoop}>
simdTypeVN is $142 {SimdType(simd16, ulong)}
N004 [000018] HWINTRINSIC => <l:$282 {HWI_Vector128_ToScalar($201, $142)}, c:$283 {HWI_Vector128_ToScalar($241, $142)}>
N005 [000019] MUL => <l:$284 {MUL($280, $282)}, c:$285 {MUL($281, $283)}>
simdTypeVN is $142 {SimdType(simd16, ulong)}
N006 [000020] HWINTRINSIC => <l:$202 {HWI_Vector128_CreateScalarUnsafe($284, $142)}, c:$203 {HWI_Vector128_CreateScalarUnsafe($285, $142)}>
N007 [000028] CNS_INT 1 => $43 {IntCns 1}
N008 [000021] LCL_VAR V02 tmp1 u:1 (last use) => <l:$200 {$80[$c2]}, c:$240 {MemOpaque:NotInLoop}>
N009 [000023] CNS_INT 1 => $43 {IntCns 1}
simdTypeVN is $142 {SimdType(simd16, ulong)}
N010 [000024] HWINTRINSIC => <l:$300 {HWI_Vector128_GetElement($200, $43, $142)}, c:$301 {HWI_Vector128_GetElement($240, $43, $142)}>
N011 [000022] LCL_VAR V03 tmp2 u:1 (last use) => <l:$201 {$80[$c4]}, c:$241 {MemOpaque:NotInLoop}>
N012 [000025] CNS_INT 1 => $43 {IntCns 1}
simdTypeVN is $142 {SimdType(simd16, ulong)}
N013 [000026] HWINTRINSIC => <l:$302 {HWI_Vector128_GetElement($201, $43, $142)}, c:$303 {HWI_Vector128_GetElement($241, $43, $142)}>
N014 [000027] MUL => <l:$286 {MUL($300, $302)}, c:$287 {MUL($301, $303)}>
simdTypeVN is $142 {SimdType(simd16, ulong)}
N015 [000029] HWINTRINSIC => <l:$340 {HWI_AdvSimd_Insert($202, $43, $286, $142)}, c:$341 {HWI_AdvSimd_Insert($203, $43, $287, $142)}>
N016 [000014] RETURN => $VN.Void
***** BB01, STMT00001(after)
N016 ( 22, 23) [000014] -----+----- * RETURN simd16 $VN.Void
N015 ( 21, 22) [000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert <l:$340, c:$341>
N006 ( 9, 8) [000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe <l:$202, c:$203>
N005 ( 8, 7) [000019] -----+----- | \--* MUL long <l:$284, c:$285>
N002 ( 2, 2) [000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar <l:$280, c:$281>
N001 ( 1, 1) [000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 <l:$200, c:$240>
N004 ( 2, 2) [000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar <l:$282, c:$283>
N003 ( 1, 1) [000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 <l:$201, c:$241>
N007 ( 1, 2) [000028] -----+-N--- +--* CNS_INT int 1 $43
N014 ( 10, 11) [000027] -----+----- \--* MUL long <l:$286, c:$287>
N010 ( 3, 4) [000024] -----+----- +--* HWINTRINSIC long ulong GetElement <l:$300, c:$301>
N008 ( 1, 1) [000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 (last use) <l:$200, c:$240>
N009 ( 1, 2) [000023] -----+----- | \--* CNS_INT int 1 $43
N013 ( 3, 4) [000026] -----+----- \--* HWINTRINSIC long ulong GetElement <l:$302, c:$303>
N011 ( 1, 1) [000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 (last use) <l:$201, c:$241>
N012 ( 1, 2) [000025] -----+----- \--* CNS_INT int 1 $43
*************** Finishing PHASE Do value numbering
Trees after Do value numbering
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
SSA MEM: ByrefExposed, GcHeap = m:1
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
N006 ( 23, 29) [000005] -ACXG+----- * COMMA void $141
N002 ( 17, 15) [000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) [000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
N005 ( 6, 14) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
N004 ( 6, 14) [000001] I---G+----- \--* IND simd16 <l:$200, c:$240>
N003 ( 3, 12) [000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
N006 ( 23, 29) [000011] -ACXG+----- * COMMA void $141
N002 ( 17, 15) [000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) [000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
N005 ( 6, 14) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
N004 ( 6, 14) [000007] I---G+----- \--* IND simd16 <l:$201, c:$241>
N003 ( 3, 12) [000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>] $c3
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
N016 ( 22, 23) [000014] -----+----- * RETURN simd16 $VN.Void
N015 ( 21, 22) [000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert <l:$340, c:$341>
N006 ( 9, 8) [000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe <l:$202, c:$203>
N005 ( 8, 7) [000019] -----+----- | \--* MUL long <l:$284, c:$285>
N002 ( 2, 2) [000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar <l:$280, c:$281>
N001 ( 1, 1) [000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 <l:$200, c:$240>
N004 ( 2, 2) [000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar <l:$282, c:$283>
N003 ( 1, 1) [000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 <l:$201, c:$241>
N007 ( 1, 2) [000028] -----+-N--- +--* CNS_INT int 1 $43
N014 ( 10, 11) [000027] -----+----- \--* MUL long <l:$286, c:$287>
N010 ( 3, 4) [000024] -----+----- +--* HWINTRINSIC long ulong GetElement <l:$300, c:$301>
N008 ( 1, 1) [000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 (last use) <l:$200, c:$240>
N009 ( 1, 2) [000023] -----+----- | \--* CNS_INT int 1 $43
N013 ( 3, 4) [000026] -----+----- \--* HWINTRINSIC long ulong GetElement <l:$302, c:$303>
N011 ( 1, 1) [000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 (last use) <l:$201, c:$241>
N012 ( 1, 2) [000025] -----+----- \--* CNS_INT int 1 $43
SSA MEM: ByrefExposed, GcHeap = m:2
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
SSA checks completed successfully
*************** Starting PHASE Hoist loop code
No loops; no hoisting
*************** Finishing PHASE Hoist loop code [no changes]
*************** Starting PHASE VN based copy prop
Copy Assertion for BB01
curSsaName stack: { }
Live vars after [000030]: {} +{V02} => {V02}
Live vars after [000031]: {V02} +{V03} => {V02 V03}
Live vars after [000021]: {V02 V03} -{V02} => {V03}
Live vars after [000022]: {V03} -{V03} => {}
*************** Finishing PHASE VN based copy prop [no changes]
*************** Starting PHASE Redundant branch opts
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Redundant branch opts [no changes]
*************** Starting PHASE Optimize Valnum CSEs
CONST CSE is enabled
Standard CSE Heuristic
Standard CSE Heuristic
Candidate CSE #01, key=K_0xffff41308000 in BB01, [cost= 3, size=12]:
N001 ( 3, 12) CSE #01 (use)[000009] H----+----- * CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
Candidate CSE #02, key=$180 in BB01, [cost=17, size=15]:
N002 ( 17, 15) CSE #02 (use)[000010] H-CXG+----- * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) CSE #01 (use)[000009] H----+----- arg0 in x0 \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
Candidate CSE #03, key=K_0xffbe99a53000 in BB01, [cost= 3, size=12]:
N003 ( 3, 12) CSE #03 (use)[000006] H----+----- * CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>] $c3
Blocks that generate CSE def/uses
BB01 cseGen = 000000000000003D CSE #01, CSE #02.c, CSE #03.c
Performing DataFlow for ValnumCSE's
After performing DataFlow for ValnumCSE's
BB01
in: 0000000000000000
gen: 000000000000003D CSE #01, CSE #02.c, CSE #03.c
out: 000000000000003D CSE #01, CSE #02.c, CSE #03.c
Labeling the CSEs with Use/Def information
BB01 [000003] Def of CSE #01 [weight=1]
BB01 [000004] Def of CSE #02 [weight=1]
BB01 [000000] Def of CSE #03 [weight=1]
BB01 [000009] Use of CSE #01 [weight=1] *** Now Live Across Call ***
BB01 [000010] Use of CSE #02 [weight=1]
BB01 [000006] Use of CSE #03 [weight=1]
************ Trees at start of optValnumCSE_Heuristic()
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
N006 ( 23, 29) [000005] -ACXG+----- * COMMA void $141
N002 ( 17, 15) CSE #02 (def)[000004] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) CSE #01 (def)[000003] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
N005 ( 6, 14) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
N004 ( 6, 14) [000001] I---G+----- \--* IND simd16 <l:$200, c:$240>
N003 ( 3, 12) CSE #03 (def)[000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
N006 ( 23, 29) [000011] -ACXG+----- * COMMA void $141
N002 ( 17, 15) CSE #02 (use)[000010] H-CXG+----- +--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) CSE #01 (use)[000009] H----+----- arg0 in x0 | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
N005 ( 6, 14) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
N004 ( 6, 14) [000007] I---G+----- \--* IND simd16 <l:$201, c:$241>
N003 ( 3, 12) CSE #03 (use)[000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>] $c3
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
N016 ( 22, 23) [000014] -----+----- * RETURN simd16 $VN.Void
N015 ( 21, 22) [000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert <l:$340, c:$341>
N006 ( 9, 8) [000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe <l:$202, c:$203>
N005 ( 8, 7) [000019] -----+----- | \--* MUL long <l:$284, c:$285>
N002 ( 2, 2) [000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar <l:$280, c:$281>
N001 ( 1, 1) [000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 <l:$200, c:$240>
N004 ( 2, 2) [000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar <l:$282, c:$283>
N003 ( 1, 1) [000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 <l:$201, c:$241>
N007 ( 1, 2) [000028] -----+-N--- +--* CNS_INT int 1 $43
N014 ( 10, 11) [000027] -----+----- \--* MUL long <l:$286, c:$287>
N010 ( 3, 4) [000024] -----+----- +--* HWINTRINSIC long ulong GetElement <l:$300, c:$301>
N008 ( 1, 1) [000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 (last use) <l:$200, c:$240>
N009 ( 1, 2) [000023] -----+----- | \--* CNS_INT int 1 $43
N013 ( 3, 4) [000026] -----+----- \--* HWINTRINSIC long ulong GetElement <l:$302, c:$303>
N011 ( 1, 1) [000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 (last use) <l:$201, c:$241>
N012 ( 1, 2) [000025] -----+----- \--* CNS_INT int 1 $43
-------------------------------------------------------------------------------------------------------------------
Standard CSE Heuristic
Aggressive CSE Promotion cutoff is 200.000000
Moderate CSE Promotion cutoff is 100.000000
enregCount is 2
Framesize estimate is 0x0000
We have a small frame
Sorted CSE candidates:
CSE #02, {$180, $140} useCnt=1: [def=100.000000, use=100.000000, cost= 17 ]
:: N002 ( 17, 15) CSE #02 (def)[000004] H-CXG+----- * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
CSE #01, {K_0xffff41308000} useCnt=1: [def=100.000000, use=100.000000, cost= 3, call]
:: N001 ( 3, 12) CSE #01 (def)[000003] H----+----- * CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
CSE #03, {K_0xffbe99a53000} useCnt=1: [def=100.000000, use=100.000000, cost= 3 ]
:: N003 ( 3, 12) CSE #03 (def)[000000] H----+----- * CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
Considering CSE #02 {$180, $140} [def=100.000000, use=100.000000, cost= 17 ]
CSE Expression :
N002 ( 17, 15) CSE #02 (def)[000004] H-CXG+----- * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) CSE #01 (def)[000003] H----+----- arg0 in x0 \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
Aggressive CSE Promotion (300.000000 >= 200.000000)
cseRefCnt=300.000000, aggressiveRefCnt=200.000000, moderateRefCnt=100.000000
defCnt=100.000000, useCnt=100.000000, cost=17, size=15
def_cost=1, use_cost=1, extra_no_cost=28, extra_yes_cost=0
CSE cost savings check (1728.000000 >= 200.000000) passes
Promoting CSE:
lvaGrabTemp returning 4 (V04 rat0) (a long lifetime temp) called for CSE #02: aggressive.
CSE #02 is single-def, so associated CSE temp V04 will be in SSA
New refCnts for V04: refCnt = 2, refCntWtd = 2
New refCnts for V04: refCnt = 3, refCntWtd = 3
CSE #02 def at [000004] replaced in BB01 with def of V04
ReMorphing args for 4.CALL:
Args for [000004].CALL after fgMorphArgs:
CallArg[[000003].CNS_INT long (By value), 1 reg: x0, isLate, processed]
OutgoingArgsStackSize is 0
optValnumCSE morphed tree:
N009 ( 24, 30) [000005] -ACXG+----- * COMMA void $141
N005 ( 18, 16) [000035] -ACXG------ +--* COMMA byref $1c0
N003 ( 17, 15) CSE #02 (def)[000033] DACXG------ | +--* STORE_LCL_VAR byref V04 cse0 d:1 $VN.Void
N002 ( 17, 15) [000004] H-CXG+----- | | \--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) CSE #01 (def)[000003] H----+----- arg0 in x0 | | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
N004 ( 1, 1) [000034] ----------- | \--* LCL_VAR byref V04 cse0 u:1 $1c0
N008 ( 6, 14) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
N007 ( 6, 14) [000001] I---G+----- \--* IND simd16 <l:$200, c:$240>
N006 ( 3, 12) CSE #03 (def)[000000] H----+----- \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
Working on the replacement of the CSE #02 use at [000010] in BB01
Unmark CSE use #01 at [000009]: 1 -> 0
optValnumCSE morphed tree:
N005 ( 7, 15) [000011] -A--G+----- * COMMA void $141
N001 ( 1, 1) [000036] ----------- +--* LCL_VAR byref V04 cse0 u:1 $180
N004 ( 6, 14) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
N003 ( 6, 14) [000007] I---G+----- \--* IND simd16 <l:$201, c:$241>
N002 ( 3, 12) CSE #03 (use)[000006] H----+----- \--* CNS_INT(h) long 0xffbe99a538a8 static Fseq[<unknown field>] $c3
Considering CSE #03 {K_0xffbe99a53000} [def=100.000000, use=100.000000, cost= 3 ]
CSE Expression :
N006 ( 3, 12) CSE #03 (def)[000000] H----+----- * CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
Aggressive CSE Promotion (300.000000 >= 200.000000)
cseRefCnt=300.000000, aggressiveRefCnt=200.000000, moderateRefCnt=100.000000
defCnt=100.000000, useCnt=100.000000, cost=3, size=12
def_cost=1, use_cost=1, extra_no_cost=22, extra_yes_cost=0
CSE cost savings check (322.000000 >= 200.000000) passes
Promoting CSE:
lvaGrabTemp returning 5 (V05 rat0) (a long lifetime temp) called for CSE #03: aggressive.
CSE #03 is single-def, so associated CSE temp V05 will be in SSA
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V05: refCnt = 3, refCntWtd = 3
We have shared Const CSE's and selected $c1 with a value of 0x0xffbe99a53888 as the base.
CSE #03 def at [000000] replaced in BB01 with def of V05
ReMorphing args for 4.CALL:
Args for [000004].CALL after fgMorphArgs:
CallArg[[000003].CNS_INT long (By value), 1 reg: x0, isLate, processed]
OutgoingArgsStackSize is 0
optValnumCSE morphed tree:
N012 ( 25, 31) [000005] -ACXG+----- * COMMA void $141
N005 ( 18, 16) [000035] -ACXG------ +--* COMMA byref $1c0
N003 ( 17, 15) CSE #02 (def)[000033] DACXG------ | +--* STORE_LCL_VAR byref V04 cse0 d:1 $VN.Void
N002 ( 17, 15) [000004] H-CXG+----- | | \--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) CSE #01 (def)[000003] H----+----- arg0 in x0 | | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
N004 ( 1, 1) [000034] ----------- | \--* LCL_VAR byref V04 cse0 u:1 $1c0
N011 ( 7, 15) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
N010 ( 7, 15) [000001] IA--G+----- \--* IND simd16 <l:$200, c:$240>
N009 ( 4, 13) [000039] -A--------- \--* COMMA long $c1
N007 ( 3, 12) CSE #03 (def)[000037] DA--------- +--* STORE_LCL_VAR long V05 cse1 d:1 $VN.Void
N006 ( 3, 12) [000000] H----+----- | \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
N008 ( 1, 1) [000038] ----------- \--* LCL_VAR long V05 cse1 u:1 $c1
Working on the replacement of the CSE #03 use at [000006] in BB01
optValnumCSE morphed tree:
N007 ( 5, 4) [000011] -A--G+----- * COMMA void $141
N001 ( 1, 1) [000036] ----------- +--* LCL_VAR byref V04 cse0 u:1 $180
N006 ( 4, 3) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
N005 ( 4, 3) [000007] I---G+----- \--* IND simd16 <l:$201, c:$241>
N004 ( 3, 4) [000042] -------N--- \--* ADD long $c3
N002 ( 1, 1) [000040] ----------- +--* LCL_VAR long V05 cse1 u:1 $c1
N003 ( 1, 2) [000041] ----------- \--* CNS_INT long 32
*************** Finishing PHASE Optimize Valnum CSEs
Trees after Optimize Valnum CSEs
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..010) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [000..010) (return), preds={} succs={}
***** BB01 [0000]
STMT00002 ( 0x000[E-] ... ??? )
N012 ( 25, 31) [000005] -ACXG+----- * COMMA void $141
N005 ( 18, 16) [000035] -ACXG------ +--* COMMA byref $1c0
N003 ( 17, 15) [000033] DACXG------ | +--* STORE_LCL_VAR byref V04 cse0 d:1 $VN.Void
N002 ( 17, 15) [000004] H-CXG+----- | | \--* CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) [000003] H----+----- arg0 in x0 | | \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
N004 ( 1, 1) [000034] ----------- | \--* LCL_VAR byref V04 cse0 u:1 $1c0
N011 ( 7, 15) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
N010 ( 7, 15) [000001] IA--G+----- \--* IND simd16 <l:$200, c:$240>
N009 ( 4, 13) [000039] -A--------- \--* COMMA long $c1
N007 ( 3, 12) [000037] DA--------- +--* STORE_LCL_VAR long V05 cse1 d:1 $VN.Void
N006 ( 3, 12) [000000] H----+----- | \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
N008 ( 1, 1) [000038] ----------- \--* LCL_VAR long V05 cse1 u:1 $c1
***** BB01 [0000]
STMT00003 ( 0x000[E-] ... ??? )
N007 ( 5, 4) [000011] -A--G+----- * COMMA void $141
N001 ( 1, 1) [000036] ----------- +--* LCL_VAR byref V04 cse0 u:1 $180
N006 ( 4, 3) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
N005 ( 4, 3) [000007] I---G+----- \--* IND simd16 <l:$201, c:$241>
N004 ( 3, 4) [000042] -------N--- \--* ADD long $c3
N002 ( 1, 1) [000040] ----------- +--* LCL_VAR long V05 cse1 u:1 $c1
N003 ( 1, 2) [000041] ----------- \--* CNS_INT long 32
***** BB01 [0000]
STMT00001 ( 0x000[E-] ... ??? )
N016 ( 22, 23) [000014] -----+----- * RETURN simd16 $VN.Void
N015 ( 21, 22) [000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert <l:$340, c:$341>
N006 ( 9, 8) [000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe <l:$202, c:$203>
N005 ( 8, 7) [000019] -----+----- | \--* MUL long <l:$284, c:$285>
N002 ( 2, 2) [000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar <l:$280, c:$281>
N001 ( 1, 1) [000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 <l:$200, c:$240>
N004 ( 2, 2) [000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar <l:$282, c:$283>
N003 ( 1, 1) [000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 <l:$201, c:$241>
N007 ( 1, 2) [000028] -----+-N--- +--* CNS_INT int 1 $43
N014 ( 10, 11) [000027] -----+----- \--* MUL long <l:$286, c:$287>
N010 ( 3, 4) [000024] -----+----- +--* HWINTRINSIC long ulong GetElement <l:$300, c:$301>
N008 ( 1, 1) [000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 (last use) <l:$200, c:$240>
N009 ( 1, 2) [000023] -----+----- | \--* CNS_INT int 1 $43
N013 ( 3, 4) [000026] -----+----- \--* HWINTRINSIC long ulong GetElement <l:$302, c:$303>
N011 ( 1, 1) [000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 (last use) <l:$201, c:$241>
N012 ( 1, 2) [000025] -----+----- \--* CNS_INT int 1 $43
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Assertion prop
*************** Finishing PHASE Assertion prop [no changes]
*************** Starting PHASE Optimize index checks
*************** Finishing PHASE Optimize index checks [no changes]
*************** Starting PHASE Optimize Induction Variables
*************** In optInductionVariables()
Skipping since this method has no natural loops
*************** Finishing PHASE Optimize Induction Variables [no changes]
*************** Starting PHASE VN-based dead store removal
*************** Finishing PHASE VN-based dead store removal [no changes]
*************** Starting PHASE VN based intrinsic expansion
*************** Finishing PHASE VN based intrinsic expansion [no changes]
*************** Starting PHASE Stress gtSplitTree
*************** Finishing PHASE Stress gtSplitTree [no changes]
*************** Starting PHASE Expand casts
*************** Finishing PHASE Expand casts [no changes]
*************** Starting PHASE Expand runtime lookups
*************** Finishing PHASE Expand runtime lookups [no changes]
*************** Starting PHASE Expand static init
Expanding static initialization for 'System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]', call: [000004] in BB01
New Basic Block BB02 [0002] created.
setting likelihood of BB01 -> BB02 to 1
New Basic Block BB03 [0003] created.
New Basic Block BB04 [0004] created.
MorphCopyBlock:
PrepareDst for [000030] have found a local var V02.
block store to morph:
N011 ( 7, 15) [000030] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
N010 ( 7, 15) [000001] IA--G+----- \--* IND simd16 <l:$200, c:$240>
N009 ( 4, 13) [000039] -A--------- \--* COMMA long $c1
N007 ( 3, 12) [000037] DA--------- +--* STORE_LCL_VAR long V05 cse1 d:1 $VN.Void
N006 ( 3, 12) [000000] H----+----- | \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
N008 ( 1, 1) [000038] ----------- \--* LCL_VAR long V05 cse1 u:1 $c1
this requires a CopyBlock.
MorphCopyBlock (after):
N011 ( 7, 15) [000030] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
N010 ( 7, 15) [000001] IA--G+----- \--* IND simd16 <l:$200, c:$240>
N009 ( 4, 13) [000039] -A--------- \--* COMMA long $c1
N007 ( 3, 12) [000037] DA--------- +--* STORE_LCL_VAR long V05 cse1 d:1 $VN.Void
N006 ( 3, 12) [000000] H----+----- | \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
N008 ( 1, 1) [000038] ----------- \--* LCL_VAR long V05 cse1 u:1 $c1
setting likelihood of BB04 -> BB02 to 1
setting likelihood of BB03 -> BB02 to 1
setting likelihood of BB03 -> BB04 to 0
Compacting BB03 into BB01:
*************** In fgDebugCheckBBlist
*************** Before renumbering the basic blocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB02(1),BB04(0) ( cond ) i hascall
BB04 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) rare internal
BB02 [0002] 2 BB01,BB04 1 [000..???) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB04 to BB02
Renumber BB02 to BB03
*************** After renumbering the basic blocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB03(1),BB02(0) ( cond ) i hascall
BB02 [0004] 1 BB01 0 [???..???)-> BB03(1) (always) rare internal
BB03 [0002] 2 BB01,BB02 1 [000..???) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 2, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
*************** Finishing PHASE Expand static init
Trees after Expand static init
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB03(1),BB02(0) ( cond ) i hascall
BB02 [0004] 1 BB01 0 [???..???)-> BB03(1) (always) rare internal
BB03 [0002] 2 BB01,BB02 1 [000..???) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [???..???) -> BB03(1),BB02(0) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00004 ( 0x000[E-] ... ??? )
N007 ( 12, 22) [000049] ----GO----- * JTRUE void
N006 ( 10, 20) [000048] J---GO----- \--* EQ int
N004 ( 8, 17) [000046] ----GO----- +--* AND int
N002 ( 6, 14) [000044] V---GO----- | +--* IND int
N001 ( 3, 12) [000043] H---------- | | \--* CNS_INT(h) long 0xffff41308f10 global ptr
N003 ( 1, 2) [000045] ----------- | \--* CNS_INT int 1
N005 ( 1, 2) [000047] ----------- \--* CNS_INT int 1
------------ BB02 [0004] [???..???) -> BB03(1) (always), preds={BB01} succs={BB03}
***** BB02 [0004]
STMT00005 ( 0x000[E-] ... ??? )
N002 ( 17, 15) [000004] H-CXG+----- * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) [000003] H----+----- arg0 in x0 \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
------------ BB03 [0002] [000..???) (return), preds={BB01,BB02} succs={}
***** BB03 [0002]
STMT00002 ( 0x000[E-] ... ??? )
N011 ( 11, 28) [000005] -A--G+----- * COMMA void $141
N004 ( 4, 13) [000035] -A--G------ +--* COMMA byref $1c0
N002 ( 3, 12) [000033] DA--G------ | +--* STORE_LCL_VAR byref V04 cse0 d:1 $VN.Void
N001 ( 3, 12) [000050] H---------- | | \--* CNS_INT(h) long 0xffbf30000748 static
N003 ( 1, 1) [000034] ----------- | \--* LCL_VAR byref V04 cse0 u:1 $1c0
N010 ( 7, 15) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
N009 ( 7, 15) [000001] IA--G+----- \--* IND simd16 <l:$200, c:$240>
N008 ( 4, 13) [000039] -A--------- \--* COMMA long $c1
N006 ( 3, 12) [000037] DA--------- +--* STORE_LCL_VAR long V05 cse1 d:1 $VN.Void
N005 ( 3, 12) [000000] H----+----- | \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
N007 ( 1, 1) [000038] ----------- \--* LCL_VAR long V05 cse1 u:1 $c1
***** BB03 [0002]
STMT00003 ( 0x000[E-] ... ??? )
N007 ( 5, 4) [000011] -A--G+----- * COMMA void $141
N001 ( 1, 1) [000036] ----------- +--* LCL_VAR byref V04 cse0 u:1 $180
N006 ( 4, 3) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
N005 ( 4, 3) [000007] I---G+----- \--* IND simd16 <l:$201, c:$241>
N004 ( 3, 4) [000042] -------N--- \--* ADD long $c3
N002 ( 1, 1) [000040] ----------- +--* LCL_VAR long V05 cse1 u:1 $c1
N003 ( 1, 2) [000041] ----------- \--* CNS_INT long 32
***** BB03 [0002]
STMT00001 ( 0x000[E-] ... ??? )
N016 ( 22, 23) [000014] -----+----- * RETURN simd16 $VN.Void
N015 ( 21, 22) [000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert <l:$340, c:$341>
N006 ( 9, 8) [000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe <l:$202, c:$203>
N005 ( 8, 7) [000019] -----+----- | \--* MUL long <l:$284, c:$285>
N002 ( 2, 2) [000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar <l:$280, c:$281>
N001 ( 1, 1) [000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 <l:$200, c:$240>
N004 ( 2, 2) [000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar <l:$282, c:$283>
N003 ( 1, 1) [000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 <l:$201, c:$241>
N007 ( 1, 2) [000028] -----+-N--- +--* CNS_INT int 1 $43
N014 ( 10, 11) [000027] -----+----- \--* MUL long <l:$286, c:$287>
N010 ( 3, 4) [000024] -----+----- +--* HWINTRINSIC long ulong GetElement <l:$300, c:$301>
N008 ( 1, 1) [000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 (last use) <l:$200, c:$240>
N009 ( 1, 2) [000023] -----+----- | \--* CNS_INT int 1 $43
N013 ( 3, 4) [000026] -----+----- \--* HWINTRINSIC long ulong GetElement <l:$302, c:$303>
N011 ( 1, 1) [000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 (last use) <l:$201, c:$241>
N012 ( 1, 2) [000025] -----+----- \--* CNS_INT int 1 $43
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Expand TLS access
Nothing to expand.
*************** Finishing PHASE Expand TLS access [no changes]
*************** Starting PHASE Insert GC Polls
*************** Finishing PHASE Insert GC Polls [no changes]
*************** Starting PHASE Create throw helper blocks
*************** Finishing PHASE Create throw helper blocks [no changes]
*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
optimized 0 BBJ_COND cases, 0 BBJ_RETURN cases in 1 passes
*************** Finishing PHASE Optimize bools
Trees after Optimize bools
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB03(1),BB02(0) ( cond ) i hascall
BB02 [0004] 1 BB01 0 [???..???)-> BB03(1) (always) rare internal
BB03 [0002] 2 BB01,BB02 1 [000..???) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [???..???) -> BB03(1),BB02(0) (cond), preds={} succs={BB02,BB03}
***** BB01 [0000]
STMT00004 ( 0x000[E-] ... ??? )
N007 ( 12, 22) [000049] ----GO----- * JTRUE void
N006 ( 10, 20) [000048] J---GO----- \--* EQ int
N004 ( 8, 17) [000046] ----GO----- +--* AND int
N002 ( 6, 14) [000044] V---GO----- | +--* IND int
N001 ( 3, 12) [000043] H---------- | | \--* CNS_INT(h) long 0xffff41308f10 global ptr
N003 ( 1, 2) [000045] ----------- | \--* CNS_INT int 1
N005 ( 1, 2) [000047] ----------- \--* CNS_INT int 1
------------ BB02 [0004] [???..???) -> BB03(1) (always), preds={BB01} succs={BB03}
***** BB02 [0004]
STMT00005 ( 0x000[E-] ... ??? )
N002 ( 17, 15) [000004] H-CXG+----- * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) [000003] H----+----- arg0 in x0 \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
------------ BB03 [0002] [000..???) (return), preds={BB01,BB02} succs={}
***** BB03 [0002]
STMT00002 ( 0x000[E-] ... ??? )
N011 ( 11, 28) [000005] -A--G+----- * COMMA void $141
N004 ( 4, 13) [000035] -A--G------ +--* COMMA byref $1c0
N002 ( 3, 12) [000033] DA--G------ | +--* STORE_LCL_VAR byref V04 cse0 d:1 $VN.Void
N001 ( 3, 12) [000050] H---------- | | \--* CNS_INT(h) long 0xffbf30000748 static
N003 ( 1, 1) [000034] ----------- | \--* LCL_VAR byref V04 cse0 u:1 $1c0
N010 ( 7, 15) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
N009 ( 7, 15) [000001] IA--G+----- \--* IND simd16 <l:$200, c:$240>
N008 ( 4, 13) [000039] -A--------- \--* COMMA long $c1
N006 ( 3, 12) [000037] DA--------- +--* STORE_LCL_VAR long V05 cse1 d:1 $VN.Void
N005 ( 3, 12) [000000] H----+----- | \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
N007 ( 1, 1) [000038] ----------- \--* LCL_VAR long V05 cse1 u:1 $c1
***** BB03 [0002]
STMT00003 ( 0x000[E-] ... ??? )
N007 ( 5, 4) [000011] -A--G+----- * COMMA void $141
N001 ( 1, 1) [000036] ----------- +--* LCL_VAR byref V04 cse0 u:1 $180
N006 ( 4, 3) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
N005 ( 4, 3) [000007] I---G+----- \--* IND simd16 <l:$201, c:$241>
N004 ( 3, 4) [000042] -------N--- \--* ADD long $c3
N002 ( 1, 1) [000040] ----------- +--* LCL_VAR long V05 cse1 u:1 $c1
N003 ( 1, 2) [000041] ----------- \--* CNS_INT long 32
***** BB03 [0002]
STMT00001 ( 0x000[E-] ... ??? )
N016 ( 22, 23) [000014] -----+----- * RETURN simd16 $VN.Void
N015 ( 21, 22) [000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert <l:$340, c:$341>
N006 ( 9, 8) [000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe <l:$202, c:$203>
N005 ( 8, 7) [000019] -----+----- | \--* MUL long <l:$284, c:$285>
N002 ( 2, 2) [000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar <l:$280, c:$281>
N001 ( 1, 1) [000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 <l:$200, c:$240>
N004 ( 2, 2) [000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar <l:$282, c:$283>
N003 ( 1, 1) [000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 <l:$201, c:$241>
N007 ( 1, 2) [000028] -----+-N--- +--* CNS_INT int 1 $43
N014 ( 10, 11) [000027] -----+----- \--* MUL long <l:$286, c:$287>
N010 ( 3, 4) [000024] -----+----- +--* HWINTRINSIC long ulong GetElement <l:$300, c:$301>
N008 ( 1, 1) [000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 (last use) <l:$200, c:$240>
N009 ( 1, 2) [000023] -----+----- | \--* CNS_INT int 1 $43
N013 ( 3, 4) [000026] -----+----- \--* HWINTRINSIC long ulong GetElement <l:$302, c:$303>
N011 ( 1, 1) [000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 (last use) <l:$201, c:$241>
N012 ( 1, 2) [000025] -----+----- \--* CNS_INT int 1 $43
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE If conversion
*************** Finishing PHASE If conversion [no changes]
*************** Starting PHASE Optimize layout
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB03(1),BB02(0) ( cond ) i hascall
BB02 [0004] 1 BB01 0 [???..???)-> BB03(1) (always) rare internal
BB03 [0002] 2 BB01,BB02 1 [000..???) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** In fgDoReversePostOrderLayout()
Initial BasicBlocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB03(1),BB02(0) ( cond ) i hascall
BB02 [0004] 1 BB01 0 [???..???)-> BB03(1) (always) rare internal
BB03 [0002] 2 BB01,BB02 1 [000..???) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgMoveHotJumps()
Initial BasicBlocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB03(1),BB02(0) ( cond ) i hascall
BB02 [0004] 1 BB01 0 [???..???)-> BB03(1) (always) rare internal
BB03 [0002] 2 BB01,BB02 1 [000..???) (return) i hascall
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgMoveColdBlocks()
Initial BasicBlocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB03(1),BB02(0) ( cond ) i hascall
BB03 [0002] 2 BB01,BB02 1 [000..???) (return) i hascall
BB02 [0004] 1 BB01 0 [???..???)-> BB03(1) (always) rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Before renumbering the basic blocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB03(1),BB02(0) ( cond ) i hascall
BB03 [0002] 2 BB01,BB02 1 [000..???) (return) i hascall
BB02 [0004] 1 BB01 0 [???..???)-> BB03(1) (always) rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB02 to BB03
*************** After renumbering the basic blocks
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB02(1),BB03(0) ( cond ) i hascall
BB02 [0002] 2 BB01,BB03 1 [000..???) (return) i hascall
BB03 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 3, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB02(1),BB03(0) ( cond ) i hascall
BB02 [0002] 2 BB01,BB03 1 [000..???) (return) i hascall
BB03 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize layout
Trees after Optimize layout
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB02(1),BB03(0) ( cond ) i hascall
BB02 [0002] 2 BB01,BB03 1 [000..???) (return) i hascall
BB03 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [???..???) -> BB02(1),BB03(0) (cond), preds={} succs={BB03,BB02}
***** BB01 [0000]
STMT00004 ( 0x000[E-] ... ??? )
N007 ( 12, 22) [000049] ----GO----- * JTRUE void
N006 ( 10, 20) [000048] J---GO----- \--* EQ int
N004 ( 8, 17) [000046] ----GO----- +--* AND int
N002 ( 6, 14) [000044] V---GO----- | +--* IND int
N001 ( 3, 12) [000043] H---------- | | \--* CNS_INT(h) long 0xffff41308f10 global ptr
N003 ( 1, 2) [000045] ----------- | \--* CNS_INT int 1
N005 ( 1, 2) [000047] ----------- \--* CNS_INT int 1
------------ BB02 [0002] [000..???) (return), preds={BB01,BB03} succs={}
***** BB02 [0002]
STMT00002 ( 0x000[E-] ... ??? )
N011 ( 11, 28) [000005] -A--G+----- * COMMA void $141
N004 ( 4, 13) [000035] -A--G------ +--* COMMA byref $1c0
N002 ( 3, 12) [000033] DA--G------ | +--* STORE_LCL_VAR byref V04 cse0 d:1 $VN.Void
N001 ( 3, 12) [000050] H---------- | | \--* CNS_INT(h) long 0xffbf30000748 static
N003 ( 1, 1) [000034] ----------- | \--* LCL_VAR byref V04 cse0 u:1 $1c0
N010 ( 7, 15) [000030] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
N009 ( 7, 15) [000001] IA--G+----- \--* IND simd16 <l:$200, c:$240>
N008 ( 4, 13) [000039] -A--------- \--* COMMA long $c1
N006 ( 3, 12) [000037] DA--------- +--* STORE_LCL_VAR long V05 cse1 d:1 $VN.Void
N005 ( 3, 12) [000000] H----+----- | \--* CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
N007 ( 1, 1) [000038] ----------- \--* LCL_VAR long V05 cse1 u:1 $c1
***** BB02 [0002]
STMT00003 ( 0x000[E-] ... ??? )
N007 ( 5, 4) [000011] -A--G+----- * COMMA void $141
N001 ( 1, 1) [000036] ----------- +--* LCL_VAR byref V04 cse0 u:1 $180
N006 ( 4, 3) [000031] DA--G+----- \--* STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
N005 ( 4, 3) [000007] I---G+----- \--* IND simd16 <l:$201, c:$241>
N004 ( 3, 4) [000042] -------N--- \--* ADD long $c3
N002 ( 1, 1) [000040] ----------- +--* LCL_VAR long V05 cse1 u:1 $c1
N003 ( 1, 2) [000041] ----------- \--* CNS_INT long 32
***** BB02 [0002]
STMT00001 ( 0x000[E-] ... ??? )
N016 ( 22, 23) [000014] -----+----- * RETURN simd16 $VN.Void
N015 ( 21, 22) [000029] -----+----- \--* HWINTRINSIC simd16 ulong Insert <l:$340, c:$341>
N006 ( 9, 8) [000020] -----+----- +--* HWINTRINSIC simd16 ulong CreateScalarUnsafe <l:$202, c:$203>
N005 ( 8, 7) [000019] -----+----- | \--* MUL long <l:$284, c:$285>
N002 ( 2, 2) [000017] -----+----- | +--* HWINTRINSIC long ulong ToScalar <l:$280, c:$281>
N001 ( 1, 1) [000015] -----+----- | | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 <l:$200, c:$240>
N004 ( 2, 2) [000018] -----+----- | \--* HWINTRINSIC long ulong ToScalar <l:$282, c:$283>
N003 ( 1, 1) [000016] -----+----- | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 <l:$201, c:$241>
N007 ( 1, 2) [000028] -----+-N--- +--* CNS_INT int 1 $43
N014 ( 10, 11) [000027] -----+----- \--* MUL long <l:$286, c:$287>
N010 ( 3, 4) [000024] -----+----- +--* HWINTRINSIC long ulong GetElement <l:$300, c:$301>
N008 ( 1, 1) [000021] -----+----- | +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 (last use) <l:$200, c:$240>
N009 ( 1, 2) [000023] -----+----- | \--* CNS_INT int 1 $43
N013 ( 3, 4) [000026] -----+----- \--* HWINTRINSIC long ulong GetElement <l:$302, c:$303>
N011 ( 1, 1) [000022] -----+----- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 (last use) <l:$201, c:$241>
N012 ( 1, 2) [000025] -----+----- \--* CNS_INT int 1 $43
------------ BB03 [0004] [???..???) -> BB02(1) (always), preds={BB01} succs={BB02}
***** BB03 [0004]
STMT00005 ( 0x000[E-] ... ??? )
N002 ( 17, 15) [000004] H-CXG+----- * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
N001 ( 3, 12) [000003] H----+----- arg0 in x0 \--* CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Recognize Switch
*************** Finishing PHASE Recognize Switch [no changes]
*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method
*************** Finishing PHASE Determine first cold block [no changes]
*************** Starting PHASE Rationalize IR
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB02(1),BB03(0) ( cond ) i LIR hascall
BB02 [0002] 2 BB01,BB03 1 [000..???) (return) i LIR hascall
BB03 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) LIR rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [???..???) -> BB02(1),BB03(0) (cond), preds={} succs={BB03,BB02}
[000051] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 3, 12) [000043] H---------- t43 = CNS_INT(h) long 0xffff41308f10 global ptr
/--* t43 long
N002 ( 6, 14) [000044] V---GO----- t44 = * IND int
N003 ( 1, 2) [000045] ----------- t45 = CNS_INT int 1
/--* t44 int
+--* t45 int
N004 ( 8, 17) [000046] ----GO----- t46 = * AND int
N005 ( 1, 2) [000047] ----------- t47 = CNS_INT int 1
/--* t46 int
+--* t47 int
N006 ( 10, 20) [000048] J---GO----- t48 = * EQ int
/--* t48 int
N007 ( 12, 22) [000049] ----GO----- * JTRUE void
------------ BB02 [0002] [000..???) (return), preds={BB01,BB03} succs={}
[000052] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 3, 12) [000050] H---------- t50 = CNS_INT(h) long 0xffbf30000748 static
/--* t50 long
N002 ( 3, 12) [000033] DA--G------ * STORE_LCL_VAR byref V04 cse0 d:1 $VN.Void
N005 ( 3, 12) [000000] H----+----- t0 = CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
/--* t0 long
N006 ( 3, 12) [000037] DA--------- * STORE_LCL_VAR long V05 cse1 d:1 $VN.Void
N007 ( 1, 1) [000038] ----------- t38 = LCL_VAR long V05 cse1 u:1 $c1
/--* t38 long
N009 ( 7, 15) [000001] IA--G+----- t1 = * IND simd16 <l:$200, c:$240>
/--* t1 simd16
N010 ( 7, 15) [000030] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
[000053] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N002 ( 1, 1) [000040] ----------- t40 = LCL_VAR long V05 cse1 u:1 $c1
N003 ( 1, 2) [000041] ----------- t41 = CNS_INT long 32
/--* t40 long
+--* t41 long
N004 ( 3, 4) [000042] -------N--- t42 = * ADD long $c3
/--* t42 long
N005 ( 4, 3) [000007] I---G+----- t7 = * IND simd16 <l:$201, c:$241>
/--* t7 simd16
N006 ( 4, 3) [000031] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
[000054] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000015] -----+----- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 <l:$200, c:$240>
/--* t15 simd16
N002 ( 2, 2) [000017] -----+----- t17 = * HWINTRINSIC long ulong ToScalar <l:$280, c:$281>
N003 ( 1, 1) [000016] -----+----- t16 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 <l:$201, c:$241>
/--* t16 simd16
N004 ( 2, 2) [000018] -----+----- t18 = * HWINTRINSIC long ulong ToScalar <l:$282, c:$283>
/--* t17 long
+--* t18 long
N005 ( 8, 7) [000019] -----+----- t19 = * MUL long <l:$284, c:$285>
/--* t19 long
N006 ( 9, 8) [000020] -----+----- t20 = * HWINTRINSIC simd16 ulong CreateScalarUnsafe <l:$202, c:$203>
N007 ( 1, 2) [000028] -----+-N--- t28 = CNS_INT int 1 $43
N008 ( 1, 1) [000021] -----+----- t21 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 (last use) <l:$200, c:$240>
N009 ( 1, 2) [000023] -----+----- t23 = CNS_INT int 1 $43
/--* t21 simd16
+--* t23 int
N010 ( 3, 4) [000024] -----+----- t24 = * HWINTRINSIC long ulong GetElement <l:$300, c:$301>
N011 ( 1, 1) [000022] -----+----- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 (last use) <l:$201, c:$241>
N012 ( 1, 2) [000025] -----+----- t25 = CNS_INT int 1 $43
/--* t22 simd16
+--* t25 int
N013 ( 3, 4) [000026] -----+----- t26 = * HWINTRINSIC long ulong GetElement <l:$302, c:$303>
/--* t24 long
+--* t26 long
N014 ( 10, 11) [000027] -----+----- t27 = * MUL long <l:$286, c:$287>
/--* t20 simd16
+--* t28 int
+--* t27 long
N015 ( 21, 22) [000029] -----+----- t29 = * HWINTRINSIC simd16 ulong Insert <l:$340, c:$341>
/--* t29 simd16
N016 ( 22, 23) [000014] -----+----- * RETURN simd16 $VN.Void
------------ BB03 [0004] [???..???) -> BB02(1) (always), preds={BB01} succs={BB02}
[000055] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 3, 12) [000003] H----+----- t3 = CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
/--* t3 long arg0 in x0
N002 ( 17, 15) [000004] H-CXG+----- u4 = * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Lowering nodeinfo
..could not turn [000044] or [000045] into a def of flags, bailing
Lowering JTRUE:
N001 ( 3, 12) [000043] H---------- t43 = CNS_INT(h) long 0xffff41308f10 global ptr
/--* t43 long
N002 ( 6, 14) [000044] V---GO----- t44 = * IND int
N003 ( 1, 2) [000045] -c--------- t45 = CNS_INT int 1
/--* t44 int
+--* t45 int
N006 ( 10, 20) [000048] J---GO----- t48 = * TEST_NE int
/--* t48 int
N007 ( 12, 22) [000049] ----GO----- * JTRUE void
Lowered to JTEST
lowering store lcl var/field (before):
N001 ( 3, 12) [000050] H---------- t50 = CNS_INT(h) long 0xffbf30000748 static
/--* t50 long
N002 ( 3, 12) [000033] DA--G------ * STORE_LCL_VAR byref V04 cse0 d:1 $VN.Void
lowering store lcl var/field (after):
N001 ( 3, 12) [000050] H---------- t50 = CNS_INT(h) long 0xffbf30000748 static
/--* t50 long
N002 ( 3, 12) [000033] DA--G------ * STORE_LCL_VAR byref V04 cse0 d:1 $VN.Void
lowering store lcl var/field (before):
N005 ( 3, 12) [000000] H----+----- t0 = CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
/--* t0 long
N006 ( 3, 12) [000037] DA--------- * STORE_LCL_VAR long V05 cse1 d:1 $VN.Void
lowering store lcl var/field (after):
N005 ( 3, 12) [000000] H----+----- t0 = CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
/--* t0 long
N006 ( 3, 12) [000037] DA--------- * STORE_LCL_VAR long V05 cse1 d:1 $VN.Void
lowering store lcl var/field (before):
N007 ( 1, 1) [000038] ----------- t38 = LCL_VAR long V05 cse1 u:1 $c1
/--* t38 long
N009 ( 7, 15) [000001] IA--G+----- t1 = * IND simd16 <l:$200, c:$240>
/--* t1 simd16
N010 ( 7, 15) [000030] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
lowering store lcl var/field (after):
N007 ( 1, 1) [000038] ----------- t38 = LCL_VAR long V05 cse1 u:1 $c1
/--* t38 long
N009 ( 7, 15) [000001] IA--G+----- t1 = * IND simd16 <l:$200, c:$240>
/--* t1 simd16
N010 ( 7, 15) [000030] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
Notify VM instruction set (ArmBase_Arm64) must be supported.
Addressing mode:
Base
N002 ( 1, 1) [000040] ----------- * LCL_VAR long V05 cse1 u:1 $c1
+ 32
Removing unused node:
N003 ( 1, 2) [000041] -c--------- * CNS_INT long 32
New addressing mode node:
N004 ( 3, 4) [000042] -------N--- * LEA(b+32) long
[000007] and [000001] are indirs off the same base with offsets +032 and +000
..but at non-adjacent offset
lowering store lcl var/field (before):
N002 ( 1, 1) [000040] ----------- t40 = LCL_VAR long V05 cse1 u:1 $c1
/--* t40 long
N004 ( 3, 4) [000042] -c-----N--- t42 = * LEA(b+32) long
/--* t42 long
N005 ( 4, 3) [000007] I---G+----- t7 = * IND simd16 <l:$201, c:$241>
/--* t7 simd16
N006 ( 4, 3) [000031] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
lowering store lcl var/field (after):
N002 ( 1, 1) [000040] ----------- t40 = LCL_VAR long V05 cse1 u:1 $c1
/--* t40 long
N004 ( 3, 4) [000042] -c-----N--- t42 = * LEA(b+32) long
/--* t42 long
N005 ( 4, 3) [000007] I---G+----- t7 = * IND simd16 <l:$201, c:$241>
/--* t7 simd16
N006 ( 4, 3) [000031] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
lowering return node
N016 ( 22, 23) [000014] -----+----- * RETURN simd16 $VN.Void
============
lowering call (before):
N001 ( 3, 12) [000003] H----+----- t3 = CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
/--* t3 long arg0 in x0
N002 ( 17, 15) [000004] H-CXG+----- u4 = * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
args:
======
late:
======
lowering arg : N001 ( 3, 12) [000003] H----+----- * CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
new node is : [000058] ----------- * PUTARG_REG long REG x0
lowering call (after):
N001 ( 3, 12) [000003] H----+----- t3 = CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
/--* t3 long
[000058] ----------- t58 = * PUTARG_REG long REG x0
/--* t58 long arg0 in x0
N002 ( 17, 15) [000004] H-CXG+----- u4 = * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
Lower has completed modifying nodes.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB02(1),BB03(0) ( cond ) i LIR hascall
BB02 [0002] 2 BB01,BB03 1 [000..???) (return) i LIR hascall
BB03 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) LIR rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [???..???) -> BB02(1),BB03(0) (cond), preds={} succs={BB03,BB02}
[000051] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 3, 12) [000043] H---------- t43 = CNS_INT(h) long 0xffff41308f10 global ptr
/--* t43 long
N002 ( 6, 14) [000044] V---GO----- t44 = * IND int
N003 ( 1, 2) [000045] -c--------- t45 = CNS_INT int 1
/--* t44 int
+--* t45 int
N007 ( 12, 22) [000049] ----GO----- * JTEST void
------------ BB02 [0002] [000..???) (return), preds={BB01,BB03} succs={}
[000052] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 3, 12) [000050] H---------- t50 = CNS_INT(h) long 0xffbf30000748 static
/--* t50 long
N002 ( 3, 12) [000033] DA--G------ * STORE_LCL_VAR byref V04 cse0 d:1 $VN.Void
N005 ( 3, 12) [000000] H----+----- t0 = CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
/--* t0 long
N006 ( 3, 12) [000037] DA--------- * STORE_LCL_VAR long V05 cse1 d:1 $VN.Void
N007 ( 1, 1) [000038] ----------- t38 = LCL_VAR long V05 cse1 u:1 $c1
/--* t38 long
N009 ( 7, 15) [000001] IA--G+----- t1 = * IND simd16 <l:$200, c:$240>
/--* t1 simd16
N010 ( 7, 15) [000030] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
[000053] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N002 ( 1, 1) [000040] ----------- t40 = LCL_VAR long V05 cse1 u:1 $c1
/--* t40 long
N004 ( 3, 4) [000042] -c-----N--- t42 = * LEA(b+32) long
/--* t42 long
N005 ( 4, 3) [000007] I---G+----- t7 = * IND simd16 <l:$201, c:$241>
/--* t7 simd16
N006 ( 4, 3) [000031] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
[000054] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000015] -----+----- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 <l:$200, c:$240>
/--* t15 simd16
N002 ( 2, 2) [000017] -----+----- t17 = * HWINTRINSIC long ulong ToScalar <l:$280, c:$281>
N003 ( 1, 1) [000016] -----+----- t16 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 <l:$201, c:$241>
/--* t16 simd16
N004 ( 2, 2) [000018] -----+----- t18 = * HWINTRINSIC long ulong ToScalar <l:$282, c:$283>
/--* t17 long
+--* t18 long
N005 ( 8, 7) [000019] -----+----- t19 = * MUL long <l:$284, c:$285>
/--* t19 long
N006 ( 9, 8) [000020] -----+----- t20 = * HWINTRINSIC simd16 ulong CreateScalarUnsafe <l:$202, c:$203>
N007 ( 1, 2) [000028] -c---+-N--- t28 = CNS_INT int 1 $43
N008 ( 1, 1) [000021] -----+----- t21 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 (last use) <l:$200, c:$240>
N009 ( 1, 2) [000023] -c---+----- t23 = CNS_INT int 1 $43
/--* t21 simd16
+--* t23 int
N010 ( 3, 4) [000024] -----+----- t24 = * HWINTRINSIC long ulong GetElement <l:$300, c:$301>
N011 ( 1, 1) [000022] -----+----- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 (last use) <l:$201, c:$241>
N012 ( 1, 2) [000025] -c---+----- t25 = CNS_INT int 1 $43
/--* t22 simd16
+--* t25 int
N013 ( 3, 4) [000026] -----+----- t26 = * HWINTRINSIC long ulong GetElement <l:$302, c:$303>
/--* t24 long
+--* t26 long
N014 ( 10, 11) [000027] -----+----- t27 = * MUL long <l:$286, c:$287>
/--* t20 simd16
+--* t28 int
+--* t27 long
N015 ( 21, 22) [000029] -----+----- t29 = * HWINTRINSIC simd16 ulong Insert <l:$340, c:$341>
/--* t29 simd16
N016 ( 22, 23) [000014] -----+----- * RETURN simd16 $VN.Void
------------ BB03 [0004] [???..???) -> BB02(1) (always), preds={BB01} succs={BB02}
[000055] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 3, 12) [000003] H----+----- t3 = CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
/--* t3 long
[000058] ----------- t58 = * PUTARG_REG long REG x0
/--* t58 long arg0 in x0
N002 ( 17, 15) [000004] H-CXG+----- u4 = * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V04: refCnt = 1, refCntWtd = 1
New refCnts for V05: refCnt = 1, refCntWtd = 1
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 1, refCntWtd = 2
New refCnts for V05: refCnt = 3, refCntWtd = 3
New refCnts for V03: refCnt = 1, refCntWtd = 2
New refCnts for V02: refCnt = 2, refCntWtd = 4
New refCnts for V03: refCnt = 2, refCntWtd = 4
New refCnts for V02: refCnt = 3, refCntWtd = 6
New refCnts for V03: refCnt = 3, refCntWtd = 6
*** lvaComputeRefCounts -- implicit counts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 this ref this class-hnd single-def <System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]>
; V01 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
; V02 tmp1 simd16 HFA(simd16) "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ulong]>
; V03 tmp2 simd16 HFA(simd16) "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ulong]>
; V04 cse0 byref "CSE #02: aggressive"
; V05 cse1 long "CSE #03: aggressive"
In fgLocalVarLivenessInit
Local V01 should not be enregistered because: struct size does not match reg size
Tracked variable (4 out of 6) table:
V05 cse1 [ long]: refCnt = 3, refCntWtd = 3
V04 cse0 [ byref]: refCnt = 1, refCntWtd = 1
V02 tmp1 [simd16]: refCnt = 3, refCntWtd = 6
V03 tmp2 [simd16]: refCnt = 3, refCntWtd = 6
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={} + ByrefExposed + GcHeap
DEF(0)={} + ByrefExposed + GcHeap
BB02 USE(0)={ } + ByrefExposed + GcHeap
DEF(4)={V05 V04 V02 V03}
BB03 USE(0)={} + ByrefExposed + GcHeap
DEF(0)={} + ByrefExposed* + GcHeap*
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB02 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={}
BB03 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Removing dead local store:
N002 ( 3, 12) [000033] DA--G------ * STORE_LCL_VAR byref V04 cse0 d:1 (last use) $VN.Void
Removing dead node:
N001 ( 3, 12) [000050] H---------- * CNS_INT(h) long 0xffbf30000748 static
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB02(1),BB03(0) ( cond ) i LIR hascall
BB02 [0002] 2 BB01,BB03 1 [000..???) (return) i LIR hascall
BB03 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) LIR rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V05: refCnt = 1, refCntWtd = 1
New refCnts for V05: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 1, refCntWtd = 2
New refCnts for V05: refCnt = 3, refCntWtd = 3
New refCnts for V03: refCnt = 1, refCntWtd = 2
New refCnts for V02: refCnt = 2, refCntWtd = 4
New refCnts for V03: refCnt = 2, refCntWtd = 4
New refCnts for V02: refCnt = 3, refCntWtd = 6
New refCnts for V03: refCnt = 3, refCntWtd = 6
*** lvaComputeRefCounts -- implicit counts ***
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB02(1),BB03(0) ( cond ) i LIR hascall
BB02 [0002] 2 BB01,BB03 1 [000..???) (return) i LIR hascall
BB03 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) LIR rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [???..???) -> BB02(1),BB03(0) (cond), preds={} succs={BB03,BB02}
[000051] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 3, 12) [000043] H---------- t43 = CNS_INT(h) long 0xffff41308f10 global ptr
/--* t43 long
N002 ( 6, 14) [000044] V---GO----- t44 = * IND int
N003 ( 1, 2) [000045] -c--------- t45 = CNS_INT int 1
/--* t44 int
+--* t45 int
N007 ( 12, 22) [000049] ----GO----- * JTEST void
------------ BB02 [0002] [000..???) (return), preds={BB01,BB03} succs={}
[000052] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N005 ( 3, 12) [000000] H----+----- t0 = CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] $c1
/--* t0 long
N006 ( 3, 12) [000037] DA--------- * STORE_LCL_VAR long V05 cse1 d:1 $VN.Void
N007 ( 1, 1) [000038] ----------- t38 = LCL_VAR long V05 cse1 u:1 $c1
/--* t38 long
N009 ( 7, 15) [000001] IA--G+----- t1 = * IND simd16 <l:$200, c:$240>
/--* t1 simd16
N010 ( 7, 15) [000030] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 $VN.Void
[000053] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N002 ( 1, 1) [000040] ----------- t40 = LCL_VAR long V05 cse1 u:1 (last use) $c1
/--* t40 long
N004 ( 3, 4) [000042] -c-----N--- t42 = * LEA(b+32) long
/--* t42 long
N005 ( 4, 3) [000007] I---G+----- t7 = * IND simd16 <l:$201, c:$241>
/--* t7 simd16
N006 ( 4, 3) [000031] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 $VN.Void
[000054] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 1, 1) [000015] -----+----- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 <l:$200, c:$240>
/--* t15 simd16
N002 ( 2, 2) [000017] -----+----- t17 = * HWINTRINSIC long ulong ToScalar <l:$280, c:$281>
N003 ( 1, 1) [000016] -----+----- t16 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 <l:$201, c:$241>
/--* t16 simd16
N004 ( 2, 2) [000018] -----+----- t18 = * HWINTRINSIC long ulong ToScalar <l:$282, c:$283>
/--* t17 long
+--* t18 long
N005 ( 8, 7) [000019] -----+----- t19 = * MUL long <l:$284, c:$285>
/--* t19 long
N006 ( 9, 8) [000020] -----+----- t20 = * HWINTRINSIC simd16 ulong CreateScalarUnsafe <l:$202, c:$203>
N007 ( 1, 2) [000028] -c---+-N--- t28 = CNS_INT int 1 $43
N008 ( 1, 1) [000021] -----+----- t21 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 (last use) <l:$200, c:$240>
N009 ( 1, 2) [000023] -c---+----- t23 = CNS_INT int 1 $43
/--* t21 simd16
+--* t23 int
N010 ( 3, 4) [000024] -----+----- t24 = * HWINTRINSIC long ulong GetElement <l:$300, c:$301>
N011 ( 1, 1) [000022] -----+----- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 (last use) <l:$201, c:$241>
N012 ( 1, 2) [000025] -c---+----- t25 = CNS_INT int 1 $43
/--* t22 simd16
+--* t25 int
N013 ( 3, 4) [000026] -----+----- t26 = * HWINTRINSIC long ulong GetElement <l:$302, c:$303>
/--* t24 long
+--* t26 long
N014 ( 10, 11) [000027] -----+----- t27 = * MUL long <l:$286, c:$287>
/--* t20 simd16
+--* t28 int
+--* t27 long
N015 ( 21, 22) [000029] -----+----- t29 = * HWINTRINSIC simd16 ulong Insert <l:$340, c:$341>
/--* t29 simd16
N016 ( 22, 23) [000014] -----+----- * RETURN simd16 $VN.Void
------------ BB03 [0004] [???..???) -> BB02(1) (always), preds={BB01} succs={BB02}
[000055] ----------- IL_OFFSET void INLRT @ 0x000[E-]
N001 ( 3, 12) [000003] H----+----- t3 = CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] $c0
/--* t3 long
[000058] ----------- t58 = * PUTARG_REG long REG x0
/--* t58 long arg0 in x0
N002 ( 17, 15) [000004] H-CXG+----- u4 = * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE $1c0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots [no changes]
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01
use: {}
def: {}
in: {}
out: {}
BB02
use: {}
def: {V02 V03 V04 V05}
in: {}
out: {}
BB03
use: {}
def: {}
in: {}
out: {}
Interval 0: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 0: (V02) simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 1: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 1: (V03) simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 2: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[]
Interval 2: (V05) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Aversions=[]
Interval 3: double RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 4: double RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = false, singleExit = true
; Decided to create an EBP based frame for ETW stackwalking (Temporary ARM64 force frame pointer)
*************** In lvaAssignFrameOffsets(REGALLOC_FRAME_LAYOUT)
Setting genSaveFpLrWithAllCalleeSavedRegisters to false
Pad V00 this, size=8, stkOffs=-0x97, pad=7
Assign V00 this, size=8, stkOffs=-0x9f
Pad V02 tmp1, size=16, stkOffs=-0xae, pad=15
Assign V02 tmp1, size=16, stkOffs=-0xbe
Pad V03 tmp2, size=16, stkOffs=-0xcd, pad=15
Assign V03 tmp2, size=16, stkOffs=-0xdd
Pad V05 cse1, size=8, stkOffs=-0xe4, pad=7
Assign V05 cse1, size=8, stkOffs=-0xec
Pad V04 cse0, size=8, stkOffs=-0xf3, pad=7
Assign V04 cse0, size=8, stkOffs=-0xfb
--- delta bump 304 for FP frame
--- virtual stack offset to actual stack offset delta is 304
-- V00 was -159, now 145
-- V01 was 0, now 304
-- V02 was -190, now 114
-- V03 was -221, now 83
-- V04 was -251, now 53
-- V05 was -236, now 68
compRsvdRegCheck
frame size = 304
compArgSize = 8
Returning true (ARM64)
Reserved REG_OPT_RSVD (xip1) due to large frame
TUPLE STYLE DUMP BEFORE LSRA
Start LSRA Block Sequence:
Current block: BB01
Succ block: BB03, Criteria: weight, Worklist: [BB03 ]
Succ block: BB02, Criteria: weight, Worklist: [BB02 BB03 ]
Current block: BB02
Current block: BB03
Final LSRA Block Sequence:
BB01 ( 1 ) critical-out
BB02 ( 1 ) critical-in
BB03 ( 0 )
BB01 [0000] [???..???) -> BB02(1),BB03(0) (cond), preds={} succs={BB03,BB02}
=====
N000. IL_OFFSET INLRT @ 0x000[E-]
N001. t43 = CNS_INT(h) 0xffff41308f10 global ptr
N002. t44 = IND ; t43
N003. CNS_INT 1
N007. JTEST ; t44
BB02 [0002] [000..???) (return), preds={BB01,BB03} succs={}
=====
N000. IL_OFFSET INLRT @ 0x000[E-]
N005. t0 = CNS_INT(h) 0xffbe99a53888 static Fseq[<unknown field>]
N006. V05(t37); t0
N007. V05(t38)
N009. t1 = IND ; t38
N010. V02(t30); t1
N000. IL_OFFSET INLRT @ 0x000[E-]
N002. V05(t40*)
N004. t42 = LEA(b+32); t40*
N005. t7 = IND ; t42
N006. V03(t31); t7
N000. IL_OFFSET INLRT @ 0x000[E-]
N001. V02(t15)
N002. t17 = HWINTRINSIC; t15
N003. V03(t16)
N004. t18 = HWINTRINSIC; t16
N005. t19 = MUL ; t17,t18
N006. t20 = HWINTRINSIC; t19
N007. CNS_INT 1
N008. V02(t21*)
N009. CNS_INT 1
N010. t24 = HWINTRINSIC; t21*
N011. V03(t22*)
N012. CNS_INT 1
N013. t26 = HWINTRINSIC; t22*
N014. t27 = MUL ; t24,t26
N015. t29 = HWINTRINSIC; t20,t27
N016. RETURN ; t29
BB03 [0004] [???..???) -> BB02(1) (always), preds={BB01} succs={BB02}
=====
N000. IL_OFFSET INLRT @ 0x000[E-]
N001. t3 = CNS_INT(h) 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
N000. t58 = PUTARG_REG; t3
N002. CALL help; t58
buildIntervals second part ========
Int arg V00 in reg x0
NEW BLOCK BB01
<RefPosition #0 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
DefList: { }
N003 (???,???) [000051] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA
DefList: { }
N005 ( 3, 12) [000043] H---------- * CNS_INT(h) long 0xffff41308f10 global ptr REG NA
Interval 5: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #1 @6 RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
DefList: { N005.t43. CNS_INT }
N007 ( 6, 14) [000044] V---GO----- * IND int REG NA
<RefPosition #2 @7 RefTypeUse <Ivl:5> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 6: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #3 @8 RefTypeDef <Ivl:6> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
DefList: { N007.t44. IND }
N009 ( 1, 2) [000045] -c--------- * CNS_INT int 1 REG NA
Contained
DefList: { N007.t44. IND }
N011 ( 12, 22) [000049] ----GO----- * JTEST void REG NA
<RefPosition #4 @11 RefTypeUse <Ivl:6> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
CHECKING LAST USES for BB01, liveout={}
==============================
use: {}
def: {}
NEW BLOCK BB02
Setting BB01 as the predecessor for determining incoming variable registers of BB02
<RefPosition #5 @13 RefTypeBB BB02 regmask=[] minReg=1 wt=100.00>
DefList: { }
N015 (???,???) [000052] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA
DefList: { }
N017 ( 3, 12) [000000] H----+----- * CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] REG NA $c1
Interval 7: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #6 @18 RefTypeDef <Ivl:7> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
DefList: { N017.t0. CNS_INT }
N019 ( 3, 12) [000037] DA--------- * STORE_LCL_VAR long V05 cse1 d:1 NA REG NA $VN.Void
<RefPosition #7 @19 RefTypeUse <Ivl:7> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Assigning related <V05/L2> to <I7>
<RefPosition #8 @20 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00>
DefList: { }
N021 ( 1, 1) [000038] ----------- * LCL_VAR long V05 cse1 u:1 NA REG NA $c1
DefList: { }
N023 ( 7, 15) [000001] IA--G+----- * IND simd16 REG NA <l:$200, c:$240>
<RefPosition #9 @23 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00>
Interval 8: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #10 @24 RefTypeDef <Ivl:8> IND BB02 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N023.t1. IND }
N025 ( 7, 15) [000030] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 NA REG NA $VN.Void
<RefPosition #11 @25 RefTypeUse <Ivl:8> BB02 regmask=[allFloat] minReg=1 last wt=100.00>
Assigning related <V02/L0> to <I8>
<RefPosition #12 @26 RefTypeDef <Ivl:0 V02> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
DefList: { }
N027 (???,???) [000053] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA
DefList: { }
N029 ( 1, 1) [000040] ----------- * LCL_VAR long V05 cse1 u:1 NA (last use) REG NA $c1
DefList: { }
N031 ( 3, 4) [000042] -c-----N--- * LEA(b+32) long REG NA
Contained
DefList: { }
N033 ( 4, 3) [000007] I---G+----- * IND simd16 REG NA <l:$201, c:$241>
<RefPosition #13 @33 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00>
Interval 9: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #14 @34 RefTypeDef <Ivl:9> IND BB02 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N033.t7. IND }
N035 ( 4, 3) [000031] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 NA REG NA $VN.Void
<RefPosition #15 @35 RefTypeUse <Ivl:9> BB02 regmask=[allFloat] minReg=1 last wt=100.00>
Assigning related <V03/L1> to <I9>
<RefPosition #16 @36 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
DefList: { }
N037 (???,???) [000054] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA
DefList: { }
N039 ( 1, 1) [000015] -----+----- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 NA REG NA <l:$200, c:$240>
DefList: { }
N041 ( 2, 2) [000017] -----+----- * HWINTRINSIC long ulong ToScalar REG NA <l:$280, c:$281>
<RefPosition #17 @41 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
Interval 10: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #18 @42 RefTypeDef <Ivl:10> HWINTRINSIC BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
DefList: { N041.t17. HWINTRINSIC }
N043 ( 1, 1) [000016] -----+----- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 NA REG NA <l:$201, c:$241>
DefList: { N041.t17. HWINTRINSIC }
N045 ( 2, 2) [000018] -----+----- * HWINTRINSIC long ulong ToScalar REG NA <l:$282, c:$283>
<RefPosition #19 @45 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
Interval 11: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #20 @46 RefTypeDef <Ivl:11> HWINTRINSIC BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
DefList: { N041.t17. HWINTRINSIC; N045.t18. HWINTRINSIC }
N047 ( 8, 7) [000019] -----+----- * MUL long REG NA <l:$284, c:$285>
<RefPosition #21 @47 RefTypeUse <Ivl:10> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #22 @47 RefTypeUse <Ivl:11> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 12: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #23 @48 RefTypeDef <Ivl:12> MUL BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
DefList: { N047.t19. MUL }
N049 ( 9, 8) [000020] -----+----- * HWINTRINSIC simd16 ulong CreateScalarUnsafe REG NA <l:$202, c:$203>
<RefPosition #24 @49 RefTypeUse <Ivl:12> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 13: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #25 @50 RefTypeDef <Ivl:13> HWINTRINSIC BB02 regmask=[allFloat] minReg=1 wt=400.00>
DefList: { N049.t20. HWINTRINSIC }
N051 ( 1, 2) [000028] -c---+-N--- * CNS_INT int 1 REG NA $43
Contained
DefList: { N049.t20. HWINTRINSIC }
N053 ( 1, 1) [000021] -----+----- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 NA (last use) REG NA <l:$200, c:$240>
DefList: { N049.t20. HWINTRINSIC }
N055 ( 1, 2) [000023] -c---+----- * CNS_INT int 1 REG NA $43
Contained
DefList: { N049.t20. HWINTRINSIC }
N057 ( 3, 4) [000024] -----+----- * HWINTRINSIC long ulong GetElement REG NA <l:$300, c:$301>
<RefPosition #26 @57 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
Interval 14: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #27 @58 RefTypeDef <Ivl:14> HWINTRINSIC BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
DefList: { N049.t20. HWINTRINSIC; N057.t24. HWINTRINSIC }
N059 ( 1, 1) [000022] -----+----- * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 NA (last use) REG NA <l:$201, c:$241>
DefList: { N049.t20. HWINTRINSIC; N057.t24. HWINTRINSIC }
N061 ( 1, 2) [000025] -c---+----- * CNS_INT int 1 REG NA $43
Contained
DefList: { N049.t20. HWINTRINSIC; N057.t24. HWINTRINSIC }
N063 ( 3, 4) [000026] -----+----- * HWINTRINSIC long ulong GetElement REG NA <l:$302, c:$303>
<RefPosition #28 @63 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
Interval 15: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #29 @64 RefTypeDef <Ivl:15> HWINTRINSIC BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
DefList: { N049.t20. HWINTRINSIC; N057.t24. HWINTRINSIC; N063.t26. HWINTRINSIC }
N065 ( 10, 11) [000027] -----+----- * MUL long REG NA <l:$286, c:$287>
<RefPosition #30 @65 RefTypeUse <Ivl:14> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #31 @65 RefTypeUse <Ivl:15> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 16: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #32 @66 RefTypeDef <Ivl:16> MUL BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
DefList: { N049.t20. HWINTRINSIC; N065.t27. MUL }
N067 ( 21, 22) [000029] -----+----- * HWINTRINSIC simd16 ulong Insert REG NA <l:$340, c:$341>
<RefPosition #33 @67 RefTypeUse <Ivl:13> BB02 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #34 @67 RefTypeUse <Ivl:16> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 17: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #35 @68 RefTypeDef <Ivl:17> HWINTRINSIC BB02 regmask=[allFloat] minReg=1 wt=400.00>
Assigning related <I17> to <I13>
DefList: { N067.t29. HWINTRINSIC }
N069 ( 22, 23) [000014] -----+----- * RETURN simd16 REG NA $VN.Void
<RefPosition #36 @69 RefTypeFixedReg <Reg:d0 > BB02 regmask=[d0] minReg=1 wt=100.00>
<RefPosition #37 @69 RefTypeUse <Ivl:17> BB02 regmask=[d0] minReg=1 last fixed wt=100.00>
CHECKING LAST USES for BB02, liveout={}
==============================
use: {}
def: {V02 V03 V04 V05}
NEW BLOCK BB03
Setting BB01 as the predecessor for determining incoming variable registers of BB03
<RefPosition #38 @71 RefTypeBB BB03 regmask=[] minReg=1 wt=0.00>
firstColdLoc = 73
DefList: { }
N073 (???,???) [000055] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA
DefList: { }
N075 ( 3, 12) [000003] H----+----- * CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] REG NA $c0
Interval 18: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #39 @76 RefTypeDef <Ivl:18> CNS_INT BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00>
DefList: { N075.t3. CNS_INT }
N077 (???,???) [000058] ----------- * PUTARG_REG long REG x0
<RefPosition #40 @77 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #41 @77 RefTypeUse <Ivl:18> BB03 regmask=[x0] minReg=1 last fixed wt=0.00>
Interval 19: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #42 @78 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #43 @78 RefTypeDef <Ivl:19> PUTARG_REG BB03 regmask=[x0] minReg=1 fixed wt=0.00>
DefList: { N077.t58. PUTARG_REG }
N079 ( 17, 15) [000004] H-CXG+----- * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE REG NA $1c0
<RefPosition #44 @79 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #45 @79 RefTypeUse <Ivl:19> BB03 regmask=[x0] minReg=1 last fixed wt=0.00>
<RefPosition #46 @80 RefTypeKill BB03 regmask=[x0-xip1 lr d0-d7 d16-d31] minReg=1>
Interval 20: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #47 @80 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #48 @80 RefTypeDef <Ivl:20> CALL BB03 regmask=[x0] minReg=1 fixed wt=0.00>
CHECKING LAST USES for BB03, liveout={}
==============================
use: {}
def: {}
<RefPosition #49 @81 RefTypeBB BB03 regmask=[] minReg=1 wt=0.00>
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V02) simd16 RefPositions {#12@26 #17@41 #26@57} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 1: (V03) simd16 RefPositions {#16@36 #19@45 #28@63} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 2: (V05) long RefPositions {#8@20 #9@23 #13@33} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 3: (U02) double RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <V02/L0>
Interval 4: (U03) double RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <V03/L1>
Interval 5: long (constant) RefPositions {#1@6 #2@7} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 6: int RefPositions {#3@8 #4@11} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 7: long (constant) RefPositions {#6@18 #7@19} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval <V05/L2>
Interval 8: simd16 RefPositions {#10@24 #11@25} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <V02/L0>
Interval 9: simd16 RefPositions {#14@34 #15@35} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <V03/L1>
Interval 10: long RefPositions {#18@42 #21@47} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 11: long RefPositions {#20@46 #22@47} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 12: long RefPositions {#23@48 #24@49} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 13: simd16 RefPositions {#25@50 #33@67} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <I17>
Interval 14: long RefPositions {#27@58 #30@65} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 15: long RefPositions {#29@64 #31@65} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 16: long RefPositions {#32@66 #34@67} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 17: simd16 (interfering uses) RefPositions {#35@68 #37@69} physReg:NA Preferences=[d0] Aversions=[]
Interval 18: long (constant) RefPositions {#39@76 #41@77} physReg:NA Preferences=[x0] Aversions=[]
Interval 19: long RefPositions {#43@78 #45@79} physReg:NA Preferences=[x0] Aversions=[]
Interval 20: byref RefPositions {#48@80} physReg:NA Preferences=[x0] Aversions=[]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #1 @6 RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #2 @7 RefTypeUse <Ivl:5> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #3 @8 RefTypeDef <Ivl:6> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #4 @11 RefTypeUse <Ivl:6> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #5 @13 RefTypeBB BB02 regmask=[] minReg=1 wt=100.00>
<RefPosition #6 @18 RefTypeDef <Ivl:7> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #7 @19 RefTypeUse <Ivl:7> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #8 @20 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00>
<RefPosition #9 @23 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00>
<RefPosition #10 @24 RefTypeDef <Ivl:8> IND BB02 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #11 @25 RefTypeUse <Ivl:8> BB02 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #12 @26 RefTypeDef <Ivl:0 V02> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #13 @33 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00>
<RefPosition #14 @34 RefTypeDef <Ivl:9> IND BB02 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #15 @35 RefTypeUse <Ivl:9> BB02 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #16 @36 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #17 @41 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #18 @42 RefTypeDef <Ivl:10> HWINTRINSIC BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #19 @45 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #20 @46 RefTypeDef <Ivl:11> HWINTRINSIC BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #21 @47 RefTypeUse <Ivl:10> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #22 @47 RefTypeUse <Ivl:11> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #23 @48 RefTypeDef <Ivl:12> MUL BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #24 @49 RefTypeUse <Ivl:12> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #25 @50 RefTypeDef <Ivl:13> HWINTRINSIC BB02 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #26 @57 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
<RefPosition #27 @58 RefTypeDef <Ivl:14> HWINTRINSIC BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #28 @63 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
<RefPosition #29 @64 RefTypeDef <Ivl:15> HWINTRINSIC BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #30 @65 RefTypeUse <Ivl:14> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #31 @65 RefTypeUse <Ivl:15> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #32 @66 RefTypeDef <Ivl:16> MUL BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #33 @67 RefTypeUse <Ivl:13> BB02 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #34 @67 RefTypeUse <Ivl:16> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=100.00>
<RefPosition #35 @68 RefTypeDef <Ivl:17> HWINTRINSIC BB02 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #36 @69 RefTypeFixedReg <Reg:d0 > BB02 regmask=[d0] minReg=1 wt=100.00>
<RefPosition #37 @69 RefTypeUse <Ivl:17> BB02 regmask=[d0] minReg=1 last fixed wt=100.00>
<RefPosition #38 @71 RefTypeBB BB03 regmask=[] minReg=1 wt=0.00>
<RefPosition #39 @76 RefTypeDef <Ivl:18> CNS_INT BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #40 @77 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #41 @77 RefTypeUse <Ivl:18> BB03 regmask=[x0] minReg=1 last fixed wt=0.00>
<RefPosition #42 @78 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #43 @78 RefTypeDef <Ivl:19> PUTARG_REG BB03 regmask=[x0] minReg=1 fixed wt=0.00>
<RefPosition #44 @79 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #45 @79 RefTypeUse <Ivl:19> BB03 regmask=[x0] minReg=1 last fixed wt=0.00>
<RefPosition #46 @80 RefTypeKill BB03 regmask=[x0-xip1 lr d0-d7 d16-d31 p0-p15] minReg=1>
<RefPosition #47 @80 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #48 @80 RefTypeDef <Ivl:20> CALL BB03 regmask=[x0] minReg=1 last fixed local wt=0.00>
<RefPosition #49 @81 RefTypeBB BB03 regmask=[] minReg=1 wt=0.00>
------------
REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval)
------------
-----------------
<RefPosition #8 @20 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00>
<RefPosition #9 @23 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00>
<RefPosition #13 @33 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00>
-----------------
<RefPosition #12 @26 RefTypeDef <Ivl:0 V02> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #17 @41 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #26 @57 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
-----------------
<RefPosition #16 @36 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #19 @45 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #28 @63 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [0000] [???..???) -> BB02(1),BB03(0) (cond), preds={} succs={BB03,BB02}
=====
N003. IL_OFFSET INLRT @ 0x000[E-]
N005. CNS_INT(h) 0xffff41308f10 global ptr
Def:<I5>(#1)
N007. IND
Use:<I5>(#2) *
Def:<I6>(#3)
N009. CNS_INT 1
N011. JTEST
Use:<I6>(#4) *
BB02 [0002] [000..???) (return), preds={BB01,BB03} succs={}
=====
N015. IL_OFFSET INLRT @ 0x000[E-]
N017. CNS_INT(h) 0xffbe99a53888 static Fseq[<unknown field>]
Def:<I7>(#6) Pref:<V05/L2>
N019. V05(L2)
Use:<I7>(#7) *
Def:<V05/L2>(#8)
N021. V05(L2)
N023. IND
Use:<V05/L2>(#9)
Def:<I8>(#10) Pref:<V02/L0>
N025. V02(L0)
Use:<I8>(#11) *
Def:<V02/L0>(#12)
N027. IL_OFFSET INLRT @ 0x000[E-]
N029. V05(L2)
N031. LEA(b+32)
N033. IND
Use:<V05/L2>(#13) *
Def:<I9>(#14) Pref:<V03/L1>
N035. V03(L1)
Use:<I9>(#15) *
Def:<V03/L1>(#16)
N037. IL_OFFSET INLRT @ 0x000[E-]
N039. V02(L0)
N041. HWINTRINSIC
Use:<V02/L0>(#17)
Def:<I10>(#18)
N043. V03(L1)
N045. HWINTRINSIC
Use:<V03/L1>(#19)
Def:<I11>(#20)
N047. MUL
Use:<I10>(#21) *
Use:<I11>(#22) *
Def:<I12>(#23)
N049. HWINTRINSIC
Use:<I12>(#24) *
Def:<I13>(#25) Pref:<I17>
N051. CNS_INT 1
N053. V02(L0)
N055. CNS_INT 1
N057. HWINTRINSIC
Use:<V02/L0>(#26) *
Def:<I14>(#27)
N059. V03(L1)
N061. CNS_INT 1
N063. HWINTRINSIC
Use:<V03/L1>(#28) *
Def:<I15>(#29)
N065. MUL
Use:<I14>(#30) *
Use:<I15>(#31) *
Def:<I16>(#32)
N067. HWINTRINSIC
Use:<I13>(#33) *
Use:<I16>(#34) *
Def:<I17>(#35)
N069. RETURN
Use:<I17>(#37) Fixed:d0(#36) *
BB03 [0004] [???..???) -> BB02(1) (always), preds={BB01} succs={BB02}
=====
N073. IL_OFFSET INLRT @ 0x000[E-]
N075. CNS_INT(h) 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
Def:<I18>(#39)
N077. PUTARG_REG
Use:<I18>(#41) Fixed:x0(#40) *
Def:<I19>(#43) x0
N079. CALL help
Use:<I19>(#45) Fixed:x0(#44) *
Kill: [x0-xip1 lr d0-d7 d16-d31 p0-p15]
Def:<I20>(#48) x0 LocalDefUse *
Linear scan intervals after buildIntervals:
Interval 0: (V02) simd16 RefPositions {#12@26 #17@41 #26@57} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 1: (V03) simd16 RefPositions {#16@36 #19@45 #28@63} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 2: (V05) long RefPositions {#8@20 #9@23 #13@33} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 3: (U02) double RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <V02/L0>
Interval 4: (U03) double RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <V03/L1>
Interval 5: long (constant) RefPositions {#1@6 #2@7} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 6: int RefPositions {#3@8 #4@11} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 7: long (constant) RefPositions {#6@18 #7@19} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval <V05/L2>
Interval 8: simd16 RefPositions {#10@24 #11@25} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <V02/L0>
Interval 9: simd16 RefPositions {#14@34 #15@35} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <V03/L1>
Interval 10: long RefPositions {#18@42 #21@47} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 11: long RefPositions {#20@46 #22@47} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 12: long RefPositions {#23@48 #24@49} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 13: simd16 RefPositions {#25@50 #33@67} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <I17>
Interval 14: long RefPositions {#27@58 #30@65} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 15: long RefPositions {#29@64 #31@65} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 16: long RefPositions {#32@66 #34@67} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 17: simd16 (interfering uses) RefPositions {#35@68 #37@69} physReg:NA Preferences=[d0] Aversions=[]
Interval 18: long (constant) RefPositions {#39@76 #41@77} physReg:NA Preferences=[x0] Aversions=[]
Interval 19: long RefPositions {#43@78 #45@79} physReg:NA Preferences=[x0] Aversions=[]
Interval 20: byref RefPositions {#48@80} physReg:NA Preferences=[x0] Aversions=[]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V02) simd16 RefPositions {#12@26 #17@41 #26@57} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 1: (V03) simd16 RefPositions {#16@36 #19@45 #28@63} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 2: (V05) long RefPositions {#8@20 #9@23 #13@33} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 3: (U02) double RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <V02/L0>
Interval 4: (U03) double RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <V03/L1>
Interval 5: long (constant) RefPositions {#1@6 #2@7} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 6: int RefPositions {#3@8 #4@11} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 7: long (constant) RefPositions {#6@18 #7@19} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[] RelatedInterval <V05/L2>
Interval 8: simd16 RefPositions {#10@24 #11@25} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <V02/L0>
Interval 9: simd16 RefPositions {#14@34 #15@35} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <V03/L1>
Interval 10: long RefPositions {#18@42 #21@47} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 11: long RefPositions {#20@46 #22@47} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 12: long RefPositions {#23@48 #24@49} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 13: simd16 RefPositions {#25@50 #33@67} physReg:NA Preferences=[allFloat] Aversions=[] RelatedInterval <I17>
Interval 14: long RefPositions {#27@58 #30@65} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 15: long RefPositions {#29@64 #31@65} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 16: long RefPositions {#32@66 #34@67} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 17: simd16 (interfering uses) RefPositions {#35@68 #37@69} physReg:NA Preferences=[d0] Aversions=[]
Interval 18: long (constant) RefPositions {#39@76 #41@77} physReg:NA Preferences=[x0] Aversions=[]
Interval 19: long RefPositions {#43@78 #45@79} physReg:NA Preferences=[x0] Aversions=[]
Interval 20: byref RefPositions {#48@80} physReg:NA Preferences=[x0] Aversions=[]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #1 @6 RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #2 @7 RefTypeUse <Ivl:5> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #3 @8 RefTypeDef <Ivl:6> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #4 @11 RefTypeUse <Ivl:6> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #5 @13 RefTypeBB BB02 regmask=[] minReg=1 wt=100.00>
<RefPosition #6 @18 RefTypeDef <Ivl:7> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #7 @19 RefTypeUse <Ivl:7> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #8 @20 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00>
<RefPosition #9 @23 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00>
<RefPosition #10 @24 RefTypeDef <Ivl:8> IND BB02 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #11 @25 RefTypeUse <Ivl:8> BB02 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #12 @26 RefTypeDef <Ivl:0 V02> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #13 @33 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00>
<RefPosition #14 @34 RefTypeDef <Ivl:9> IND BB02 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #15 @35 RefTypeUse <Ivl:9> BB02 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #16 @36 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #17 @41 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #18 @42 RefTypeDef <Ivl:10> HWINTRINSIC BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #19 @45 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #20 @46 RefTypeDef <Ivl:11> HWINTRINSIC BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #21 @47 RefTypeUse <Ivl:10> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #22 @47 RefTypeUse <Ivl:11> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #23 @48 RefTypeDef <Ivl:12> MUL BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #24 @49 RefTypeUse <Ivl:12> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #25 @50 RefTypeDef <Ivl:13> HWINTRINSIC BB02 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #26 @57 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
<RefPosition #27 @58 RefTypeDef <Ivl:14> HWINTRINSIC BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #28 @63 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
<RefPosition #29 @64 RefTypeDef <Ivl:15> HWINTRINSIC BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #30 @65 RefTypeUse <Ivl:14> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #31 @65 RefTypeUse <Ivl:15> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #32 @66 RefTypeDef <Ivl:16> MUL BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #33 @67 RefTypeUse <Ivl:13> BB02 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #34 @67 RefTypeUse <Ivl:16> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last delay wt=100.00>
<RefPosition #35 @68 RefTypeDef <Ivl:17> HWINTRINSIC BB02 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #36 @69 RefTypeFixedReg <Reg:d0 > BB02 regmask=[d0] minReg=1 wt=100.00>
<RefPosition #37 @69 RefTypeUse <Ivl:17> BB02 regmask=[d0] minReg=1 last fixed wt=100.00>
<RefPosition #38 @71 RefTypeBB BB03 regmask=[] minReg=1 wt=0.00>
<RefPosition #39 @76 RefTypeDef <Ivl:18> CNS_INT BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #40 @77 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #41 @77 RefTypeUse <Ivl:18> BB03 regmask=[x0] minReg=1 last fixed wt=0.00>
<RefPosition #42 @78 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #43 @78 RefTypeDef <Ivl:19> PUTARG_REG BB03 regmask=[x0] minReg=1 fixed wt=0.00>
<RefPosition #44 @79 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #45 @79 RefTypeUse <Ivl:19> BB03 regmask=[x0] minReg=1 last fixed wt=0.00>
<RefPosition #46 @80 RefTypeKill BB03 regmask=[x0-xip1 lr d0-d7 d16-d31 p0-p15] minReg=1>
<RefPosition #47 @80 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #48 @80 RefTypeDef <Ivl:20> CALL BB03 regmask=[x0] minReg=1 last fixed local wt=0.00>
<RefPosition #49 @81 RefTypeBB BB03 regmask=[] minReg=1 wt=0.00>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00
--- V01
--- V02 (Interval 0)
<RefPosition #12 @26 RefTypeDef <Ivl:0 V02> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #17 @41 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #26 @57 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
--- V03 (Interval 1)
<RefPosition #16 @36 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #19 @45 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[allFloat] minReg=1 wt=600.00>
<RefPosition #28 @63 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[allFloat] minReg=1 last wt=600.00>
--- V04
--- V05 (Interval 2)
<RefPosition #8 @20 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00>
<RefPosition #9 @23 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00>
<RefPosition #13 @33 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
| | | | | | | | | | | | | | | |
1.#0 BB1 PredBB0 | | | | | | | | | | | | | | | |
[000043] 6.#1 C5 Def BSFIT(A) x0 |C5 a| | | | | | | | | | | | | | |
[000044] 7.#2 C5 Use * Keep x0 |C5 a| | | | | | | | | | | | | | |
8.#3 I6 Def BSFIT(A) x0 |I6 a| | | | | | | | | | | | | | |
[000049] 11.#4 I6 Use * Keep x0 |I6 a| | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
13.#5 BB2 PredBB1 | | | | | | | | | | | | | | | |
[000000] 18.#6 C7 Def BSFIT(A) x0 |C7 a| | | | | | | | | | | | | | |
[000037] 19.#7 C7 Use * Keep x0 |C7 a| | | | | | | | | | | | | | |
20.#8 V05 Def COVRS(A) x0 |V05a| | | | | | | | | | | | | | |
[000001] 23.#9 V05 Use Keep x0 |V05a| | | | | | | | | | | | | | |
24.#10 I8 Def BSFIT(A) d0 |V05a| | | | | | | | | |I8 a| | | | |
[000030] 25.#11 I8 Use * Keep d0 |V05a| | | | | | | | | |I8 a| | | | |
26.#12 V02 Def COVRS(A) d0 |V05a| | | | | | | | | |V02a| | | | |
[000007] 33.#13 V05 Use * Keep x0 |V05a| | | | | | | | | |V02a| | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |d16 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
34.#14 I9 Def ORDER(A) d16 | | | | | | | | | | |V02a| | | | |I9 a|
[000031] 35.#15 I9 Use * Keep d16 | | | | | | | | | | |V02a| | | | |I9 a|
36.#16 V03 Def COVRS(A) d16 | | | | | | | | | | |V02a| | | | |V03a|
[000017] 41.#17 V02 Use Keep d0 | | | | | | | | | | |V02a| | | | |V03a|
42.#18 I10 Def BSFIT(A) x0 |I10a| | | | | | | | | |V02a| | | | |V03a|
[000018] 45.#19 V03 Use Keep d16 |I10a| | | | | | | | | |V02a| | | | |V03a|
46.#20 I11 Def ORDER(A) x1 |I10a|I11a| | | | | | | | |V02a| | | | |V03a|
[000019] 47.#21 I10 Use * Keep x0 |I10a|I11a| | | | | | | | |V02a| | | | |V03a|
47.#22 I11 Use * Keep x1 |I10a|I11a| | | | | | | | |V02a| | | | |V03a|
48.#23 I12 Def BSFIT(A) x0 |I12a| | | | | | | | | |V02a| | | | |V03a|
[000020] 49.#24 I12 Use * Keep x0 |I12a| | | | | | | | | |V02a| | | | |V03a|
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |d16 |d17 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
50.#25 I13 Def ORDER(A) d17 | | | | | | | | | | |V02a| | | | |V03a|I13a|
[000024] 57.#26 V02 Use * Keep d0 | | | | | | | | | | |V02a| | | | |V03a|I13a|
58.#27 I14 Def BSFIT(A) x0 |I14a| | | | | | | | | | | | | | |V03a|I13a|
[000026] 63.#28 V03 Use * Keep d16 |I14a| | | | | | | | | | | | | | |V03a|I13a|
64.#29 I15 Def ORDER(A) x1 |I14a|I15a| | | | | | | | | | | | | | |I13a|
[000027] 65.#30 I14 Use * Keep x0 |I14a|I15a| | | | | | | | | | | | | | |I13a|
65.#31 I15 Use * Keep x1 |I14a|I15a| | | | | | | | | | | | | | |I13a|
66.#32 I16 Def BSFIT(A) x0 |I16a| | | | | | | | | | | | | | | |I13a|
[000029] 67.#33 I13 Use * Keep d17 |I16a| | | | | | | | | | | | | | | |I13a|
67.#34 I16 Use *D Keep x0 |I16a| | | | | | | | | | | | | | | |I13a|
68.#35 I17 Def COFUL(A) d17 |I16a| | | | | | | | | | | | | | | |I17a|
[000014] 69.#36 d0 Fixd Keep d0 | | | | | | | | | | | | | | | | |I17a|
69.#37 I17 Use * Copy d0 | | | | | | | | | | |I17a| | | | | |I17a|
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |d16 |d17 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
71.#38 BB3 PredBB1 | | | | | | | | | | | | | | | | | |
[000003] 76.#39 C18 Def Alloc x0 |C18a| | | | | | | | | | | | | | | | |
[000058] 77.#40 x0 Fixd Keep x0 |C18a| | | | | | | | | | | | | | | | |
77.#41 C18 Use * Keep x0 |C18a| | | | | | | | | | | | | | | | |
78.#42 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |
78.#43 I19 Def Alloc x0 |I19a| | | | | | | | | | | | | | | | |
[000004] 79.#44 x0 Fixd Keep x0 |I19a| | | | | | | | | | | | | | | | |
79.#45 I19 Use * Keep x0 |I19a| | | | | | | | | | | | | | | | |
80.#46 Kill None [x0-xip1 lr d0-d7 d16-d31 p0-p15]
| | | | | | | | | | | | | | | | | |
80.#47 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |
80.#48 I20 Def * Alloc x0 |I20a| | | | | | | | | | | | | | | | |
81.#49 END | | | | | | | | | | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @1 RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #1 @6 RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #2 @7 RefTypeUse <Ivl:5> BB01 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #3 @8 RefTypeDef <Ivl:6> IND BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #4 @11 RefTypeUse <Ivl:6> BB01 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #5 @13 RefTypeBB BB02 regmask=[] minReg=1 wt=100.00>
<RefPosition #6 @18 RefTypeDef <Ivl:7> CNS_INT BB02 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #7 @19 RefTypeUse <Ivl:7> BB02 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #8 @20 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB02 regmask=[x0] minReg=1 wt=300.00>
<RefPosition #9 @23 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0] minReg=1 wt=300.00>
<RefPosition #10 @24 RefTypeDef <Ivl:8> IND BB02 regmask=[d0] minReg=1 wt=400.00>
<RefPosition #11 @25 RefTypeUse <Ivl:8> BB02 regmask=[d0] minReg=1 last wt=100.00>
<RefPosition #12 @26 RefTypeDef <Ivl:0 V02> STORE_LCL_VAR BB02 regmask=[d0] minReg=1 wt=600.00>
<RefPosition #13 @33 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0] minReg=1 last wt=300.00>
<RefPosition #14 @34 RefTypeDef <Ivl:9> IND BB02 regmask=[d16] minReg=1 wt=400.00>
<RefPosition #15 @35 RefTypeUse <Ivl:9> BB02 regmask=[d16] minReg=1 last wt=100.00>
<RefPosition #16 @36 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[d16] minReg=1 wt=600.00>
<RefPosition #17 @41 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[d0] minReg=1 wt=600.00>
<RefPosition #18 @42 RefTypeDef <Ivl:10> HWINTRINSIC BB02 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #19 @45 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[d16] minReg=1 wt=600.00>
<RefPosition #20 @46 RefTypeDef <Ivl:11> HWINTRINSIC BB02 regmask=[x1] minReg=1 wt=400.00>
<RefPosition #21 @47 RefTypeUse <Ivl:10> BB02 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #22 @47 RefTypeUse <Ivl:11> BB02 regmask=[x1] minReg=1 last wt=100.00>
<RefPosition #23 @48 RefTypeDef <Ivl:12> MUL BB02 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #24 @49 RefTypeUse <Ivl:12> BB02 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #25 @50 RefTypeDef <Ivl:13> HWINTRINSIC BB02 regmask=[d17] minReg=1 wt=400.00>
<RefPosition #26 @57 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[d0] minReg=1 last wt=600.00>
<RefPosition #27 @58 RefTypeDef <Ivl:14> HWINTRINSIC BB02 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #28 @63 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[d16] minReg=1 last wt=600.00>
<RefPosition #29 @64 RefTypeDef <Ivl:15> HWINTRINSIC BB02 regmask=[x1] minReg=1 wt=400.00>
<RefPosition #30 @65 RefTypeUse <Ivl:14> BB02 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #31 @65 RefTypeUse <Ivl:15> BB02 regmask=[x1] minReg=1 last wt=100.00>
<RefPosition #32 @66 RefTypeDef <Ivl:16> MUL BB02 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #33 @67 RefTypeUse <Ivl:13> BB02 regmask=[d17] minReg=1 last wt=100.00>
<RefPosition #34 @67 RefTypeUse <Ivl:16> BB02 regmask=[x0] minReg=1 last delay wt=100.00>
<RefPosition #35 @68 RefTypeDef <Ivl:17> HWINTRINSIC BB02 regmask=[d17] minReg=1 wt=400.00>
<RefPosition #36 @69 RefTypeFixedReg <Reg:d0 > BB02 regmask=[d0] minReg=1 wt=100.00>
<RefPosition #37 @69 RefTypeUse <Ivl:17> BB02 regmask=[d0] minReg=1 last move fixed wt=100.00>
<RefPosition #38 @71 RefTypeBB BB03 regmask=[] minReg=1 wt=0.00>
<RefPosition #39 @76 RefTypeDef <Ivl:18> CNS_INT BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #40 @77 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #41 @77 RefTypeUse <Ivl:18> BB03 regmask=[x0] minReg=1 last fixed wt=0.00>
<RefPosition #42 @78 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #43 @78 RefTypeDef <Ivl:19> PUTARG_REG BB03 regmask=[x0] minReg=1 fixed wt=0.00>
<RefPosition #44 @79 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #45 @79 RefTypeUse <Ivl:19> BB03 regmask=[x0] minReg=1 last fixed wt=0.00>
<RefPosition #46 @80 RefTypeKill BB03 regmask=[x0-xip1 lr d0-d7 d16-d31 p0-p15] minReg=1>
<RefPosition #47 @80 RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=0.00>
<RefPosition #48 @80 RefTypeDef <Ivl:20> CALL BB03 regmask=[x0] minReg=1 last fixed local wt=0.00>
<RefPosition #49 @81 RefTypeBB BB03 regmask=[] minReg=1 wt=0.00>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00
--- V01
--- V02 (Interval 0)
<RefPosition #12 @26 RefTypeDef <Ivl:0 V02> STORE_LCL_VAR BB02 regmask=[d0] minReg=1 wt=600.00>
<RefPosition #17 @41 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[d0] minReg=1 wt=600.00>
<RefPosition #26 @57 RefTypeUse <Ivl:0 V02> LCL_VAR BB02 regmask=[d0] minReg=1 last wt=600.00>
--- V03 (Interval 1)
<RefPosition #16 @36 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB02 regmask=[d16] minReg=1 wt=600.00>
<RefPosition #19 @45 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[d16] minReg=1 wt=600.00>
<RefPosition #28 @63 RefTypeUse <Ivl:1 V03> LCL_VAR BB02 regmask=[d16] minReg=1 last wt=600.00>
--- V04
--- V05 (Interval 2)
<RefPosition #8 @20 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB02 regmask=[x0] minReg=1 wt=300.00>
<RefPosition #9 @23 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0] minReg=1 wt=300.00>
<RefPosition #13 @33 RefTypeUse <Ivl:2 V05> LCL_VAR BB02 regmask=[x0] minReg=1 last wt=300.00>
Active intervals at end of allocation:
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {}
Has Critical Edges
Prior to Resolution
BB01
use: {}
def: {}
in: {}
out: {}
Var=Reg beg of BB01: none
Var=Reg end of BB01: none
BB02
use: {}
def: {V02 V03 V04 V05}
in: {}
out: {}
Var=Reg beg of BB02: none
Var=Reg end of BB02: none
BB03
use: {}
def: {}
in: {}
out: {}
Var=Reg beg of BB03: none
Var=Reg end of BB03: none
RESOLVING EDGES
Trees after linear scan register allocator (LSRA)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB02(1),BB03(0) ( cond ) i LIR hascall
BB02 [0002] 2 BB01,BB03 1 [000..???) (return) i LIR hascall
BB03 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) LIR rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [???..???) -> BB02(1),BB03(0) (cond), preds={} succs={BB03,BB02}
N003 (???,???) [000051] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 3, 12) [000043] H---------- t43 = CNS_INT(h) long 0xffff41308f10 global ptr REG x0
/--* t43 long
N007 ( 6, 14) [000044] V---GO----- t44 = * IND int REG x0
N009 ( 1, 2) [000045] -c--------- t45 = CNS_INT int 1 REG NA
/--* t44 int
+--* t45 int
N011 ( 12, 22) [000049] ----GO----- * JTEST void REG NA
------------ BB02 [0002] [000..???) (return), preds={BB01,BB03} succs={}
N015 (???,???) [000052] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N017 ( 3, 12) [000000] H----+----- t0 = CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] REG x0 $c1
/--* t0 long
N019 ( 3, 12) [000037] DA--------- * STORE_LCL_VAR long V05 cse1 d:1 x0 REG x0 $VN.Void
N021 ( 1, 1) [000038] ----------- t38 = LCL_VAR long V05 cse1 u:1 x0 REG x0 $c1
/--* t38 long
N023 ( 7, 15) [000001] IA--G+----- t1 = * IND simd16 REG d0 <l:$200, c:$240>
/--* t1 simd16
N025 ( 7, 15) [000030] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 d0 REG d0 $VN.Void
N027 (???,???) [000053] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N029 ( 1, 1) [000040] ----------- t40 = LCL_VAR long V05 cse1 u:1 x0 (last use) REG x0 $c1
/--* t40 long
N031 ( 3, 4) [000042] -c-----N--- t42 = * LEA(b+32) long REG NA
/--* t42 long
N033 ( 4, 3) [000007] I---G+----- t7 = * IND simd16 REG d16 <l:$201, c:$241>
/--* t7 simd16
N035 ( 4, 3) [000031] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 d16 REG d16 $VN.Void
N037 (???,???) [000054] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N039 ( 1, 1) [000015] -----+----- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 d0 REG d0 <l:$200, c:$240>
/--* t15 simd16
N041 ( 2, 2) [000017] -----+----- t17 = * HWINTRINSIC long ulong ToScalar REG x0 <l:$280, c:$281>
N043 ( 1, 1) [000016] -----+----- t16 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 d16 REG d16 <l:$201, c:$241>
/--* t16 simd16
N045 ( 2, 2) [000018] -----+----- t18 = * HWINTRINSIC long ulong ToScalar REG x1 <l:$282, c:$283>
/--* t17 long
+--* t18 long
N047 ( 8, 7) [000019] -----+----- t19 = * MUL long REG x0 <l:$284, c:$285>
/--* t19 long
N049 ( 9, 8) [000020] -----+----- t20 = * HWINTRINSIC simd16 ulong CreateScalarUnsafe REG d17 <l:$202, c:$203>
N051 ( 1, 2) [000028] -c---+-N--- t28 = CNS_INT int 1 REG NA $43
N053 ( 1, 1) [000021] -----+----- t21 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 d0 (last use) REG d0 <l:$200, c:$240>
N055 ( 1, 2) [000023] -c---+----- t23 = CNS_INT int 1 REG NA $43
/--* t21 simd16
+--* t23 int
N057 ( 3, 4) [000024] -----+----- t24 = * HWINTRINSIC long ulong GetElement REG x0 <l:$300, c:$301>
N059 ( 1, 1) [000022] -----+----- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 d16 (last use) REG d16 <l:$201, c:$241>
N061 ( 1, 2) [000025] -c---+----- t25 = CNS_INT int 1 REG NA $43
/--* t22 simd16
+--* t25 int
N063 ( 3, 4) [000026] -----+----- t26 = * HWINTRINSIC long ulong GetElement REG x1 <l:$302, c:$303>
/--* t24 long
+--* t26 long
N065 ( 10, 11) [000027] -----+----- t27 = * MUL long REG x0 <l:$286, c:$287>
/--* t20 simd16
+--* t28 int
+--* t27 long
N067 ( 21, 22) [000029] -----+----- t29 = * HWINTRINSIC simd16 ulong Insert REG d17 <l:$340, c:$341>
/--* t29 simd16
[000059] ----------- t59 = * COPY simd16 REG d0
/--* t59 simd16
N069 ( 22, 23) [000014] -----+----- * RETURN simd16 REG NA $VN.Void
------------ BB03 [0004] [???..???) -> BB02(1) (always), preds={BB01} succs={BB02}
N073 (???,???) [000055] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N075 ( 3, 12) [000003] H----+----- t3 = CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] REG x0 $c0
/--* t3 long
N077 (???,???) [000058] ----------- t58 = * PUTARG_REG long REG x0
/--* t58 long arg0 in x0
N079 ( 17, 15) [000004] H-CXG+----- u4 = * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE REG x0 $1c0
-------------------------------------------------------------------------------------------------------------------
Final allocation
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |d16 |d17 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
1.#0 BB1 PredBB0 | | | | | | | | | | | | | | | | | |
[000043] 6.#1 C5 Def Alloc x0 |C5 a| | | | | | | | | | | | | | | | |
[000044] 7.#2 C5 Use * Keep x0 |C5 i| | | | | | | | | | | | | | | | |
8.#3 I6 Def Alloc x0 |I6 a| | | | | | | | | | | | | | | | |
[000049] 11.#4 I6 Use * Keep x0 |I6 i| | | | | | | | | | | | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |d16 |d17 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
13.#5 BB2 PredBB1 | | | | | | | | | | | | | | | | | |
[000000] 18.#6 C7 Def Alloc x0 |C7 a| | | | | | | | | | | | | | | | |
[000037] 19.#7 C7 Use * Keep x0 |C7 i| | | | | | | | | | | | | | | | |
20.#8 V05 Def Alloc x0 |V05a| | | | | | | | | | | | | | | | |
[000001] 23.#9 V05 Use Keep x0 |V05a| | | | | | | | | | | | | | | | |
24.#10 I8 Def Alloc d0 |V05a| | | | | | | | | |I8 a| | | | | | |
[000030] 25.#11 I8 Use * Keep d0 |V05a| | | | | | | | | |I8 i| | | | | | |
26.#12 V02 Def Alloc d0 |V05a| | | | | | | | | |V02a| | | | | | |
[000007] 33.#13 V05 Use * Keep x0 |V05i| | | | | | | | | |V02a| | | | | | |
34.#14 I9 Def Alloc d16 | | | | | | | | | | |V02a| | | | |I9 a| |
[000031] 35.#15 I9 Use * Keep d16 | | | | | | | | | | |V02a| | | | |I9 i| |
36.#16 V03 Def Alloc d16 | | | | | | | | | | |V02a| | | | |V03a| |
[000017] 41.#17 V02 Use Keep d0 | | | | | | | | | | |V02a| | | | |V03a| |
42.#18 I10 Def Alloc x0 |I10a| | | | | | | | | |V02a| | | | |V03a| |
[000018] 45.#19 V03 Use Keep d16 |I10a| | | | | | | | | |V02a| | | | |V03a| |
46.#20 I11 Def Alloc x1 |I10a|I11a| | | | | | | | |V02a| | | | |V03a| |
[000019] 47.#21 I10 Use * Keep x0 |I10i|I11a| | | | | | | | |V02a| | | | |V03a| |
47.#22 I11 Use * Keep x1 | |I11i| | | | | | | | |V02a| | | | |V03a| |
48.#23 I12 Def Alloc x0 |I12a| | | | | | | | | |V02a| | | | |V03a| |
[000020] 49.#24 I12 Use * Keep x0 |I12i| | | | | | | | | |V02a| | | | |V03a| |
50.#25 I13 Def Alloc d17 | | | | | | | | | | |V02a| | | | |V03a|I13a|
[000024] 57.#26 V02 Use * Keep d0 | | | | | | | | | | |V02i| | | | |V03a|I13a|
58.#27 I14 Def Alloc x0 |I14a| | | | | | | | | | | | | | |V03a|I13a|
[000026] 63.#28 V03 Use * Keep d16 |I14a| | | | | | | | | | | | | | |V03i|I13a|
64.#29 I15 Def Alloc x1 |I14a|I15a| | | | | | | | | | | | | | |I13a|
[000027] 65.#30 I14 Use * Keep x0 |I14i|I15a| | | | | | | | | | | | | | |I13a|
65.#31 I15 Use * Keep x1 | |I15i| | | | | | | | | | | | | | |I13a|
66.#32 I16 Def Alloc x0 |I16a| | | | | | | | | | | | | | | |I13a|
[000029] 67.#33 I13 Use * Keep d17 |I16a| | | | | | | | | | | | | | | |I13i|
67.#34 I16 Use *D Keep x0 |I16i| | | | | | | | | | | | | | | | |
68.#35 I17 Def Alloc d17 | | | | | | | | | | | | | | | | |I17a|
[000014] 69.#36 d0 Fixd Keep d0 | | | | | | | | | | | | | | | | |I17a|
Move d0 | | | | | | | | | | |I17i| | | | | | |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID LocRP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |d0 |d1 |d2 |d8 |d9 |d16 |d17 |
------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
71.#38 BB3 PredBB1 | | | | | | | | | | | | | | | | | |
[000003] 76.#39 C18 Def Alloc x0 |C18a| | | | | | | | | | | | | | | | |
[000058] 77.#40 x0 Fixd Keep x0 |C18a| | | | | | | | | | | | | | | | |
77.#41 C18 Use * Keep x0 |C18i| | | | | | | | | | | | | | | | |
78.#42 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |
78.#43 I19 Def Alloc x0 |I19a| | | | | | | | | | | | | | | | |
[000004] 79.#44 x0 Fixd Keep x0 |I19a| | | | | | | | | | | | | | | | |
79.#45 I19 Use * Keep x0 |I19i| | | | | | | | | | | | | | | | |
80.#46 Kill None [x0-xip1 lr d0-d7 d16-d31 p0-p15]
| | | | | | | | | | | | | | | | | |
80.#47 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |
80.#48 I20 Def * Alloc x0 |I20i| | | | | | | | | | | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars: 4
Total Reg Cand Vars: 3
Total number of Intervals: 20
Total number of RefPositions: 49
Total Number of spill temps created: 0
..........
BB01 [ 100.00]: BEST_FIT = 2
BB02 [ 100.00]: CopyReg = 1, COVERS = 3, COVERS_FULL = 1, BEST_FIT = 6, REG_ORDER = 4
..........
Total SpillCount : 0 Weighted: 0.000000
Total CopyReg : 1 Weighted: 100.000000
Total ResolutionMovs : 0 Weighted: 0.000000
Total SplitEdges : 0 Weighted: 0.000000
..........
Total COVERS [# 4] : 3 Weighted: 300.000000
Total COVERS_FULL [#10] : 1 Weighted: 100.000000
Total BEST_FIT [#11] : 8 Weighted: 800.000000
Total REG_ORDER [#13] : 4 Weighted: 400.000000
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [0000] [???..???) -> BB02(1),BB03(0) (cond), preds={} succs={BB03,BB02}
=====
N003. IL_OFFSET INLRT @ 0x000[E-]
N005. x0 = CNS_INT(h) 0xffff41308f10 global ptr
N007. x0 = IND ; x0
N009. CNS_INT 1
N011. JTEST ; x0
Var=Reg end of BB01: none
BB02 [0002] [000..???) (return), preds={BB01,BB03} succs={}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB02: none
N015. IL_OFFSET INLRT @ 0x000[E-]
N017. x0 = CNS_INT(h) 0xffbe99a53888 static Fseq[<unknown field>]
* N019. V05(x0); x0
N021. V05(x0)
N023. d0 = IND ; x0
* N025. V02(d0); d0
N027. IL_OFFSET INLRT @ 0x000[E-]
N029. V05(x0*)
N031. STK = LEA(b+32); x0*
N033. d16 = IND ; STK
* N035. V03(d16); d16
N037. IL_OFFSET INLRT @ 0x000[E-]
N039. V02(d0)
N041. x0 = HWINTRINSIC; d0
N043. V03(d16)
N045. x1 = HWINTRINSIC; d16
N047. x0 = MUL ; x0,x1
N049. d17 = HWINTRINSIC; x0
N051. CNS_INT 1
N053. V02(d0*)
N055. CNS_INT 1
N057. x0 = HWINTRINSIC; d0*
N059. V03(d16*)
N061. CNS_INT 1
N063. x1 = HWINTRINSIC; d16*
N065. x0 = MUL ; x0,x1
N067. d17 = HWINTRINSIC; d17,x0
N000. d0 = COPY ; d17
N069. RETURN ; d0
Var=Reg end of BB02: none
BB03 [0004] [???..???) -> BB02(1) (always), preds={BB01} succs={BB02}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB03: none
N073. IL_OFFSET INLRT @ 0x000[E-]
N075. x0 = CNS_INT(h) 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]
N077. x0 = PUTARG_REG; x0
* N079. x0 = CALL help; x0
Var=Reg end of BB03: none
*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB02(1),BB03(0) ( cond ) i LIR hascall
BB02 [0002] 2 BB01,BB03 1 [000..???) (return) i LIR hascall
BB03 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) LIR rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [???..???) -> BB02(1),BB03(0) (cond), preds={} succs={BB03,BB02}
N003 (???,???) [000051] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 3, 12) [000043] H---------- t43 = CNS_INT(h) long 0xffff41308f10 global ptr REG x0
/--* t43 long
N007 ( 6, 14) [000044] V---GO----- t44 = * IND int REG x0
N009 ( 1, 2) [000045] -c--------- t45 = CNS_INT int 1 REG NA
/--* t44 int
+--* t45 int
N011 ( 12, 22) [000049] ----GO----- * JTEST void REG NA
------------ BB02 [0002] [000..???) (return), preds={BB01,BB03} succs={}
N015 (???,???) [000052] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N017 ( 3, 12) [000000] H----+----- t0 = CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] REG x0 $c1
/--* t0 long
N019 ( 3, 12) [000037] DA--------- * STORE_LCL_VAR long V05 cse1 d:1 x0 REG x0 $VN.Void
N021 ( 1, 1) [000038] ----------- t38 = LCL_VAR long V05 cse1 u:1 x0 REG x0 $c1
/--* t38 long
N023 ( 7, 15) [000001] IA--G+----- t1 = * IND simd16 REG d0 <l:$200, c:$240>
/--* t1 simd16
N025 ( 7, 15) [000030] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 d0 REG d0 $VN.Void
N027 (???,???) [000053] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N029 ( 1, 1) [000040] ----------- t40 = LCL_VAR long V05 cse1 u:1 x0 (last use) REG x0 $c1
/--* t40 long
N031 ( 3, 4) [000042] -c-----N--- t42 = * LEA(b+32) long REG NA
/--* t42 long
N033 ( 4, 3) [000007] I---G+----- t7 = * IND simd16 REG d16 <l:$201, c:$241>
/--* t7 simd16
N035 ( 4, 3) [000031] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 d16 REG d16 $VN.Void
N037 (???,???) [000054] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N039 ( 1, 1) [000015] -----+----- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 d0 REG d0 <l:$200, c:$240>
/--* t15 simd16
N041 ( 2, 2) [000017] -----+----- t17 = * HWINTRINSIC long ulong ToScalar REG x0 <l:$280, c:$281>
N043 ( 1, 1) [000016] -----+----- t16 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 d16 REG d16 <l:$201, c:$241>
/--* t16 simd16
N045 ( 2, 2) [000018] -----+----- t18 = * HWINTRINSIC long ulong ToScalar REG x1 <l:$282, c:$283>
/--* t17 long
+--* t18 long
N047 ( 8, 7) [000019] -----+----- t19 = * MUL long REG x0 <l:$284, c:$285>
/--* t19 long
N049 ( 9, 8) [000020] -----+----- t20 = * HWINTRINSIC simd16 ulong CreateScalarUnsafe REG d17 <l:$202, c:$203>
N051 ( 1, 2) [000028] -c---+-N--- t28 = CNS_INT int 1 REG NA $43
N053 ( 1, 1) [000021] -----+----- t21 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 d0 (last use) REG d0 <l:$200, c:$240>
N055 ( 1, 2) [000023] -c---+----- t23 = CNS_INT int 1 REG NA $43
/--* t21 simd16
+--* t23 int
N057 ( 3, 4) [000024] -----+----- t24 = * HWINTRINSIC long ulong GetElement REG x0 <l:$300, c:$301>
N059 ( 1, 1) [000022] -----+----- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 d16 (last use) REG d16 <l:$201, c:$241>
N061 ( 1, 2) [000025] -c---+----- t25 = CNS_INT int 1 REG NA $43
/--* t22 simd16
+--* t25 int
N063 ( 3, 4) [000026] -----+----- t26 = * HWINTRINSIC long ulong GetElement REG x1 <l:$302, c:$303>
/--* t24 long
+--* t26 long
N065 ( 10, 11) [000027] -----+----- t27 = * MUL long REG x0 <l:$286, c:$287>
/--* t20 simd16
+--* t28 int
+--* t27 long
N067 ( 21, 22) [000029] -----+----- t29 = * HWINTRINSIC simd16 ulong Insert REG d17 <l:$340, c:$341>
/--* t29 simd16
[000059] ----------- t59 = * COPY simd16 REG d0
/--* t59 simd16
N069 ( 22, 23) [000014] -----+----- * RETURN simd16 REG NA $VN.Void
------------ BB03 [0004] [???..???) -> BB02(1) (always), preds={BB01} succs={BB02}
N073 (???,???) [000055] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N075 ( 3, 12) [000003] H----+----- t3 = CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] REG x0 $c0
/--* t3 long
N077 (???,???) [000058] ----------- t58 = * PUTARG_REG long REG x0
/--* t58 long arg0 in x0
N079 ( 17, 15) [000004] H-CXG+----- u4 = * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE REG x0 $1c0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Optimize post-layout
*************** Finishing PHASE Optimize post-layout
Trees after Optimize post-layout
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB03(0),BB02(1) ( cond ) i LIR hascall
BB02 [0002] 2 BB01,BB03 1 [000..???) (return) i LIR hascall
BB03 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) LIR rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [0000] [???..???) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03}
N003 (???,???) [000051] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N005 ( 3, 12) [000043] H---------- t43 = CNS_INT(h) long 0xffff41308f10 global ptr REG x0
/--* t43 long
N007 ( 6, 14) [000044] V---GO----- t44 = * IND int REG x0
N009 ( 1, 2) [000045] -c--------- t45 = CNS_INT int 1 REG NA
/--* t44 int
+--* t45 int
N011 ( 12, 22) [000049] ----GO----- * JTEST void REG NA
------------ BB02 [0002] [000..???) (return), preds={BB01,BB03} succs={}
N015 (???,???) [000052] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N017 ( 3, 12) [000000] H----+----- t0 = CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] REG x0 $c1
/--* t0 long
N019 ( 3, 12) [000037] DA--------- * STORE_LCL_VAR long V05 cse1 d:1 x0 REG x0 $VN.Void
N021 ( 1, 1) [000038] ----------- t38 = LCL_VAR long V05 cse1 u:1 x0 REG x0 $c1
/--* t38 long
N023 ( 7, 15) [000001] IA--G+----- t1 = * IND simd16 REG d0 <l:$200, c:$240>
/--* t1 simd16
N025 ( 7, 15) [000030] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 d0 REG d0 $VN.Void
N027 (???,???) [000053] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N029 ( 1, 1) [000040] ----------- t40 = LCL_VAR long V05 cse1 u:1 x0 (last use) REG x0 $c1
/--* t40 long
N031 ( 3, 4) [000042] -c-----N--- t42 = * LEA(b+32) long REG NA
/--* t42 long
N033 ( 4, 3) [000007] I---G+----- t7 = * IND simd16 REG d16 <l:$201, c:$241>
/--* t7 simd16
N035 ( 4, 3) [000031] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 d16 REG d16 $VN.Void
N037 (???,???) [000054] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N039 ( 1, 1) [000015] -----+----- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 d0 REG d0 <l:$200, c:$240>
/--* t15 simd16
N041 ( 2, 2) [000017] -----+----- t17 = * HWINTRINSIC long ulong ToScalar REG x0 <l:$280, c:$281>
N043 ( 1, 1) [000016] -----+----- t16 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 d16 REG d16 <l:$201, c:$241>
/--* t16 simd16
N045 ( 2, 2) [000018] -----+----- t18 = * HWINTRINSIC long ulong ToScalar REG x1 <l:$282, c:$283>
/--* t17 long
+--* t18 long
N047 ( 8, 7) [000019] -----+----- t19 = * MUL long REG x0 <l:$284, c:$285>
/--* t19 long
N049 ( 9, 8) [000020] -----+----- t20 = * HWINTRINSIC simd16 ulong CreateScalarUnsafe REG d17 <l:$202, c:$203>
N051 ( 1, 2) [000028] -c---+-N--- t28 = CNS_INT int 1 REG NA $43
N053 ( 1, 1) [000021] -----+----- t21 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 d0 (last use) REG d0 <l:$200, c:$240>
N055 ( 1, 2) [000023] -c---+----- t23 = CNS_INT int 1 REG NA $43
/--* t21 simd16
+--* t23 int
N057 ( 3, 4) [000024] -----+----- t24 = * HWINTRINSIC long ulong GetElement REG x0 <l:$300, c:$301>
N059 ( 1, 1) [000022] -----+----- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 d16 (last use) REG d16 <l:$201, c:$241>
N061 ( 1, 2) [000025] -c---+----- t25 = CNS_INT int 1 REG NA $43
/--* t22 simd16
+--* t25 int
N063 ( 3, 4) [000026] -----+----- t26 = * HWINTRINSIC long ulong GetElement REG x1 <l:$302, c:$303>
/--* t24 long
+--* t26 long
N065 ( 10, 11) [000027] -----+----- t27 = * MUL long REG x0 <l:$286, c:$287>
/--* t20 simd16
+--* t28 int
+--* t27 long
N067 ( 21, 22) [000029] -----+----- t29 = * HWINTRINSIC simd16 ulong Insert REG d17 <l:$340, c:$341>
/--* t29 simd16
[000059] ----------- t59 = * COPY simd16 REG d0
/--* t59 simd16
N069 ( 22, 23) [000014] -----+----- * RETURN simd16 REG NA $VN.Void
------------ BB03 [0004] [???..???) -> BB02(1) (always), preds={BB01} succs={BB02}
N073 (???,???) [000055] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
N075 ( 3, 12) [000003] H----+----- t3 = CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] REG x0 $c0
/--* t3 long
N077 (???,???) [000058] ----------- t58 = * PUTARG_REG long REG x0
/--* t58 long arg0 in x0
N079 ( 17, 15) [000004] H-CXG+----- u4 = * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE REG x0 $1c0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Place 'align' instructions
*************** In placeLoopAlignInstructions()
Identifying loops in DFS tree with following reverse post order:
RPO -> BB [pre, post]
00 -> BB01[0, 2]
01 -> BB03[2, 1]
02 -> BB02[1, 0]
Flow graph has no cycles; skipping identification of natural loops
Not checking for any loops as fgMightHaveNaturalLoops is false
*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB03(0),BB02(1) ( cond ) i LIR hascall
BB02 [0002] 2 BB01,BB03 1 [000..???) (return) i LIR hascall
BB03 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) LIR rare internal
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
<none>
Modified regs: [x0-xip1 lr d0-d7 d16-d31 p0-p15]
Callee-saved registers pushed: 2 [fp lr]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Setting genSaveFpLrWithAllCalleeSavedRegisters to false
--- delta bump 16 for FP frame
--- virtual stack offset to actual stack offset delta is 16
-- V01 was 0, now 16
; Final local variable assignments
;
;* V00 this [V00 ] ( 0, 0 ) ref -> zero-ref this class-hnd single-def <System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]>
;# V01 OutArgs [V01 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
; V02 tmp1 [V02,T02] ( 3, 6 ) simd16 -> d0 HFA(simd16) "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ulong]>
; V03 tmp2 [V03,T03] ( 3, 6 ) simd16 -> d16 HFA(simd16) "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ulong]>
;* V04 cse0 [V04,T01] ( 0, 0 ) byref -> zero-ref "CSE #02: aggressive"
; V05 cse1 [V05,T00] ( 3, 3 ) long -> x0 "CSE #03: aggressive"
;
; Lcl frame size = 0
Created:
G_M11552_IG02: ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Mark labels for codegen
BB01 : first block
BB03 : branch target
BB02 : branch target
*************** After genMarkLabelsForCodegen()
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???)-> BB03(0),BB02(1) ( cond ) i LIR label hascall
BB02 [0002] 2 BB01,BB03 1 [000..???) (return) i LIR label hascall
BB03 [0004] 1 BB01 0 [???..???)-> BB02(1) (always) LIR rare internal label
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Setting stack level from -572662307 to 0
=============== Generating BB01 [0000] [???..???) -> BB03(0),BB02(1) (cond), preds={} succs={BB02,BB03} flags=0x00000000.10008011: i LIR label hascall
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Recording Var Locations at start of BB01
<none>
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M11552_BB01:
Label: G_M11552_IG02, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB01, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: 0x0000 STACK_EMPTY (G_M11552_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000051] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
Generating: N005 ( 3, 12) [000043] H---------- t43 = CNS_INT(h) long 0xffff41308f10 global ptr REG x0
Mapped BB01 to G_M11552_IG02
IN0001: movz x0, #0x8F10
IN0002: movk x0, #0x4130 LSL #16
IN0003: movk x0, #0xFFFF LSL #32
/--* t43 long
Generating: N007 ( 6, 14) [000044] V---GO----- t44 = * IND int REG x0
Notify VM instruction set (Rcpc) must be supported.
IN0004: ldapr w0, [x0]
Generating: N009 ( 1, 2) [000045] -c--------- t45 = CNS_INT int 1 REG NA
/--* t44 int
+--* t45 int
Generating: N011 ( 12, 22) [000049] ----GO----- * JTEST void REG NA
IN0005: tbz (LARGEJMP)L_M11552_BB03
Scope info: ignoring block end
Variable Live Range History Dump for BB01
..None..
=============== Generating BB02 [0002] [000..???) (return), preds={BB01,BB03} succs={} flags=0x00000000.10008011: i LIR label hascall
BB02 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={}
Recording Var Locations at start of BB02
<none>
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M11552_BB02:
Saved:
G_M11552_IG02: ; offs=0x000000, size=0x0018, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
Created:
G_M11552_IG03: ; offs=0x000018, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Label: G_M11552_IG03, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB02, IL range [000..???)
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N015 (???,???) [000052] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
Generating: N017 ( 3, 12) [000000] H----+----- t0 = CNS_INT(h) long 0xffbe99a53888 static Fseq[<unknown field>] REG x0 $c1
Mapped BB02 to G_M11552_IG03
IN0006: movz x0, #0x3888 // data for <unknown class>:<unknown field>
IN0007: movk x0, #0x99A5 LSL #16
IN0008: movk x0, #0xFFBE LSL #32
/--* t0 long
Generating: N019 ( 3, 12) [000037] DA--------- * STORE_LCL_VAR long V05 cse1 d:1 x0 REG x0 $VN.Void
V05 in reg x0 is becoming live [000037]
Live regs: 0000000000000000 {} + {x0} => 0000000000000001 {x0}
Live vars after [000037]: {} +{V05} => {V05}
Generating: N021 ( 1, 1) [000038] ----------- t38 = LCL_VAR long V05 cse1 u:1 x0 REG x0 $c1
/--* t38 long
Generating: N023 ( 7, 15) [000001] IA--G+----- t1 = * IND simd16 REG d0 <l:$200, c:$240>
IN0009: ldr q0, [x0]
/--* t1 simd16
Generating: N025 ( 7, 15) [000030] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 d:1 d0 REG d0 $VN.Void
V02 in reg d0 is becoming live [000030]
Live regs: 0000000000000001 {x0} + {d0} => 0000000100000001 {x0 d0}
Live vars after [000030]: {V05} +{V02} => {V02 V05}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N027 (???,???) [000053] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
Generating: N029 ( 1, 1) [000040] ----------- t40 = LCL_VAR long V05 cse1 u:1 x0 (last use) REG x0 $c1
/--* t40 long
Generating: N031 ( 3, 4) [000042] -c-----N--- t42 = * LEA(b+32) long REG NA
/--* t42 long
Generating: N033 ( 4, 3) [000007] I---G+----- t7 = * IND simd16 REG d16 <l:$201, c:$241>
V05 in reg x0 is becoming dead [000040]
Live regs: 0000000100000001 {x0 d0} - {x0} => 0000000100000000 {d0}
Live vars after [000040]: {V02 V05} -{V05} => {V02}
IN000a: ldr q16, [x0, #0x20]
/--* t7 simd16
Generating: N035 ( 4, 3) [000031] DA--G+----- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 d:1 d16 REG d16 $VN.Void
V03 in reg d16 is becoming live [000031]
Live regs: 0000000100000000 {d0} + {d16} => 0001000100000000 {d0 d16}
Live vars after [000031]: {V02} +{V03} => {V02 V03}
genIPmappingAdd: ignoring duplicate IL offset 0x0
Generating: N037 (???,???) [000054] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
Generating: N039 ( 1, 1) [000015] -----+----- t15 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 d0 REG d0 <l:$200, c:$240>
/--* t15 simd16
Generating: N041 ( 2, 2) [000017] -----+----- t17 = * HWINTRINSIC long ulong ToScalar REG x0 <l:$280, c:$281>
IN000b: umov x0, v0.d[0]
Generating: N043 ( 1, 1) [000016] -----+----- t16 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 d16 REG d16 <l:$201, c:$241>
/--* t16 simd16
Generating: N045 ( 2, 2) [000018] -----+----- t18 = * HWINTRINSIC long ulong ToScalar REG x1 <l:$282, c:$283>
IN000c: umov x1, v16.d[0]
/--* t17 long
+--* t18 long
Generating: N047 ( 8, 7) [000019] -----+----- t19 = * MUL long REG x0 <l:$284, c:$285>
IN000d: mul x0, x0, x1
/--* t19 long
Generating: N049 ( 9, 8) [000020] -----+----- t20 = * HWINTRINSIC simd16 ulong CreateScalarUnsafe REG d17 <l:$202, c:$203>
IN000e: ins v17.d[0], x0
Generating: N051 ( 1, 2) [000028] -c---+-N--- t28 = CNS_INT int 1 REG NA $43
Generating: N053 ( 1, 1) [000021] -----+----- t21 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V02 tmp1 u:1 d0 (last use) REG d0 <l:$200, c:$240>
Generating: N055 ( 1, 2) [000023] -c---+----- t23 = CNS_INT int 1 REG NA $43
/--* t21 simd16
+--* t23 int
Generating: N057 ( 3, 4) [000024] -----+----- t24 = * HWINTRINSIC long ulong GetElement REG x0 <l:$300, c:$301>
V02 in reg d0 is becoming dead [000021]
Live regs: 0001000100000000 {d0 d16} - {d0} => 0001000000000000 {d16}
Live vars after [000021]: {V02 V03} -{V02} => {V03}
IN000f: umov x0, v0.d[1]
Generating: N059 ( 1, 1) [000022] -----+----- t22 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1> V03 tmp2 u:1 d16 (last use) REG d16 <l:$201, c:$241>
Generating: N061 ( 1, 2) [000025] -c---+----- t25 = CNS_INT int 1 REG NA $43
/--* t22 simd16
+--* t25 int
Generating: N063 ( 3, 4) [000026] -----+----- t26 = * HWINTRINSIC long ulong GetElement REG x1 <l:$302, c:$303>
V03 in reg d16 is becoming dead [000022]
Live regs: 0001000000000000 {d16} - {d16} => 0000000000000000 {}
Live vars after [000022]: {V03} -{V03} => {}
IN0010: umov x1, v16.d[1]
/--* t24 long
+--* t26 long
Generating: N065 ( 10, 11) [000027] -----+----- t27 = * MUL long REG x0 <l:$286, c:$287>
IN0011: mul x0, x0, x1
/--* t20 simd16
+--* t28 int
+--* t27 long
Generating: N067 ( 21, 22) [000029] -----+----- t29 = * HWINTRINSIC simd16 ulong Insert REG d17 <l:$340, c:$341>
IN0012: ins v17.d[1], x0
/--* t29 simd16
Generating: [000059] ----------- t59 = * COPY simd16 REG d0
/--* t59 simd16
Generating: N069 ( 22, 23) [000014] -----+----- * RETURN simd16 REG NA $VN.Void
IN0013: mov v0.16b, v17.16b
Scope info: ignoring block end
Added IP mapping: EPILOG (G_M11552_IG03,ins#14,ofs#56) label
Reserving epilog IG for block BB02
Saved:
G_M11552_IG03: ; offs=0x000018, size=0x0038, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0002], byref
Created:
G_M11552_IG04: ; offs=0x000050, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Created:
G_M11552_IG05: ; offs=0x000150, size=0x0000, bbWeight=1, gcrefRegs=0000 {}, epilog
*************** After placeholder IG creation
G_M11552_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M11552_IG02: ; offs=0x000000, size=0x0018, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M11552_IG03: ; offs=0x000018, size=0x0038, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0002], byref
G_M11552_IG04: ; epilog placeholder, next placeholder=<END>, BB02 [0002], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
G_M11552_IG05: ; offs=0x000150, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Current IG
Variable Live Range History Dump for BB02
..None..
=============== Generating BB03 [0004] [???..???) -> BB02(1) (always), preds={BB01} succs={BB02} flags=0x00000000.0000a021: LIR rare internal label
BB03 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Recording Var Locations at start of BB03
<none>
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 0000000000000000 {}
GC regs: (unchanged) 0000 {}
Byref regs: (unchanged) 0000 {}
L_M11552_BB03:
Label: G_M11552_IG05, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Scope info: begin block BB03, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: NO_MAP (G_M11552_IG05,ins#0,ofs#0) label
Added IP mapping: 0x0000 STACK_EMPTY (G_M11552_IG05,ins#0,ofs#0) label
Generating: N073 (???,???) [000055] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA
Generating: N075 ( 3, 12) [000003] H----+----- t3 = CNS_INT(h) long 0xffff41308cd8 class System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong] REG x0 $c0
Mapped BB03 to G_M11552_IG05
IN0014: movz x0, #0x8CD8
IN0015: movk x0, #0x4130 LSL #16
IN0016: movk x0, #0xFFFF LSL #32
/--* t3 long
Generating: N077 (???,???) [000058] ----------- t58 = * PUTARG_REG long REG x0
/--* t58 long arg0 in x0
Generating: N079 ( 17, 15) [000004] H-CXG+----- u4 = * CALL help byref CORINFO_HELP_GET_GCSTATIC_BASE REG x0 $1c0
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0017: bl CORINFO_HELP_GET_GCSTATIC_BASE
Byref regs: 0000 {} => 0001 {x0}
Byref regs: 0001 {x0} => 0000 {}
Scope info: ignoring block end
IN0018: b L_M11552_BB02
Variable Live Range History Dump for BB03
..None..
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 67, compSizeEstimate = 92 System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this
; Final local variable assignments
;
;* V00 this [V00 ] ( 0, 0 ) ref -> zero-ref this class-hnd single-def <System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]>
;# V01 OutArgs [V01 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
; V02 tmp1 [V02,T02] ( 3, 6 ) simd16 -> d0 HFA(simd16) "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ulong]>
; V03 tmp2 [V03,T03] ( 3, 6 ) simd16 -> d16 HFA(simd16) "Inlining Arg" <System.Runtime.Intrinsics.Vector128`1[ulong]>
;* V04 cse0 [V04,T01] ( 0, 0 ) byref -> zero-ref "CSE #02: aggressive"
; V05 cse1 [V05,T00] ( 3, 3 ) long -> x0 "CSE #03: aggressive"
;
; Lcl frame size = 0
*************** Before prolog / epilog generation
G_M11552_IG01: ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M11552_IG02: ; offs=0x000000, size=0x0018, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M11552_IG03: ; offs=0x000018, size=0x0038, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0002], byref
G_M11552_IG04: ; epilog placeholder, next placeholder=<END>, BB02 [0002], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
G_M11552_IG05: ; offs=0x000150, size=0x0000, bbWeight=0, gcrefRegs=0000 {}, BB03 [0004] <-- Current IG
Recording Var Locations at start of BB01
<none>
Saved:
G_M11552_IG05: ; offs=0x000150, size=0x0014, bbWeight=0, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0004], gcvars, byref
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M11552_IG01,ins#0,ofs#0) label
__prolog:
Debug: New V00 debug range: first
Save float regs: []
Save int regs: [fp lr]
Frame type 1. #outsz=0; #framesz=16; LclFrameSize=0
IN0019: stp fp, lr, [sp, #-0x10]!
offset=16, calleeSaveSpDelta=0
offsetSpToSavedFp=0
IN001a: mov fp, sp
*************** In genHomeRegisterParams()
0 registers in register parameter interference graph
*************** In genEnregisterIncomingStackArgs()
Debug: Closing V00 debug range.
Saved:
G_M11552_IG01: ; offs=0x000000, size=0x0008, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {}
Frame type 1. #outsz=0; #framesz=16; localloc? false
calleeSaveSpOffset=16, calleeSaveSpDelta=0
IN001b: ldp fp, lr, [sp], #0x10
IN001c: ret lr
Saved:
G_M11552_IG04: ; offs=0x000050, size=0x0008, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M11552_IG01: ; func=00, offs=0x000000, size=0x0008, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M11552_IG02: ; offs=0x000008, size=0x0018, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M11552_IG03: ; offs=0x000020, size=0x0038, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0002], byref
G_M11552_IG04: ; offs=0x000058, size=0x0008, bbWeight=1, epilog, nogc, extend
G_M11552_IG05: ; offs=0x000060, size=0x0014, bbWeight=0, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0004], gcvars, byref
*************** In emitJumpDistBind()
Emitter Jump List:
IG02 IN0005 tbz[8] -> IG05
IG05 IN0018 b[4] -> IG03
total jump count: 2
Binding: IN0005: tbz (LARGEJMP)L_M11552_BB03
Binding L_M11552_BB03 to G_M11552_IG05
Estimate of fwd jump [96F81A4C/005]: 0018 -> 0060 = 0048
Shrinking jump [96F81A4C/005]
Adjusted offset of BB03 from 0020 to 001C
Adjusted offset of BB04 from 0058 to 0054
Adjusted offset of BB05 from 0060 to 005C
Binding: IN0018: b L_M11552_BB02
Binding L_M11552_BB02 to G_M11552_IG03
Total shrinkage = 4, min extra jump size = 4294967295
*************** Finishing PHASE Generate code
*************** Starting PHASE Emit code
Hot code size = 0x70 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0xc)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M11552_IG01: ; offs=0x000000, size=0x0008, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0019: 000000 stp fp, lr, [sp, #-0x10]!
IN001a: 000004 mov fp, sp
;; size=8 bbWeight=1 PerfScore 1.50
G_M11552_IG02: ; offs=0x000008, size=0x0014, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref, isz
IN0001: 000008 movz x0, #0x8F10
IN0002: 00000C movk x0, #0x4130 LSL #16
IN0003: 000010 movk x0, #0xFFFF LSL #32
IN0004: 000014 ldapr w0, [x0]
IN0005: 000018 tbz w0, #0, G_M11552_IG05
;; size=20 bbWeight=1 PerfScore 5.50
G_M11552_IG03: ; offs=0x00001C, size=0x0038, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0002], byref
IN0006: 00001C movz x0, #0x3888 // data for <unknown class>:<unknown field>
IN0007: 000020 movk x0, #0x99A5 LSL #16
IN0008: 000024 movk x0, #0xFFBE LSL #32
IN0009: 000028 ldr q0, [x0]
IN000a: 00002C ldr q16, [x0, #0x20]
IN000b: 000030 umov x0, v0.d[0]
IN000c: 000034 umov x1, v16.d[0]
IN000d: 000038 mul x0, x0, x1
IN000e: 00003C ins v17.d[0], x0
IN000f: 000040 umov x0, v0.d[1]
IN0010: 000044 umov x1, v16.d[1]
IN0011: 000048 mul x0, x0, x1
IN0012: 00004C ins v17.d[1], x0
IN0013: 000050 mov v0.16b, v17.16b
;; size=56 bbWeight=1 PerfScore 18.00
G_M11552_IG04: ; offs=0x000054, size=0x0008, bbWeight=1, epilog, nogc, extend
IN001b: 000054 ldp fp, lr, [sp], #0x10
IN001c: 000058 ret lr
;; size=8 bbWeight=1 PerfScore 2.00
G_M11552_IG05: ; offs=0x00005C, size=0x0014, bbWeight=0, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0004], gcvars, byref
IN0014: 00005C movz x0, #0x8CD8
IN0015: 000060 movk x0, #0x4130 LSL #16
IN0016: 000064 movk x0, #0xFFFF LSL #32
; Call at 0068 [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
recordRelocation: 0xc5bb96fb0aa8 (rw: 0xc5bb96fb0aa8) => 0xffff7eeb9a10, type 3 (IMAGE_REL_ARM64_BRANCH26), delta 0
IN0017: 000068 bl CORINFO_HELP_GET_GCSTATIC_BASE
IN0018: 00006C b G_M11552_IG03
;; size=20 bbWeight=0 PerfScore 0.00
Allocated method code size = 112 , actual size = 112, unused size = 0
; Total bytes of code 112, prolog size 8, PerfScore 27.00, instruction count 28, allocated bytes for code 112 (MethodHash=aff7d2df) for method System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this (FullOpts)
; ============================================================
*************** After end code gen, before unwindEmit()
G_M11552_IG01: ; func=00, offs=0x000000, size=0x0008, bbWeight=1, PerfScore 1.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0019: 000000 stp fp, lr, [sp, #-0x10]!
IN001a: 000004 mov fp, sp
G_M11552_IG02: ; offs=0x000008, size=0x0014, bbWeight=1, PerfScore 5.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref, isz
IN0001: 000008 movz x0, #0x8F10
IN0002: 00000C movk x0, #0x4130 LSL #16
IN0003: 000010 movk x0, #0xFFFF LSL #32
IN0004: 000014 ldapr w0, [x0]
IN0005: 000018 tbz w0, #0, G_M11552_IG05
G_M11552_IG03: ; offs=0x00001C, size=0x0038, bbWeight=1, PerfScore 18.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB02 [0002], byref
IN0006: 00001C movz x0, #0x3888 // data for <unknown class>:<unknown field>
IN0007: 000020 movk x0, #0x99A5 LSL #16
IN0008: 000024 movk x0, #0xFFBE LSL #32
IN0009: 000028 ldr q0, [x0]
IN000a: 00002C ldr q16, [x0, #0x20]
IN000b: 000030 umov x0, v0.d[0]
IN000c: 000034 umov x1, v16.d[0]
IN000d: 000038 mul x0, x0, x1
IN000e: 00003C ins v17.d[0], x0
IN000f: 000040 umov x0, v0.d[1]
IN0010: 000044 umov x1, v16.d[1]
IN0011: 000048 mul x0, x0, x1
IN0012: 00004C ins v17.d[1], x0
IN0013: 000050 mov v0.16b, v17.16b
G_M11552_IG04: ; offs=0x000054, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extend
IN001b: 000054 ldp fp, lr, [sp], #0x10
IN001c: 000058 ret lr
G_M11552_IG05: ; offs=0x00005C, size=0x0014, bbWeight=0, PerfScore 0.00, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB03 [0004], gcvars, byref
IN0014: 00005C movz x0, #0x8CD8
IN0015: 000060 movk x0, #0x4130 LSL #16
IN0016: 000064 movk x0, #0xFFFF LSL #32
IN0017: 000068 bl CORINFO_HELP_GET_GCSTATIC_BASE
IN0018: 00006C b G_M11552_IG03
*************** Finishing PHASE Emit code
*************** Starting PHASE Emit GC+EH tables
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x000070 (not in unwind data)
Code Words : 1
Epilog Count : 1
E bit : 0
X bit : 0
Vers : 0
Function Length : 28 (0x0001c) Actual length = 112 (0x000070)
---- Epilog scopes ----
---- Scope 0
Epilog Start Offset : 21 (0x00015) Actual offset = 84 (0x000054) Offset from main function begin = 84 (0x000054)
Epilog Start Index : 1 (0x01)
---- Unwind codes ----
E1 set_fp; mov fp, sp
---- Epilog start at index 1 ----
81 save_fplr_x #1 (0x01); stp fp, lr, [sp, #-16]!
E4 end
E4 end
allocUnwindInfo(pHotCode=0x0xc5bb96fb0a40, pColdCode=0x(nil), startOffset=0x0, endOffset=0x70, unwindSize=0xc, pUnwindBlock=0x0xc5bb96eedb02, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 4
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000008 ( STACK_EMPTY )
IL offs EPILOG : 0x00000054 ( STACK_EMPTY )
IL offs 0x0000 : 0x0000005C ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 1
; Variable debug info: 1 live ranges, 1 vars for method System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this
(V00 this) : From 00000000h to 00000008h, in x0
*************** In gcInfoBlockHdrSave()
Set code length to 112.
Set ReturnKind to Scalar.
Set stack base register to fp.
Set Outgoing stack arg area size to 0.
Defining 1 call sites:
Offset 0x68, size 4.
*************** Finishing PHASE Emit GC+EH tables
Method code size: 112
Allocations for System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this (MethodHash=aff7d2df)
count: 794, size: 99809, max = 7888
allocateMemory: 131072, nraUsed: 106360
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
ABI | 0 | 0.00%
AssertionProp | 6500 | 6.51%
ASTNode | 8248 | 8.26%
InstDesc | 7672 | 7.69%
ImpStack | 384 | 0.38%
BasicBlock | 1776 | 1.78%
CallArgs | 352 | 0.35%
FlowEdge | 160 | 0.16%
DepthFirstSearch | 208 | 0.21%
Loops | 116 | 0.12%
TreeStatementList | 192 | 0.19%
SiScope | 0 | 0.00%
DominatorMemory | 56 | 0.06%
LSRA | 10092 | 10.11%
LSRA_Interval | 2016 | 2.02%
LSRA_RefPosition | 4000 | 4.01%
Reachability | 40 | 0.04%
SSA | 528 | 0.53%
ValueNumber | 13632 | 13.66%
LvaTable | 1600 | 1.60%
UnwindInfo | 32 | 0.03%
hashBv | 40 | 0.04%
bitset | 32 | 0.03%
FixedBitVect | 32 | 0.03%
Generic | 886 | 0.89%
LocalAddressVisitor | 424 | 0.42%
FieldSeqStore | 176 | 0.18%
MemorySsaMap | 40 | 0.04%
MemoryPhiArg | 0 | 0.00%
CSE | 2796 | 2.80%
GC | 1285 | 1.29%
CorTailCallInfo | 0 | 0.00%
Inlining | 2088 | 2.09%
ArrayStack | 0 | 0.00%
DebugInfo | 280 | 0.28%
DebugOnly | 30173 | 30.23%
Codegen | 2568 | 2.57%
LoopOpt | 0 | 0.00%
LoopClone | 0 | 0.00%
LoopUnroll | 0 | 0.00%
LoopHoist | 0 | 0.00%
LoopIVOpts | 0 | 0.00%
Unknown | 113 | 0.11%
RangeCheck | 0 | 0.00%
CopyProp | 424 | 0.42%
Promotion | 240 | 0.24%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 272 | 0.27%
ClassLayout | 128 | 0.13%
TailMergeThrows | 0 | 0.00%
EarlyProp | 0 | 0.00%
ZeroInit | 208 | 0.21%
Pgo | 0 | 0.00%
Final metrics:
PhysicallyPromotedFields : 0
LoopsFoundDuringOpts : 0
LoopsCloned : 0
LoopsUnrolled : 0
LoopAlignmentCandidates : 0
LoopsAligned : 0
LoopsIVWidened : 0
WidenedIVs : 0
UnusedIVsRemoved : 0
LoopsMadeDownwardsCounted : 0
LoopsStrengthReduced : 0
VarsInSsa : 2
HoistedExpressions : 0
RedundantBranchesEliminated : 0
JumpThreadingsPerformed : 0
CseCount : 2
BasicBlocksAtCodegen : 3
PerfScore : 27.000000
BytesAllocated : 106360
ImporterBranchFold : 0
ImporterSwitchFold : 0
DevirtualizedCall : 0
DevirtualizedCallUnboxedEntry : 0
DevirtualizedCallRemovedBox : 0
GDV : 0
ClassGDV : 0
MethodGDV : 0
MultiGuessGDV : 0
ChainedGDV : 0
InlinerBranchFold : 0
InlineAttempt : 1
InlineCount : 1
ProfileConsistentBeforeInline : 0
ProfileConsistentAfterInline : 0
ProfileSynthesizedBlendedOrRepaired : 0
ProfileInconsistentInitially : 0
ProfileInconsistentResetLeave : 0
ProfileInconsistentImporterBranchFold : 0
ProfileInconsistentImporterSwitchFold : 0
ProfileInconsistentChainedGDV : 0
ProfileInconsistentScratchBB : 0
ProfileInconsistentInlinerBranchFold : 0
ProfileInconsistentInlineeScale : 0
ProfileInconsistentInlinee : 0
ProfileInconsistentNoReturnInlinee : 0
ProfileInconsistentMayThrowInlinee : 0
NewRefClassHelperCalls : 0
StackAllocatedRefClasses : 0
NewBoxedValueClassHelperCalls : 0
StackAllocatedBoxedValueClasses : 0
****** DONE compiling System.Runtime.Intrinsics.Tests.Perf_Vector128Of`1[ulong]:MultiplyBenchmark():System.Runtime.Intrinsics.Vector128`1[ulong]:this
Clean SuperPMI replay (1 contexts processed)
Replay summary:
All replays clean
Finish time: 12:41:49
Elapsed time: 0:00:00.083397
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