Device tree entry configuration for si5344 on custom ultrascale board based on zcu102

gistfile1.txt

        clock entry for synth clock is <&si5344 1 0>, the synth clock needs to be at 2x the desired output clock
        
        
        clocks = <&si5344 0 0>, <&si5344 0 1>, <&si5344 0 2>, <&si5344 0 3>;
        clock-names = "si5344_0", "si5344_1", "si5344_2", "si5344_3";
        assigned-clocks = <&si5344 0 0>, <&si5344 0 1>,
                          <&si5344 0 2>, <&si5344 0 3>,
                          <&si5344 1 0>;
        assigned-clock-rates = <156250000>, <156250000>,
                               <156250000>, <156250000>,
                               <312500000>;