Created
February 29, 2020 08:31
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vhdl code for single digit seven segment counter from 0 to 9. Counting is auto incremental mode with the input clock divided to make 500 milliseconds.
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---------------------------------------------------------------------------------- | |
-- Company: | |
-- Engineer: | |
-- | |
-- Create Date: 12:35:24 02/29/2020 | |
-- Design Name: | |
-- Module Name: sevensegment_ex01 - Behavioral | |
-- Project Name: | |
-- Target Devices: | |
-- Tool versions: | |
-- Description: | |
-- | |
-- Dependencies: | |
-- | |
-- Revision: | |
-- Revision 0.01 - File Created | |
-- Additional Comments: | |
-- | |
---------------------------------------------------------------------------------- | |
library IEEE; | |
use IEEE.STD_LOGIC_1164.ALL; | |
-- Uncomment the following library declaration if using | |
-- arithmetic functions with Signed or Unsigned values | |
--use IEEE.NUMERIC_STD.ALL; | |
-- Uncomment the following library declaration if instantiating | |
-- any Xilinx primitives in this code. | |
--library UNISIM; | |
--use UNISIM.VComponents.all; | |
entity sevensegment_ex01 is | |
Port ( anodes : out STD_LOGIC_VECTOR (3 downto 0); | |
clk : in STD_LOGIC; | |
cathods : out STD_LOGIC_VECTOR (7 downto 0)); | |
end sevensegment_ex01; | |
architecture Behavioral of sevensegment_ex01 is | |
signal digit0 : std_logic_vector (7 downto 0); | |
signal counter : natural range 0 to 9 := 0; | |
signal clk_counter : natural range 0 to 50000000 := 0; | |
begin | |
process(clk) | |
begin | |
if rising_edge(clk) then | |
clk_counter <= clk_counter + 1; | |
if clk_counter >= 50000000 then | |
clk_counter <= 0; | |
if counter > 8 then | |
counter <= 0; | |
else | |
counter <= counter +1; | |
end if; | |
end if; | |
end if; | |
end process; | |
process(counter) | |
begin | |
case counter is | |
when 0 => cathods <= "11000000"; --0 | |
when 1 => cathods <= "11111001"; --1 | |
when 2 => cathods <= "10100100"; --2 | |
when 3 => cathods <= "10110000"; --3 | |
when 4 => cathods <= "10011001"; --4 | |
when 5 => cathods <= "10010010"; --5 | |
when 6 => cathods <= "10000010"; --6 | |
when 7 => cathods <= "11111000"; --7 | |
when 8 => cathods <= "10000000"; --8 | |
when 9 => cathods <= "10010000"; --9 | |
end case; | |
end process; | |
anodes <= "1110"; | |
--cathods <= digit0; | |
end Behavioral; | |
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NET "anodes<0>" LOC = "N16"; | |
NET "anodes<1>" LOC = "N15"; | |
NET "anodes<2>" LOC = "P18"; | |
NET "anodes<3>" LOC = "P17"; | |
NET "clk" LOC = V10; | |
NET "cathods<0>" LOC = "T17" ; | |
NET "cathods<1>" LOC = "T18" ; | |
NET "cathods<2>" LOC = "U17" ; | |
NET "cathods<3>" LOC = "U18" ; | |
NET "cathods<4>" LOC = "M14" ; | |
NET "cathods<5>" LOC = "N14" ; | |
NET "cathods<6>" LOC = "L14" ; | |
NET "cathods<7>" LOC = "M13" ; |
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