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@acdimalev
Created September 5, 2018 09:06
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[jamin@dependent 2018-06-06-bindump]$ perf stat -e task-clock,cycles,instructions,cache-references,cache-misses
./say hello > /dev/null
Performance counter stats for './say hello':
0.197061 task-clock:u (msec) # 0.363 CPUs utilized
133682 cycles:u # 0.678 GHz
115712 instructions:u # 0.87 insn per cycle
1486 cache-references:u # 7.541 M/sec
937 cache-misses:u # 63.055 % of all cache refs
0.000542947 seconds time elapsed
[jamin@dependent 2018-06-06-bindump]$ perf stat -e L1-dcache-load-misses,L1-dcache-loads,L1-dcache-stores,L1-icache-load-misses ./say hello > /dev/null
Performance counter stats for './say hello':
963 L1-dcache-load-misses:u # 4.98% of all L1-dcache hits
19332 L1-dcache-loads:u
4357 L1-dcache-stores:u
223 L1-icache-load-misses:u
0.000503910 seconds time elapsed
[jamin@dependent 2018-06-06-bindump]$ valgrind --tool=cachegrind ./say hello > /dev/null
==3467== Cachegrind, a cache and branch-prediction profiler
==3467== Copyright (C) 2002-2017, and GNU GPL'd, by Nicholas Nethercote et al.
==3467== Using Valgrind-3.13.0 and LibVEX; rerun with -h for copyright info
==3467== Command: ./say hello
==3467==
--3467-- warning: L3 cache found, using its data for the LL simulation.
==3467==
==3467== I refs: 122,952
==3467== I1 misses: 275
==3467== LLi misses: 274
==3467== I1 miss rate: 0.22%
==3467== LLi miss rate: 0.22%
==3467==
==3467== D refs: 29,041 (22,248 rd + 6,793 wr)
==3467== D1 misses: 529 ( 371 rd + 158 wr)
==3467== LLd misses: 468 ( 314 rd + 154 wr)
==3467== D1 miss rate: 1.8% ( 1.7% + 2.3% )
==3467== LLd miss rate: 1.6% ( 1.4% + 2.3% )
==3467==
==3467== LL refs: 804 ( 646 rd + 158 wr)
==3467== LL misses: 742 ( 588 rd + 154 wr)
==3467== LL miss rate: 0.5% ( 0.4% + 2.3% )
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