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Swift options for use with -Xllvm
% swiftc -Xllvm -help-hidden /tmp/foo.swift
USAGE: swift (LLVM option parsing) [options]
OPTIONS:
-a9-754319-workaround - Enable workarounds for A9 HW bugs #754319
-a9-754320-workaround - Enable workarounds for A9 HW bugs #754320
-aarch64-use-tbi - Assume that top byte of an address is ignored
-agg-antidep-debugdiv=<int> - Debug control for aggressive anti-dep breaker
-agg-antidep-debugmod=<int> - Debug control for aggressive anti-dep breaker
-aggressive-ext-opt - Aggressive extension optimization
-align-all-blocks=<uint> - Force the alignment of all blocks in the function.
-align-neon-spills - Align ARM NEON spills in prolog and epilog
-arm-adjust-jump-tables - Adjust basic block layout to better use TB[BH]
-arm-align-constant-islands - Align constant islands in code
Load/store alignment support
-arm-default-align - Generate unaligned accesses only on hardware/OS combinations that are known to support them
-arm-strict-align - Disallow all unaligned memory accesses
-arm-no-strict-align - Allow unaligned memory accesses
-arm-enable-ehabi - Generate ARM EHABI tables
-arm-enable-ehabi-descriptors - Generate ARM EHABI tables with unwinding descriptors
-arm-interworking - Enable / disable ARM interworking (for debugging only)
-arm-long-calls - Generate calls via indirect call instructions
IT block support
-arm-default-it - Generate IT block based on arch
-arm-restrict-it - Disallow deprecated IT based on ARMv8
-arm-no-restrict-it - Allow IT blocks based on ARMv7
-arm-reserve-r9 - Reserve R9, making it unavailable as GPR
-arm-tail-calls - Generate tail calls (TEMPORARY OPTION).
-arm-use-movt -
-arm-use-mulops -
-arm64-bcc-offset-bits=<uint> - Restrict range of Bcc instructions (DEBUG)
-arm64-branch-relax - Relax out of range conditional branches
-arm64-cbz-offset-bits=<uint> - Restrict range of CB[N]Z instructions (DEBUG)
-arm64-ccmp - Enable the CCMP formation pass
-arm64-ccmp-limit=<uint> - Maximum number of instructions per speculated block.
-arm64-collect-loh - Enable the pass that emits the linker optimization hints (LOH)
-arm64-collect-loh-bb-only - Restrict analysis at basic block scope
-arm64-collect-loh-pre-collect-register - Restrict analysis to registers invovled in LOHs
-arm64-extr-generation - Allow ARM64 (or (shift)(shift))->extract
-arm64-load-store-opt -
-arm64-load-store-scan-limit=<uint> -
-arm64-neon-syntax - Choose style of NEON code to emit from ARM64 backend:
=generic - Emit generic NEON assembly
=apple - Emit Apple-style NEON assembly
-arm64-promote-const - Enable the promote constant pass
-arm64-redzone - enable use of redzone on ARM64
-arm64-shift-insert-generation - Allow ARM64 SLI/SRI formation
-arm64-simd-scalar - enable use of AdvSIMD scalar integer instructions
-arm64-simd-scalar-force-all - Force use of AdvSIMD scalar instructions everywhere
-arm64-stp-suppress - Suppress STP for ARM64
-arm64-stress-ccmp - Turn all knobs to 11
-arm64-stress-promote-const - Promote all vector constants
-arm64-strict-align - Disallow all unaligned memory accesses
-arm64-tail-calls - Generate ARM64 tail calls (TEMPORARY OPTION).
-arm64-tbz-offset-bits=<uint> - Restrict range of TB[N]Z instructions (DEBUG)
-arm64-type-promotion - Enable the type promotion pass
-arm64-type-promotion-merge - Enable merging of redundant sexts when one is dominating the other.
-arm64-unscaled-mem-op - Allow ARM64 unscaled load/store combining
-asm-verbose - Add comments to directives.
-avoid-speculation - MachineLICM should avoid speculation
-bb-vectorize-aligned-only - Only generate aligned loads and stores
-bb-vectorize-fast-dep - Use a fast instruction dependency analysis
-bb-vectorize-ignore-target-info - Ignore target information
-bb-vectorize-max-cycle-check-pairs=<uint> - The maximum number of candidate pairs with which to use a full cycle check
-bb-vectorize-max-instr-per-group=<uint> - The maximum number of pairable instructions per group
-bb-vectorize-max-iter=<uint> - The maximum number of pairing iterations
-bb-vectorize-max-pairs-per-group=<uint> - The maximum number of candidate instruction pairs per group
-bb-vectorize-no-bools - Don't try to vectorize boolean (i1) values
-bb-vectorize-no-casts - Don't try to vectorize casting (conversion) operations
-bb-vectorize-no-cmp - Don't try to vectorize comparison instructions
-bb-vectorize-no-floats - Don't try to vectorize floating-point values
-bb-vectorize-no-fma - Don't try to vectorize the fused-multiply-add intrinsic
-bb-vectorize-no-gep - Don't try to vectorize getelementptr instructions
-bb-vectorize-no-ints - Don't try to vectorize integer values
-bb-vectorize-no-math - Don't try to vectorize floating-point math intrinsics
-bb-vectorize-no-mem-op-boost - Don't boost the chain-depth contribution of loads and stores
-bb-vectorize-no-mem-ops - Don't try to vectorize loads and stores
-bb-vectorize-no-pointers - Don't try to vectorize pointer values
-bb-vectorize-no-select - Don't try to vectorize select instructions
-bb-vectorize-pow2-len-only - Don't try to form non-2^n-length vectors
-bb-vectorize-req-chain-depth=<uint> - The required chain depth for vectorization
-bb-vectorize-search-limit=<uint> - The maximum search distance for instruction pairs
-bb-vectorize-splat-breaks-chain - Replicating one element to a pair breaks the chain
-bb-vectorize-use-chain-depth - Use the chain depth requirement with target information
-bb-vectorize-vector-bits=<uint> - The size of the native vector registers
-block-placement-exit-block-bias=<uint> - Block frequency percentage a loop exit block needs over the original exit to be considered the new exit.
-break-anti-dependencies=<string> - Break post-RA scheduling anti-dependencies: "critical", "all", or "none"
-calc-spill-weights-uses-loop-depth - The calculation of spill weights uses loop depth heuristic
-check-vmlx-hazard - Check fp vmla / vmls hazard at isel time
-combiner-alias-analysis - Turn on alias analysis during testing
-combiner-global-alias-analysis - Include global information in alias analysis
-combiner-stress-load-slicing - Bypass the profitability model of load slicing
-da-delinearize - Try to delinearize array references.
-debug-pass - Print PassManager debugging information
=Disabled - disable debug output
=Arguments - print pass arguments to pass to 'opt'
=Structure - print pass structure before run()
=Executions - print pass name before it is executed
=Details - print pass details when it is executed
-dfa-sched-reg-pressure-threshold=<int> - Track reg pressure and switch priority to in-depth
-disable-2addr-hack - Disable scheduler's two-address hack
-disable-a15-sd-optimization - Inhibit optimization of S->D register accesses on A15
-disable-block-placement - Disable probability-driven block placement
-disable-branch-fold - Disable branch folding
-disable-cgp - Disable Codegen Prepare
-disable-cgp-branch-opts - Disable branch optimizations in CodeGenPrepare
-disable-cgp-select2branch - Disable select to branch conversion.
-disable-constant-hoisting - Disable ConstantHoisting
-disable-copyprop - Disable Copy Propagation pass
-disable-debug-info-print - Disable debug info printing
-disable-debug-info-verifier -
-disable-dfa-sched - Disable use of DFA during scheduling
-disable-early-ifcvt - Disable Early If-conversion
-disable-early-taildup - Disable pre-register allocation tail duplication
-disable-ifcvt-diamond -
-disable-ifcvt-simple -
-disable-ifcvt-simple-false -
-disable-ifcvt-triangle -
-disable-ifcvt-triangle-false -
-disable-ifcvt-triangle-false-rev -
-disable-ifcvt-triangle-rev -
-disable-licm-promotion - Disable memory promotion in LICM pass
-disable-lsr - Disable Loop Strength Reduction Pass
-disable-machine-cse - Disable Machine Common Subexpression Elimination
-disable-machine-dce - Disable Machine Dead Code Elimination
-disable-machine-licm - Disable Machine LICM
-disable-machine-sink - Disable Machine Sinking
-disable-peephole - Disable the peephole optimizer
-disable-phi-elim-edge-splitting - Disable critical edge splitting during PHI elimination
-disable-post-ra - Disable Post Regalloc
-disable-postra-machine-licm - Disable Machine LICM
-disable-sched-critical-path - Disable critical path priority in sched=list-ilp
-disable-sched-cycles - Disable cycle-level precision during preRA scheduling
-disable-sched-hazard - Disable hazard detection during preRA scheduling
-disable-sched-height - Disable scheduled-height priority in sched=list-ilp
-disable-sched-live-uses - Disable live use priority in sched=list-ilp
-disable-sched-physreg-join - Disable physreg def-use affinity
-disable-sched-reg-pressure - Disable regpressure priority in sched=list-ilp
-disable-sched-stalls - Disable no-stall priority in sched=list-ilp
-disable-sched-vrcycle - Disable virtual register cycle interference checks
-disable-shifter-op - Disable isel of shifter-op
-disable-spill-fusing - Disable fusing of spill code into instructions
-disable-spill-hoist - Disable inline spill hoisting
-disable-ssc - Disable Stack Slot Coloring
-disable-tail-duplicate - Disable tail duplication
-dwarf-accel-tables - Output prototype dwarf accelerator tables.
=Default - Default for platform
=Enable - Enabled
=Disable - Disabled
-dwarf-version=<uint> - Generate DWARF for dwarf version.
-early-ifcvt-limit=<uint> - Maximum number of instructions per speculated block.
-early-live-intervals - Run live interval analysis earlier in the pipeline
-enable-aa-sched-mi - Enable use of AA during MI GAD construction
-enable-abc-hoisting -
-enable-abcopts -
-enable-andcmp-sinking - Enable sinkinig and/cmp into branches.
-enable-arm-3-addr-conv - Enable ARM 2-addr to 3-addr conv
-enable-bc-uselist-preserve - Turn on experimental support for use-list order preservation.
-enable-block-placement-stats - Collect probability-driven block placement stats
-enable-copyforwarding -
-enable-correct-eh-support - Make the -lowerinvoke pass insert expensive, but correct, EH code
-enable-double-float-shrink - Enable unsafe double to float shrinking for math lib calls
-enable-if-conversion - Enable if-conversion during vectorization.
-enable-legalize-types-checking -
-enable-load-pre -
-enable-lsr-phielim - Enable LSR phi elimination
-enable-mem-access-versioning - Enable symblic stride memory access versioning
-enable-misched - Enable the machine instruction scheduling pass.
-enable-objc-arc-opts - enable/disable all ARC Optimizations
-enable-patchpoint-liveness - Enable PatchPoint Liveness Analysis Pass
-enable-pre -
-enable-rc-id-analysis -
-enable-selectiondag-sp -
-enable-stackmap-liveness - Enable StackMap Liveness Analysis Pass
-enable-static-init -
-enable-tail-merge -
-enable-tbaa -
-error-reporting-is-cold - Treat error-reporting calls as cold
-expand-all-fp-mlx -
-expand-limit=<uint> -
-fast-isel - Enable the "fast" instruction selector
-fast-isel-abort - Enable abort calls when "fast" instruction selection fails to lower an instruction
-fast-isel-abort-args - Enable abort calls when "fast" instruction selection fails to lower a formal argument
-fast-isel-verbose - Enable verbose messages in the "fast" instruction selector
-fatal-assembler-warnings - Consider warnings as error
-fdata-sections - Emit data into separate sections
-ffunction-sections - Emit functions into separate sections
-force-align-stack - Force align the stack to the minimum alignment needed for the function.
-force-ssa-updater -
-force-vector-unroll=<uint> - Sets the vectorization unroll count. Zero is autoselect.
-force-vector-width=<uint> - Sets the SIMD width. Zero is autoselect.
-generate-cu-hash - Add the CU hash as the dwo_id.
-generate-dwarf-cu-ranges - Generate DW_AT_ranges for compile units
-generate-dwarf-pub-sections - Generate DWARF pubnames and pubtypes sections
=Default - Default for platform
=Enable - Enabled
=Disable - Disabled
-generate-gnu-dwarf-pub-sections - Generate GNU-style pubnames and pubtypes
-generate-type-units - Generate DWARF4 type units.
-global-merge - Enable global merge pass
-global-merge-on-const - Enable global merge pass on constants
-help - Display available options (-help-hidden for more)
-help-hidden - Display all available options
-help-list - Display list of available options (-help-list-hidden for more)
-help-list-hidden - Display list of all available options
-ifcvt-branch-fold -
-ifcvt-fn-start=<int> -
-ifcvt-fn-stop=<int> -
-ifcvt-limit=<int> -
-info-output-file=<filename> - File to append -stats and -timer output to
-inline-threshold=<int> - Control the amount of inlining to perform (default = 225)
-inlinecold-threshold=<int> - Threshold for inlining functions with cold attribute
-inlinehint-threshold=<int> - Threshold for inlining functions with inline hint
-internalize-public-api-file=<filename> - A file containing list of symbol names to preserve
-internalize-public-api-list=<list> - A list of symbol names to preserve
-join-globalcopies - Coalesce copies that span blocks (default=subtarget)
-join-liveintervals - Coalesce copies (default=true)
-join-splitedges - Coalesce copies on split edges (default=subtarget)
-jump-threading-threshold=<uint> - Max block size to duplicate for jump threading
-lcr-max-depth=<uint> - Last chance recoloring max depth
-lcr-max-interf=<uint> - Last chance recoloring maximum number of considered interference at a time
-likely-branch-weight=<uint> - Weight of the branch likely to be taken (default = 64)
-limit-float-precision=<uint> - Generate low-precision inline sequences for some float libcalls
-liv-reduce - Reduce live induction variables.
-live-debug-variables - Enable the live debug variables pass
-loop-unswitch-threshold=<uint> - Max loop size to unswitch
-machine-sink-split - Split critical edges during machine sinking
-mark-data-regions - Mark code section jump table data regions.
-max-recurse-depth=<uint> - Max recurse depth (default = 1000)
-max-reroll-increment=<uint> - The maximum increment for loop rerolling
-max-sched-reorder=<int> - Number of instructions to allow ahead of the critical path in sched=list-ilp
-mc-x86-disable-arith-relaxation - Disable relaxation of arithmetic instruction for X86
-misched - Machine instruction scheduler to use
=default - Use the target's default scheduler choice.
=converge - Standard converging scheduler.
=ilpmax - Schedule bottom-up for max ILP
=ilpmin - Schedule bottom-up for min ILP
-misched-bench - Migrate from the target's default SD scheduler to MI scheduler
-misched-bottomup - Force bottom-up list scheduling
-misched-cluster - Enable load clustering.
-misched-cyclicpath - Enable cyclic critical path analysis.
-misched-fusion - Enable scheduling for macro fusion.
-misched-postra - Run MachineScheduler post regalloc (independent of preRA sched)
-misched-regpressure - Enable register pressure scheduling.
-misched-topdown - Force top-down list scheduling
-no-stack-coloring - Disable stack coloring
-no-stack-slot-sharing - Suppress slot sharing during stack coloring
-old-thumb2-ifcvt - Use old-style Thumb2 if-conversion heuristics
-optimize-regalloc - Enable optimized register allocation compilation path.
-phi-elim-split-all-critical-edges - Split all critical edges during PHI elimination
-phi-node-folding-threshold=<uint> - Control the amount of phi node folding to perform (default = 1)
-post-RA-scheduler - Enable scheduling after register allocation
-postra-sched-debugdiv=<int> - Debug control MBBs that are scheduled
-postra-sched-debugmod=<int> - Debug control MBBs that are scheduled
-pre-RA-sched - Instruction schedulers available (before register allocation):
=list-ilp - Bottom-up register pressure aware list scheduling which tries to balance ILP and register pressure
=list-hybrid - Bottom-up register pressure aware list scheduling which tries to balance latency and register pressure
=source - Similar to list-burr but schedules in source order when possible
=list-burr - Bottom-up register reduction list scheduling
=default - Best scheduler for the target
=vliw-td - VLIW scheduler
-print-after - Print IR after specified passes
-print-after-all - Print IR after each pass
-print-all-options - Print all option values after command line parsing
-print-before - Print IR before specified passes
-print-before-all - Print IR before each pass
-print-failed-fuse-candidates - Print instructions that the allocator wants to fuse, but the X86 backend currently can't
-print-gc - Dump garbage collector data
-print-isel-input - Print LLVM IR input to isel pass
-print-lsr-output - Print LLVM IR produced by the loop-reduce pass
-print-machineinstrs=<pass-name> - Print machine instrs
-print-options - Print non-default options after command line parsing
-protect-from-escaped-allocas - Do not optimize lifetime zones that are broken
-regalloc - Register allocator to use
=default - pick register allocator based on -O option
=fast - fast register allocator
=greedy - greedy register allocator
-regalloc-csr-first-time-cost=<uint> - Cost for first time use of callee-saved register.
-remat-pic-stub-load - Re-materialize load from stub in PIC mode
-reroll-loops - Run the loop rerolling pass
-sched-avg-ipc=<uint> - Average inst/cycle whan no target itinerary exists.
-sched-high-latency-cycles=<int> - Roughly estimate the number of cycles that 'long latency'instructions take for targets with no itinerary
-scheditins - Use InstrItineraryData for latency lookup
-schedmodel - Use TargetSchedModel for latency lookup
-show-mc-encoding - Show encoding in .s output
-show-mc-inst - Show instruction structure in .s output
-sil-abcopts-report -
-sil-looprotate -
-sil-print-no-color - Don't use color when printing SIL
-sil-print-only-function=<string> - Only print out the sil for this function
-sil-view-cfg - Enable the sil cfg viewer pass
-simplifycfg-dup-ret - Duplicate return instructions into unconditional branches
-simplifycfg-hoist-cond-stores - Hoist conditional stores if an unconditional store preceeds
-simplifycfg-sink-common - Sink common instructions down to the end block
-slp-threshold=<int> - Only vectorize if you gain more than this number
-slp-vectorize-hor - Attempt to vectorize horizontal reductions
-slp-vectorize-hor-store - Attempt to vectorize horizontal reductions feeding into a store
-spill-uses-loop-depth - Spill uses loop depth heuristic
-spiller - Spiller to use: (default: standard)
=trivial - trivial spiller
=inline - inline spiller
-split-dwarf - Output DWARF5 split debug info.
=Default - Default for platform
=Enable - Enabled
=Disable - Disabled
-split-spill-mode - Spill mode for splitting live ranges
=default - Default
=size - Optimize for size
=speed - Optimize for speed
-ssc-dce-limit=<int> -
-stats - Enable statistics output from program (available with Asserts)
-stress-early-ifcvt - Turn all knobs to 11
-stress-regalloc=<N> - Limit all regclasses to N registers
-swift-partial-update-clearance=<uint> - Clearance before partial register updates
-t2-reduce-limit=<int> -
-t2-reduce-limit2=<int> -
-t2-reduce-limit3=<int> -
-tail-dup-limit=<uint> -
-tail-dup-size=<uint> - Maximum instructions to consider tail duplicating
-tail-dup-verify - Verify sanity of PHI instructions during taildup
-tail-merge-size=<uint> - Min number of instructions to consider tail merging
-tail-merge-threshold=<uint> - Max number of predecessors to consider tail merging
-time-passes - Time each pass, printing elapsed time for each on exit
-track-memory - Enable -time-passes memory tracking (this may be slow)
-twoaddr-reschedule - Coalesce copies by rescheduling (default=true)
-unlikely-branch-weight=<uint> - Weight of the branch unlikely to be taken (default = 4)
-unroll-allow-partial - Allows loops to be partially unrolled until -unroll-threshold loop size is reached.
-unroll-count=<uint> - Use this unroll count for all loops, for testing purposes
-unroll-runtime - Unroll loops with run-time trip counts
-unroll-threshold=<uint> - The cut-off point for automatic loop unrolling
-use-gvn-after-vectorization - Run GVN instead of Early CSE after vectorization passes
-use-mbpi - use Machine Branch Probability Info
-use-new-sroa - Enable the new, experimental SROA pass
-use-unknown-locations - Make an absence of debug location information explicit.
-vectorize-loops - Run the Loop vectorization passes
-vectorize-slp - Run the SLP vectorization passes
-vectorize-slp-aggressive - Run the BB vectorization passes
-vectorizer-min-trip-count=<uint> - Don't vectorize loops with a constant trip count that is smaller than this value.
-verify-arm-pseudo-expand - Verify machine code after expanding ARM pseudos
-verify-coalescing - Verify machine instrs before and after register coalescing
-verify-dom-info - Verify dominator info (time consuming)
-verify-indvars - Verify the ScalarEvolution result after running indvars
-verify-loop-info - Verify loop info (time consuming)
-verify-machineinstrs - Verify generated machine code
-verify-misched - Verify machine instrs before and after machine scheduling
-verify-regalloc - Verify during register allocation
-verify-scev - Verify ScalarEvolution's backedge taken counts (slow)
-version - Display the version of this program
-view-background - Execute graph viewer in the background. Creates tmp file litter.
-view-edge-bundles - Pop up a window to show edge bundle graphs
-warn-stack-size=<uint> - Warn for stack size bigger than the given number
-widen-vmovs - Widen ARM vmovs to vmovd when possible
-x86-asm-syntax - Choose style of code to emit from X86 backend:
=att - Emit AT&T-style assembly
=intel - Emit Intel-style assembly
-x86-early-ifcvt - Enable early if-conversion on X86
-x86-use-base-pointer - Enable use of a base pointer for complex stack frames
-x86-use-vzeroupper - Minimize AVX to SSE transition penalty
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