addisonElliott

{
  "name": "bull-jest-issue",
  "version": "1.0.0",
  "description": "",
  "main": "index.js",
  "scripts": {
    "test": "jest"
  },
  "author": "",
  "license": "ISC",

addisonElliott

x({
    src: './PATS/PATS_1-%ww.%e',
    exts: ['png', 'webp'],
    widths: [420, 370, 298, 277, 223, 168, 139, 105],
    sizes: '177px', // 250px * 0.710 aspect ratio
    aspectRatio: 0.71,
    alt: 'Splash screen / logo'
  }),

addisonElliott

import nrrd
import time
import numpy as np

print('Reading 1KB data file with 1MB chunk size')
print('---------------------')
start = time.perf_counter()
nrrd.reader._READ_CHUNKSIZE = 2 ** 20
nrrd.read('C:/Users/Addison/Documents/PythonProjects/pynrrd/nrrd/tests/data/BallBinary30x30x30_byteskip_minus_one_nifti.nhdr')
end = time.perf_counter()

addisonElliott

import nrrd

fakeData = np.zeros((320, 260, 215), dtype=np.uint8)
fakeData[100:200, 200:300, 50:64] = 255

nrrd.write('test1.nrrd', fakeData)

# This should be L5 which for Subject0001_Final has a L5 at 50 and L4 is at 64, so that means 50-63 should be L5. (64 means where to stop in numpy array)
# Since this is a cube, trapezoidal integration should just yield the same values in between because nothing changes
# So, square area for each slice should be area = (200 - 100) * (300 - 200) * 1.40625^2 = 19775.390625mm^2

addisonElliott

import numpy as np
from scipy.signal import upfirdn

# This is the 1D array that you want to interpolate between
# In this case, it is just 1-15 counting by 1. (16 is one plus stop value)
# MAINLY NEED TO CHANGE THIS AND UPSAMPLING FACTOR
oneDArray = np.arange(1, 16)

# METHOD 1
# ------------

addisonElliott

MiSTer provides an on-screen display (OSD) that can be pulled up by pressing F12 on your keyboard. For each core that is loaded, this menu can be configured to add specific options for that core.

The top-level module for the cores is emu. Note that this does NOT mean emu is the top-level module for the project, but rather it is the top-level module for our purposes. The emu module is typically found in the SystemVerilog file (.sv extension) with the same name as the project. As an example, the Arcade-Galaga project has it's top-level module at Arcade-Galaga.sv.

The configuration string is stored in the variable CONF_STR. This variable is passed to the hps_io module that handles sending it to the processor to be read when necessary.

Each line of the configuration string is delineated with a semi-colon. The first line is the core name followed by two semi-colons.

Here are the follow valid options for the menu:

• T - Trigger button. This is simple a button that will trigger or go HIGH and the

addisonElliott

require("../util/errorCodes.js");

Parse.Cloud.define("login", function(request, response) 
{
    if (request.user == null)
    {
        response.error(Parse.Error.OPERATION_FORBIDDEN, "You must be logged on to call this function.");
        return;
    }

addisonElliott

First, if you are on Windows and find some of these commands are not found in the EDS Command Shell, then you may need to add your Quartus path. I did this by editing the env.sh file and adding the following line:

export QUARTUS_ROOTDIR_OVERRIDE="/cygdrive/c/intelFPGA_lite/16.1/quartus"

From here, someone could easily make a script for their project that allows for easily making and building all the necessary items.

Qsys

For editing Qsys run the following command. Change soc_system.qsys to your Qsys file or leave blank if you do not have one.

addisonElliott

Windows

• Make sure to run Cygwin with Administrator permissions! To get a list of partitions, run: cat /proc/partitions

It should list off your partitions. It will map them to the letter drives so you can find out which device is yours. In my case, my drive was /dev/sdc1.

For Cygwin, check if fdisk is installed: fdisk --help. If it is not found, you will probably need to add /usr/sbin to your path in Cygwin. You can do this by adding export PATH="/sbin:/usr/sbin:$PATH" to .bash_profile (vi is installed by default on Cygwin). Running fdisk --help now should work.

addisonElliott

I successfully created a project instantiating the HPS in Qsys. I added a parallel I/O in Qsys to allow the HPS to communicate with the LEDs via the HPS-to-FPGA lightweight bus. From there, I generated a preloader and U-boot along with the SOF file. I also wrote a simple C program that counts from 0-15 and sets the LEDs to that value every second. This encompasses about every step required to be able to communicate between the FPGA and HPS, so this is definitely a first step. I'm going to document what I did and how you guys can get this running.

I did this on Windows since that is my primary OS. Things are different on Linux, so you will have to figure them out if you try to do this on Linux.

File Structure

DE10NanoUART-FPGA

• Project containing everything necessary to get exactly what I have running
• HPS_FPGA_LED - Source code and makefile for the C program to blink LEDs
• hps_isw_handoff - ISW stands for Initial SoftWare so it is the first thing to be ran AFTER the hardcoded bootrom is loa