test.v

  mem = 0;
  mem_write = 'x;
  mem_width = instruction[13:12];
  mem_unsigned = instruction[14];

  (*full_case, parallel_case*)
  case ({instruction[6:2]})
  5'b01100: begin
  end
  5'b00100: begin
  end
  5'b00000: begin
    mem = 1;
    mem_write = 0;
  end
  5'b01000: begin
    mem = 1;
    mem_write = 1;
  end
  5'b11000: begin
  end
  5'b11011: begin
  end
  5'b11001: begin
  end
  5'b01101: begin
  end
  5'b00101: begin
  end
  endcase