smth.ys

read_verilog -specify -lib +/gowin/cells_sim.v

read_verilog mux8.v uart.v au.v lu.v cu.v alu.v decoder.v immdecoder.v furv.v ram.v shifter.v rom_sim.v led.v top.v

hierarchy -top top

proc
techmap t:*shift*

flatten *uart*
memory -nomap *uart*
opt -fine -full *uart*
techmap -map +/techmap.v *uart*
abc -lut 4 *uart*

alumacc *au*
share -aggressive *au*
opt -full -fine *au*

alumacc cu

share -aggressive shifter;
opt -fine -full shifter

flatten
memory -nomap
opt -fast -mux_bool -undriven -fine
pmuxtree
techmap t:*mux*
muxcover -mux4 -nodecode
opt -fine -full

techmap -map rom.v -autoproc
synth_gowin -nobram -noflatten -abc9
# synth_gowin
# memory
# opt -fast
# techmap -map +/techmap.v
# abc -lut 4:8
# techmap -map +/gowin/cells_map.v

stat
write_json myrv.json