test.v

  sel_a_pc = 0;
  sel_b_imm = 1;
  mem = 0;
  mem_write = 'x;
  mem_width = instruction[13:12];
  mem_unsigned = instruction[14];

  (* full_case *)
  case ({instruction[6:2]})
  5'b01100: begin
    sel_b_imm = 0;
    wb_sel = 2;
  end
  5'b00100: begin
    wb_sel = 2;
    de_rs2_index = 0;
  end
  5'b00000: begin
    mem = 1;
    mem_write = 0;

    wb_sel = 0;
    alu_sel = 1;
    alu_op = 0;
    de_rs2_index = 0;
  end
  5'b01000: begin
    mem = 1;
    mem_write = 1;

    wb_sel = 0;
    alu_sel = 1;
    alu_op = 0;
  end
  5'b11000: begin
    sel_a_pc = 1;
    wb_sel = 2;
    alu_sel = 1;
    alu_op = 0;
  end
  5'b11011: begin
    sel_a_pc = 1;
    wb_sel = 1;
    alu_sel = 1;
    alu_op = 0;
    de_rs2_index = 0;
  end
  5'b11001: begin
    wb_sel = 2;
    alu_sel = 1;
    alu_op = 0;
    de_rs2_index = 0;
  end
  5'b01101: begin
    wb_sel = 2;
    alu_sel = 2;
    alu_op = 0;
    de_rs2_index = 0;
  end
  5'b00101: begin
    sel_a_pc = 1;
    wb_sel = 2;
    alu_sel = 1;
    alu_op = 1;
    de_rs2_index = 0;
  end
  endcase