gistfile1.txt

initial context bits: 00000000.00000000.00000000.00000000
resolving constructor for instruction bytes at: ram:0462
decide on instruction bits: byte-offset=0, bitrange=(7,7), value=0x0, bytes=0001010(0)
   decendent constructors for decision node (complete tree dump ordered by line number):
   : {line# 47} <instruction>
   : {line# 49} <instruction>
   : {line# 153} AND <A>, <ASMEMOP>
   : {line# 209} DEC <BITOP>
   : {line# 215} HALT
   : {line# 220} INC <BITOP>
   : {line# 226} IRET
   : {line# 244} JRET <ADDROP>
   : {line# 248} LD <A>, <ASMEMOP>
   : {line# 258} LD <X>, <XSMEMOP>
   : {line# 268} LD <Y>, <YSMEMOP>
   : {line# 308} LD <A>, <S>
   : {line# 318} LD <X>, <S>
   : {line# 323} LD <S>, <X>
   : {line# 328} LD <Y>, <S>
   : {line# 333} LD <S>, <Y>
   : {line# 338} MUL <X>, <A>
   : {line# 349} MUL <Y>, <A>
   : {line# 360} NEG <BITOP>
   : {line# 371} OR <A>, <ASMEMOP>
   : {line# 378} POP <A>
   : {line# 393} POP <CC>
   : {line# 403} PUSH <A>
   : {line# 418} PUSH <CC>
   : {line# 429} RCF
   : {line# 440} RIM
   : {line# 454} RRC <BITOP>
   : {line# 464} RSP
   : {line# 468} SBC <A>, <ASMEMOP>
   : {line# 484} SLL <BITOP>
   : {line# 501} SRL <BITOP>
   : {line# 509} SUB <A>, <ASMEMOP>
   : {line# 517} SWAP <BITOP>
   : {line# 554} XOR <A>, <ASMEMOP>
   : {line# 747} BSET <imm8>, #<bit_position>
   : {line# 761} BTJT <imm8>, #<bit_position>, <REL>
decide on instruction bits: byte-offset=0, bitrange=(0,0), value=0x0, bytes=(0)0010100
   decendent constructors for decision node (complete tree dump ordered by line number):
   : {line# 209} DEC <BITOP>
   : {line# 220} INC <BITOP>
   : {line# 338} MUL <X>, <A>
   : {line# 349} MUL <Y>, <A>
   : {line# 360} NEG <BITOP>
   : {line# 454} RRC <BITOP>
   : {line# 484} SLL <BITOP>
   : {line# 501} SRL <BITOP>
   : {line# 517} SWAP <BITOP>
   : {line# 747} BSET <imm8>, #<bit_position>
   : {line# 761} BTJT <imm8>, #<bit_position>, <REL>
decide on instruction bits: byte-offset=0, bitrange=(4,6), value=0x2, bytes=0001(010)0
   decendent constructors for decision node (complete tree dump ordered by line number):
   : {line# 501} SRL <BITOP>
   : {line# 747} BSET <imm8>, #<bit_position>
   : {line# 761} BTJT <imm8>, #<bit_position>, <REL>
decide on instruction bits: byte-offset=0, bitrange=(3,3), value=0x1, bytes=000(1)0100
   decendent constructors for decision node (complete tree dump ordered by line number):
   : {line# 501} SRL <BITOP>
   : {line# 747} BSET <imm8>, #<bit_position>
check pattern[1 of 2]: {line# 501} SRL <BITOP>
   byte pattern: mask=10001111.00000000.00000000.00000000
           bytes[0-3]=00010100.00010010.10010010.00010110
          match-value=00000100.00000000.00000000.00000000 Matched
BITOP: resolving...
   decide on instruction bits: byte-offset=0, bitrange=(1,3), value=0x1, bytes=0(001)0100
      decendent constructors for decision node (complete tree dump ordered by line number):
   Unable to resolve constructor

Prototype parse failed: Unable to resolve constructor at 0462
DebugSleighInstructionParse.java> Finished!

   byte pattern: mask=10001111.00000000.00000000.00000000
           bytes[0-3]=00010100.00010010.10010010.00010110

11 12 -> BRES works (0,0)(1,3)(4,7) and (0,3)(4,6)(7,7) ... maybe I'm not thinking this through, is the bit order inverted maybe lo->hi vs hi->lo from how I suggested?

No idea actually... BITOP is defined as such:

define token inst8 (8)
	opcode = (0, 7)
	kind = (0, 3)
	addressing = (4, 7)
	bit_upper = (4, 7)
	bit_lower = (0, 0)
	bit_position = (1, 3)
;

define token immediate8 (8)
	imm8 = (0, 7)
	addr8 = (0, 7)
	rel = (0, 7) signed
;

define token immediate16 (16)
	imm16 = (0, 15)
;

define context contextreg
	# Pre-bytes - see page 30 of the programming manual.
	prefix_90 = (0, 0) noflow  # PDY
	prefix_91 = (1, 1) noflow  # PIY
	prefix_92 = (2, 2) noflow  # PIX
;

@define PRE_PDY	"prefix_90=1 & prefix_91=0 & prefix_92=0"
@define PRE_PIY "prefix_90=0 & prefix_91=1 & prefix_92=0"
@define PRE_PIX "prefix_90=0 & prefix_91=0 & prefix_92=1"
@define NO_PRE "prefix_90=0 & prefix_91=0 & prefix_92=0"

:^instruction	is prefix=0x90; instruction [ prefix_90=1; prefix_91=0; prefix_92=0; ] {}
:^instruction	is prefix=0x91; instruction [ prefix_90=0; prefix_91=1; prefix_92=0; ] {}
:^instruction	is prefix=0x92; instruction [ prefix_90=0; prefix_91=0; prefix_92=1; ] {}

BITOP: A                is $(NO_PRE) & addressing=0x04 & A          { export A; }
BITOP: X                is $(NO_PRE) & addressing=0x05 & X          { export X; }
BITOP: Y                is $(PRE_PDY) & addressing=0x05 & Y         { export Y; }
BITOP: imm8             is $(NO_PRE) & addressing=0x03 ; imm8       { export *:1 imm8; }
BITOP: (X)              is $(NO_PRE) & addressing=0x07 & X          { local address:2 = zext(X); export *:1 address; }
BITOP: (imm8,X)         is $(NO_PRE) & addressing=0x06 & X ; imm8   { local address:2 = imm8 + zext(X); export *:1 address; }
BITOP: (Y)              is $(PRE_PDY) & addressing=0x07 & Y         { local address:2 = zext(Y); export *:1 address; }
BITOP: (imm8,Y)         is $(PRE_PDY) & addressing=0x06 & Y ; imm8  { local address:2 = imm8 + zext(Y); export *:1 address; }
BITOP: [imm8]           is $(PRE_PIX) & addressing=0x03 ; imm8      { local indirect:2 = imm8; local address:1 = *:1 indirect; export *:1 address; }
BITOP: ([imm8],X)       is $(PRE_PIX) & addressing=0x06 & X ; imm8  { local indirect:2 = imm8; local address:1 = *:1 indirect + zext(X); export *:1 address; }
BITOP: ([imm8],Y)       is $(PRE_PIY) & addressing=0x06 & Y ; imm8  { local indirect:2 = imm8; local address:1 = *:1 indirect + zext(Y); export *:1 address; }

and SRL is:

:SRL BITOP is kind=0x04 ... & BITOP {
	local value = BITOP;
	C = value & 1;
	value = value >> 1;
	nzFlags(value);
	BITOP = value;
}

So no idea where the MSB comes from. However when forcing $(NO_PRE) on anything that doesn't involve prefixes things seem to work a bit better so I guess I hit up to three bugs at the same time (error in actions, instruction prefixes blocking compilations, and failed backtracking)? :)