Spartan Edge Blinker project

blinker.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/08/05 11:02:11
// Design Name: 
// Module Name: blinker
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module blinker(
    input sys_clk,
    input [1:0] key,
    output reg[1:0] led
);
parameter REG_SIZE =  24;
parameter TIMER_END0 = 24'd5_000_000;
parameter TIMER_END1 = 24'd15_000_000;

reg [REG_SIZE-1 : 0] counter0 = 0;
reg [REG_SIZE-1 : 0] counter1 = 0;
reg en_out0 = 1'b0;
reg en_out1 = 1'b0;

//wire flag = key[0] & key[1];
always @(posedge sys_clk) begin
     if (counter0 > TIMER_END0) begin
        counter0 <= 0;
        en_out0 <= ~en_out0;
    end else begin
        counter0 <= counter0 + 1;
    end
    
    if (counter1 > TIMER_END1) begin
        counter1 <= 0;
        en_out1 <= ~en_out1;
    end else begin
        counter1 <= counter1 + 1;
    end
        
    if(key[0] & en_out0)
        led[1] <= 1'b0;
    else
        led[1] <= 1'b1;
    
    if (key[1] & en_out1)
        led[0] <= 1'b1;
    else
        led[0] <= 1'b0;
    end
endmodule

blinker_pins.xdc

set_property IOSTANDARD LVCMOS33 [get_ports {key[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {key[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]

set_property PACKAGE_PIN J1 [get_ports led[0]]
set_property PACKAGE_PIN A13 [get_ports led[1]]
set_property PACKAGE_PIN H4 [get_ports sys_clk]
set_property PACKAGE_PIN C3 [get_ports {key[0]}]
set_property PACKAGE_PIN M4 [get_ports {key[1]}]

blinker_test.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/08/06 09:52:07
// Design Name: 
// Module Name: blinker_sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module blinker_sim();

reg clk;
reg [1:0] key_in;
wire [1:0] led_out;       
blinker u_test(
    clk,
    key_in,
    led_out
);      
initial begin 
    clk  = 1'b0;
    key_in = 2'b11;
    #30 key_in = 2'b00;
    #30 key_in = 2'b01;
    #30 key_in = 2'b10;
    #30 key_in = 2'b11;
end        
always #2 clk = ~clk;       
endmodule