Blinkencard project notes

gistfile1.txt

GOALS
- To make a handheld emulator for the historic Altair 8800 that recreates the feel of having blinkenlights
- To learn about FPGA development
ARCHITECTURE
- Hardware:
  - Business card size PCB
    - All components except pushbuttons on the board top
    - LEDs are backfiring and shine through holes in the PCB
    - 4 pushbuttons, heavily multiplexed for front panel control
    - PCB is to be made matte black to mimic panel-mount LED look
    - PCB legend to look similar to Altair 8800 console
  - Emulation runs on Lattice ICE40 UP5K FPGA
    - LED matrix scanned by FPGA
      - 5 banks of 8 bits (8 data, 8 status reg, 16 addr / sense, 8 control)
      - transistor for each bank to drive high side, FPGA sinks low side
    - Internal oscillator
    - Pushbuttons directly connected
    - Boots in SPI receiver mode from ESP32
    - Simplified power supply - 3.3V and 1.2V only, 2.5V needed for OTP unused
    - SPI path between ESP32 for boot can be used for peripheral emulation and debug
    - Emulation UART TX/RX pins brought to ESP32 UART
  - ESP32 for control, storage, IO
    - ESP-WROOM32 module with 4MB flash storage
    - Wifi gives multiple external IO options for bitstream updates, serial console forwarding, and control
    - 4MB flash stores ESP32 code, bitstream, and emulated disk for the target
  - Power
    - 3.3V ldo for ESP32 and FPGA 3.3V rails
    - 1.2V ldo for FPGA 1.2V rails
    - microUSB jack for power input only
    - Jack for LiPo battery
    - Auto switching between LiPo and USB 5V
    - Onboard LiPo charger
    - Assumes LiPo pack with protection board
- Software
  - IceStorm / Yosys / NextPNR toolchain for FPGA
  - Based on the mmicko/s100fpga project
  - MicroPython on the ESP32
LOG
- 12/30/20:
  - Late start to notetaking - but let's go over the state of the project
    - al177/blinkencard repo:
      - KiCad PCB
        - 2 iterations:
          - V1: no ESP32, FPGA boots from SPI flash
            - Had SiLabs USB-to-UART that I thought could be used to program the bitstream on the SPI flash
            - SiLabs part was incapable of bitbang IO and so could not access the SPI flash
            - had intended to also use the SiLabs part for other IO to the FPGA
            - design decision was to shoot for low cost, therefore did not use the 2-3x cost FTDI FT232H or 2232H
            - hacked-on header for access to the SPI flash let me prove out the FPGA design successfully
          - V2: ESP32
            - ESP32 replaces the USB-to-UART and SPI flash
            - ESP32 running MicroPython boots the FPGA directly without a dedicated flash device
            - $4 ESP-WROOM32 module cost is more than made up for by avoiding using an FTDI part
            - Added LiPo battery to make it a self-contained gadget
      - Printed enclosure
        - OpenSCAD project to make a backshell reminiscent of the Altair 8800 chassis
        - has space for a LiPo secured by double sided tape
      - micropython scripts
        - Library for uploading the bitstream to the ICE40UP5K
        - Background task to expose UART over telnet, with escape codes to reset the target and drop to CLI mode in MicroPython
        - Startup script for MicroPython to load a bitstream at boot and run the telnet server and the WebREPL server
        - Startup script also sets up the WiFi as its own AP - users may later change it to connect to another AP instead
    - al177/s100fpga blinkencard branch
      - Updated the i8080 emulation to the more accurate vm80a core
        - Done due to a giant heap of warnings that showed up when switching from Arachne-PNR to NextPNR
      - Added basic8k interpreter instead of the original basic4k
      - Added LED matrix driver to expose the A/D buses and status register (in IO space)
TODO
- Implement SPI control interface on FPGA
  - Backdoor access to memory
  - Control over the virtual front panel switches
  - Read button state
- Implement SPI interface drivers on ESP32
  - Protocol layer module
  - Method to load from file to RAM and vice-versa
  - Method to read STATUS
  - Method to read/write SENSE
  - Method to control execution bits (RUN in particular)
  - Method to generate bus reads and writes
- Switch to using SPRAM instead of block RAM for emulation RAM
  - UP5K has 128KB of single port RAM, we should use it instead of more critical block RAM
  - SPRAM cannot be initialized like BRAM, so we need to use the SPI interface for loading most everything
    - as we currently init BRAM with the TURNMON monitor and 8K BASIC
    - May leave TURNMON in BRAM as it's small and ROM-ish
  - SPI file-to-RAM method would be used immediately after bitstream load to prep RAM
- Server on ESP32 for SPI services
  - Disk read/write emulation to flash file
  - Write CP/M driver to handle this
  - Future ideas: tape emulation, additional UARTs
- Refactor repo
  - Lots of unused targets
- Emulate other similar systems
  - Similar S100 systems like IMSAI 8080
  - Z80 based systems